Subject: Fwd: Accellera FV -- December 2000 Meeting Minutes (Danny Geist)
From: Harry Foster (foster@rsn.hp.com)
Date: Tue Dec 19 2000 - 05:28:30 PST
> From: geist@il.ibm.com
> To: vfv@eda.org
> Date: Tue, 19 Dec 2000 12:16:25 +0200
> Subject: Accellera FV -- December 2000 Meeting Minutes
>
>
> Hi All.
>
> 1. Going over the document line by line like we did last time seems to be
> ineffective - we wont complete the process due to the nature of our
> meetings (large scale conference calls). I suggest that instead, everyone
> read the document and send their comments and reservations and we will
> discuss those in the meeting.
> 2. Heres my view of the usage mode:
> The connection between the SL (spec language) and the HDL will be via a
> common name space. Names that match on both descriptions will be assumed
to
> refer to the same design resource.
> There will be two ways to attach SL code to the HDL
> A. External - An auxiliary SL file will be supplied . The toolset (Model
> Checking, Simulation) will know how to link SL and HDL files together. In
> this case the SL file will be able refer to hierarchical names (e.g.
> Unit_1/Sub_unit_5/Signal_10). In fact if the tools will allow this, it
will
> be possible to mix various HDLs during linkage (e.g. Verilog, SMV, and the
> SL).
> B. Internal: Embedded SL code inside the HDL file. In this case it will
not
> be necessary to specify hierarchy - names in the SL code will refer to
> local resources. This embedded code will probably have to have a wrapping
> around it. I don't see any other way considering it will have to work with
> both Verilog and VHDL.
>
> Danny
>
>
> Daniel Geist
> IBM Haifa Research Lab. Phone:
> 972-4-8296286
> MATAM - Advanced Technology Center Fax: 972-4-8296112
> Haifa, ISRAEL
> e-mail: geist@il.ibm.com
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