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Prior to the release of Verilog-AMS HDL, the OVI board approved an analog-only specification called Verilog-A v1.0. With the release of Verilog-AMS HDL, the "official" Verilog-A LRM is no longer supported as it is included as part of the Verilog-AMS HDL specification. This annex defines a working subset of Verilog-AMS HDL for analog-only products.
C.1 Verilog-AMS introduction
This section previews Verilog-A and its language features.
C.1.1 Verilog-A overview
This Verilog-A subset defines a behavioral language for analog only systems. Verilog-A is derived from the IEEE 1364-1995 Verilog HDL specification using a minimum number of constructs for analog and mixed-signal behavioral descriptions. This Annex is intended to cover the definition and semantics of Verilog-A as proposed by OVI.
The intent of Verilog-A is to let designers of analog systems and integrated circuits create and use modules which encapsulate high-level behavioral descriptions of systems and components. The behavior of each module can be described mathematically in terms of its terminals and external parameters applied to the module. These behavioral descriptions can be used in many disciplines such as electrical, mechanical, fluid dynamics, and thermodynamics.
Verilog-A has been defined to be applicable to both electrical and non-electrical systems description. It supports conservative and signal-flow descriptions by using the terminology for these descriptions using the concepts of nodes, branches, and terminals. The solution of analog behaviors which obey the laws of conservation fall within the generalized form of Kirchhoff's Potential and Flow Laws (KPL and KFL). Both of these are defined in terms of the quantities associated with the analog behaviors.
C.1.2 Verilog-A language features
The Verilog-A subset provides access to a salient set of features of the full modeling language that allow analog designers the ability to model analog systems:
· Verilog-A modules are compatible with Verilog-AMS HDL.
· Analog behavioral modeling descriptions are contained in a separate analog block.
· Branches can be named for easy selection and access.
· Parameters can be specified with valid range limits.
· Systems can be modeled by using expressions consisting of operators, variables, and signals:
1. a full set of operators including trigonometric functions, integrals, and derivatives;
2. a set of waveform filters to modify the waveform results for faster and more accurate simulation like transition, slew, Laplace, and Z-domain;
3. a set of events to control when certain code is simulated;
4. selection of the simulation time step for simulation control;
5. support for accessing SPICE primitives from within the language.
C.2 Lexical conventions
With the exception of certain keywords required for Verilog-AMS HDL, Section 2 is applicable to both Verilog-A and Verilog-AMS HDL. All Verilog-AMS HDL keywords shall be supported by Verilog-A as reserved words, but IEEE 1364-1995 Verilog HDL and Verilog-AMS HDL specific keywords are not used in Verilog-A. The following Verilog-AMS HDL keywords are not required to be supported for a fully compliant Verilog-A subset:
· From 2.5, Numbers: support for X and Z values is limited in the analog block only to mixed-signal, as defined in 8.3.2.
· From 2.6, Strings: support for regs and strings is limited to the digital context only.
· From 2.7.2, Keywords: certain keywords are not applicable in Verilog-A, as defined in C.15.
C.3 Data types
The data types of Section 3 are applicable to both Verilog-AMS HDL and Verilog-A with the following exceptions:
· From 3.4.3.1, Domain binding: the domain binding type discrete shall be an error in Verilog-A.
· From 3.5, Real net declarations: the wreal data type is not supported in Verilog-A.
· From 3.6, Default discipline: the `default_discipline compiler directive is not supported in Verilog-A. All Verilog-A modules shall have a discipline defined for each module.
Note: This feature allows the use of digital modules in Verilog-AMS HDL without editing them to add a discipline.
C.4 Expressions
The expressions defined in Section 4 are applicable to both Verilog-AMS HDL and Verilog-A with the following exception:
The case equality operators (===, !==) are not supported in Verilog-A.
C.5 Signals
The signals defined in Section 5 are applicable to both Verilog-AMS HDL and Verilog-A.
C.6 Analog behavior
The analog behavior defined in Section 6 are applicable to both Verilog-AMS HDL and Verilog-A with the following exceptions:
· No digital behavior or events are supported in Verilog-A.
· casex and casez are not supported in Verilog-A.
C.7 Hierarchical structures
The hierarchical structure defined in Section 7 is applicable to both Verilog-AMS HDL and Verilog-A, except support for real value ports is only applicable to Verilog-AMS HDL and IEEE 1364-1995 Verilog HDL (see 7.3.3).
C.8 Mixed-signal
This section only applies to Verilog-AMS HDL.
C.9 Scheduling semantics
The analog simulation cycle is applicable to both Verilog-AMS HDL and Verilog-A. The mixed signal simulation cycle from 9.2 is only applicable to Verilog-AMS HDL.
C.10 System tasks and functions
The system tasks and functions in Section 10 are applicable to both Verilog-AMS HDL and Verilog-A.
C.11 Compiler directives
The compiler directives of Section 11 are applicable to both Verilog-AMS HDL and Verilog-A.
Verilog-A also supports the `default_function_type_analog directive, which allows user-defined functions to be treated as analog functions in Verilog-A if they do not have the key word analog as part of the definition. This is provided for backwards compatibility.
C.12 Using VPI routines
The analog behavior defined in Section 1 are applicable to both Verilog-AMS HDL and Verilog-A.
C.13 VPI routine definitions
The analog behavior defined in Section 2 are applicable to both Verilog-AMS HDL and Verilog-A.
C.14 Syntax
This annex (Annex C) defines the differences between Verilog-AMS HDL and Verilog-A. Annex A defines the BNF for Verilog-AMS HDL.
C.15 Keywords
The keywords in this annex (Annex B) are the complete set of Verilog-AMS HDL keywords, including those from IEEE 1364-1995 Verilog HDL. The following keywords as defined in this LRM are not used by Verilog-A:
· From B.1, All keywords:
connectmodule
connectrules
driver_update
endconnectrules
net_resolution
wreal
· From B.2, Discipline/nature:
All keywords in this section are supported in Verilog-A.
· From B.3, Connect rules:
connect
merged
split
resolvedto
Note: All keywords of Verilog-AMS HDL are reserved words for Verilog-A.
C.16 Standard definitions
The definitions of Annex D are applicable to both Verilog-AMS HDL and Verilog-A, with the exception of those disciplines with a domain of discrete.
C.17 SPICE compatibility
Annex E defines the SPICE compatibility for both Verilog-A and Verilog-AMS HDL.
C.18 Changes from Verilog-A LRM v1.0
As part of the Verilog-AMS HDL development, some changes and clarifications have occurred to the current Verilog-A subset. Most of the changes resulted in clarifications or additional capability; but some new compatibility issues now exist. This subsection highlights some of the key differences. The syntax and semantics of this document supersede any syntax, semantics, or interpretations of the original document.
Table C.1 list the changed functions.
Feature OVI Verilog-A v1.0 OVI Verilog-AMS v2.0 Change type Analog time $realtime $abstime new Ceiling operator N/A ceil(expr) new Floor operator N/A floor(expr) new Circular integrator N/A idtmod(expr) new Expression looping N/A genvar new Distribution functions $dist_functions() Integer based functions $rdist_functions() Real value equivalents to $dist_functions() new Empty discipline predefined as type wire type not defined default definition Implicit nodes `default_nodetype discipline_identifier default: wire default type: empty discipline, no domain type default definition initial_step default = TRAN default = ALL default definition final_step default = TRAN default = ALL default definition Analog ground no definition now a declaration statement definition $realtime $realtime :timescale =1 sec $realtime :timescale='timescale def=1n, see $abstime definition Array setting aa[0:1] = {2.1 = (1), 4.5 = (2) aa[0:1] = {2.1,4.5} syntax Discontinuity function discontinuity(x) $discontinuity(x) syntax Limiting exponential function $limexp(expression) limexp(expression) syntax Port branch access I(a,a) I(<a>) syntax Timestep control (maximum stepsize) bound_step(const_expression) $bound_step(expr) syntax Continuous waveform delay delay() absdelay() syntax User-defined analog functions function analog functionSee C.11 syntax Discipline domain N/A, assumed continuous now continuous(default) and discrete Extension k scalar (103) N/A, only "K" supported now supported Extension Module keyword module module or macromodule Extension Modulus operator integers only now supports integer and reals Extension Time tolerance on timer functions N/A supports additional time tolerance argument for timer() Extension Time tolerance on transition filter N/A supports additional time tolerance argument for transition() Extension `default_nodetype `default_nodetype `default_discipline Obsolete Forever statement forever N/A Obsolete Generate statement generate N/A Obsolete Null statement ; Limited to case, conditional, and event statements (see syntax) Obsolete
C.19 Obsolete functionality
The following statements are not supported in the current version of Verilog-AMS HDL; they are only noted for backward compatibility.
C.19.1 Forever
This statement is no longer supported.
C.19.2 NULL
This statement is no longer supported. Certain functions such as case, conditionals and the event statement do allow null statements as defined by the syntax.
C.19.3 Generate
The generate statement is a looping construct which is unrolled at elaboration time. It is the only looping statement that can contain analog operators. The syntax of generate statement is shown in Figure C.1.
The index shall not be assigned or modified in any way inside the loop. In addition, it is local to the loop and is expanded when the loop is unrolled. Even if there is a local variable with the same name as the index and the variable is modified as a side effect of a function called from within the loop, the loop index is unaffected.
The start and end bounds and the increment are constant expressions. They are only evaluated at elaboration time. If the expressions used for the increment and bounds change during the simulation, it does not affect the behavior of the generate statement.
If the lower bound is less than the upper bound and the increment is negative, or if the lower bound is greater than the upper bound and the increment is positive, then the generate statement does not execute.
If the lower bound equals the upper bound, the increment is ignored and the statement execute once. If the increment is not given, it is taken to be +1 if the lower bound is less than the upper bound, and -1 if the lower bound is greater than the upper bound.
The statement, which can be a sequential block, is replicated with all occurrences of index in the statement replaced by a constant. In the first instance of the statement, the index is replaced with the lower bound. In the second, it is replaced by the lower bound plus the increment. In the third, it is replaced by the lower bound plus two times (2x) the increment. This pattern is repeated until the lower bound plus a multiple of the increment is greater than the upper bound.
Examples:
This module implements a continuously running (unclocked) analog-to-digital converter.
module adc(in,out) ;
parameter bits=8, fullscale=1.0, dly=0.0, ttime=10n;
input in;
output [0:bits-1] out;
electrical in;
electrical [0:bits-1] out;
real sample, thresh;
analog begin
thresh = fullscale/2.0;
generate i (bits-1,0) begin
V(out[i]) <+ transition(sample > thresh, dly, ttime);
if (sample > thresh) sample = sample - thresh;
sample = 2.0*sample;
end
end
endmodule
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