1 Verilog-AMS introduction 1-1
1.1 Overview 1-1
1.2 Mixed-signal language features 1-2
1.3 Systems 1-3
1.3.1 Conservative systems 1-4
1.3.2 Kirchhoff's Laws 1-5
1.3.3 Natures, disciplines, and nets 1-6
1.3.4 Signal-flow systems 1-6
1.3.5 Mixed conservative/signal flow systems 1-7
1.4 Conventions used in this document 1-10
1.5 Contents 1-11
2 Lexical conventions 2-1
2.1 Lexical tokens 2-1
2.2 White space 2-1
2.3 Comments 2-2
2.4 Operators 2-2
2.5 Numbers 2-2
2.5.1 Integer constants 2-3
2.5.2 Real constants 2-3
2.5.3 Scale factors for real constants 2-4
2.6 Strings 2-5
2.6.1 String variable declaration 2-5
2.6.2 String manipulation 2-5
2.6.3 Special characters in strings 2-6
2.7 Identifiers, keywords, and system names 2-6
2.7.1 Escaped identifiers 2-7
2.7.2 Keywords 2-7
2.7.3 System tasks and functions 2-7
2.7.4 Compiler directives 2-8
3 Data types 3-1
3.1 Integer and real data types 3-1
3.2 Parameters 3-2
3.2.1 Type specification 3-4
3.2.2 Value range specification 3-4
3.2.3 Parameter arrays 3-5
3.3 Genvars 3-5


3.4 Net_discipline 3-6
3.4.1 Natures 3-7
3.4.2 Disciplines 3-10
3.4.3 Multi-disciplinary example 3-12
3.4.4 Net discipline declaration 3-15
3.4.5 Ground declaration 3-16
3.4.6 Implicit nets 3-17
3.5 Real net declarations 3-17
3.6 Default discipline 3-18
3.7 Discipline precedence 3-19
3.8 Net compatibility 3-20
3.9 Branches 3-22
3.10 Namespace 3-23
3.10.1 Nature and discipline 3-23
3.10.2 Access functions 3-23
3.10.3 Net 3-24
3.10.4 Branch 3-24
4 Expressions 4-1
4.1 Operators 4-1
4.1.1 Operators with real operands 4-2
4.1.2 Binary operator precedence 4-3
4.1.3 Expression evaluation order 4-4
4.1.4 Arithmetic operators 4-4
4.1.5 Relational operators 4-5
4.1.6 Case equality operators 4-6
4.1.7 Logical equality operators 4-6
4.1.8 Logical operators 4-6
4.1.9 Bit-wise operators 4-7
4.1.10 Shift operators 4-8
4.1.11 Conditional operator 4-8
4.1.12 Event or 4-8
4.1.13 Concatenations 4-8
4.2 Built-in mathematical functions 4-9
4.2.1 Standard mathematical functions 4-9
4.2.2 Transcendental functions 4-10
4.2.3 Error handling 4-11
4.3 Signal access functions 4-11
4.4 Analog operators 4-12
4.4.1 Restrictions on analog operators 4-12
4.4.2 Vector or array arguments to analog operators 4-13
4.4.3 Analog operators and equations 4-13
4.4.4 Time derivative operator 4-13
4.4.5 Time integral operator 4-14
4.4.6 Circular integrator operator 4-15
4.4.7 Absolute delay operator 4-16
4.4.8 Transition filter 4-17
4.4.9 Slew filter 4-21
4.4.10 last_crossing function 4-22
4.4.11 Laplace transform filters 4-23
4.4.12 Z-transform filters 4-25
4.4.13 Limited exponential 4-28
4.4.14 Constant versus dynamic arguments 4-29
4.5 Analysis dependent functions 4-29
4.5.1 Analysis 4-30
4.5.2 AC stimulus 4-31
4.5.3 Noise 4-31
4.6 User-defined functions 4-33
4.6.1 Defining an analog function 4-33
4.6.2 Returning a value from an analog function 4-35
4.6.3 Calling an analog function 4-35
5 Signals 5-1
5.1 Analog signals 5-1
5.1.1 Access functions 5-1
5.1.2 Probes and sources 5-2
5.1.3 Examples 5-3
5.1.4 Port branches 5-5
5.1.5 Switch branches 5-6
5.1.6 Unassigned sources 5-7
5.2 Signal access for vector branches 5-7
5.2.1 Accessing net and branch signals 5-9
5.2.2 Accessing attributes 5-10
5.3 Contribution statements 5-10
5.3.1 Branch contribution statements 5-10
5.3.2 Indirect branch assignments 5-13
6 Analog behavior 6-1
6.1 Analog procedural block 6-1
6.2 Block statements 6-2
6.2.1 Sequential blocks 6-2
6.2.2 Block names 6-3
6.3 Procedural assignments 6-3
6.4 Conditional statement 6-4
6.4.1 Examples 6-4
6.4.2 Analog conditional statements 6-5


6.5 Case statement 6-5
6.5.1 Analog case statements 6-6
6.5.2 Constant expression in case statement 6-7
6.6 Looping statements 6-7
6.6.1 Repeat and while statements 6-7
6.6.2 For statements 6-8
6.7 Events 6-9
6.7.1 Event detection 6-9
6.7.2 Event OR operator 6-10
6.7.3 Event triggered statements 6-11
6.7.4 Global events 6-11
6.7.5 Monitored events 6-13
7 Hierarchical structures 7-1
7.1 Modules 7-1
7.1.1 Toplevel modules 7-3
7.1.2 Module instantiation 7-3
7.2 Overriding module parameter values 7-6
7.2.1 Defparam statement 7-6
7.2.2 Module instance parameter value assignment by order 7-8
7.2.3 Module instance parameter value assignment by name 7-8
7.2.4 Parameter dependence 7-9
7.3 Ports 7-9
7.3.1 Port association 7-9
7.3.2 Port declarations 7-10
7.3.3 Real valued ports 7-11
7.3.4 Connecting module ports by ordered list 7-12
7.3.5 Connecting module ports by name 7-13
7.3.6 Port connection rules 7-14
7.3.7 Inheriting port natures 7-14
7.4 Hierarchical names 7-14
7.5 Scope rules 7-16
8 Mixed-signal 8-1
8.1 Introduction 8-1
8.2 Fundamentals 8-2
8.2.1 Domains 8-2
8.2.2 Contexts 8-2
8.2.3 Nets, nodes, ports, and signals 8-2
8.2.4 Mixed-signal and net disciplines 8-3
8.3 Behavioral interaction 8-4
8.3.1 Accessing discrete nets and variables from a continuous context 8-4
8.3.2 Accessing X and Z bits of a discrete net in a continuous context 8-6
8.3.3 Accessing continuous nets and variables from a discrete context 8-6
8.3.4 Detecting discrete events in a continuous context 8-7
8.3.5 Detecting continuous events in a discrete context 8-8
8.3.6 Concurrency 8-9
8.3.7 Function calls 8-11
8.4 Discipline resolution 8-11
8.4.1 Compatible discipline resolution 8-11
8.4.2 Connection of discrete-time disciplines 8-12
8.4.3 Connection of continuous-time disciplines 8-12
8.4.4 Resolution of mixed-signals 8-12
8.5 Connect modules 8-16
8.6 Connect module descriptions 8-16
8.7 Connect specification statements 8-18
8.7.1 Connect module auto-insertion statement 8-18
8.7.2 Discipline resolution connect statement 8-20
8.7.3 Parameter passing attribute 8-20
8.7.4 connect_mode 8-20
8.8 Automatic insertion of connect modules 8-20
8.8.1 Connect module selection 8-22
8.8.2 Signal segmentation 8-24
8.8.3 connect_mode parameter 8-26
8.8.4 Rules for driver-receiver segregation and connect module selection
and insertion 8-30
8.8.5 Instance names for auto-inserted instances 8-31
8.9 Driver-receiver segregation 8-32
8.10 Driver access and net resolution 8-34
8.10.1 $driver_count 8-35
8.10.2 $driver_state 8-35
8.10.3 $driver_strength 8-35
8.10.4 driver_update 8-36
8.10.5 net_resolution 8-36
8.10.6 Connect module example using driver access functions 8-37
8.11 Supplementary driver access functions 8-38
8.11.1 $driver_delay 8-39
8.11.2 $driver_next_state 8-39
8.11.3 $driver_next_strength 8-39
9 Scheduling semantics 9-1
9.1 Analog simulation cycle 9-1
9.1.1 Nodal analysis 9-1
9.1.2 Transient analysis 9-2
9.1.3 Convergence 9-3
9.2 Mixed-signal simulation cycle 9-4
9.2.1 Circuit initialization 9-5
9.2.2 Transient analysis & A/D algorithm synchronization 9-5
9.2.3 The synchronization loop 9-6
9.2.4 Assumptions about the analog and digital algorithms 9-7
10 System tasks and functions 10-1
10.1 Environment parameter functions 10-1
10.2 $random function 10-2
10.3 $dist_ functions 10-2
10.4 Simulation control system tasks 10-4
10.4.1 $finish 10-4
10.4.2 $stop 10-4
10.5 File operation tasks 10-5
10.5.1 $fopen 10-5
10.5.2 $fclose 10-5
10.6 Display tasks 10-5
10.6.1 Escape sequences for special characters 10-6
10.6.2 Format specifications 10-7
10.6.3 Hierarchical name format 10-8
10.6.4 String format 10-8
10.7 Announcing discontinuity 10-8
10.8 Time related functions 10-10
11 Compiler directives 11-1
11.1 `default_discipline 11-1
11.2 `default_transition 11-2
11.3 `define and `undef 11-2
11.3.1 `define 11-2
11.3.2 `undef 11-4
11.4 `ifdef, `else, `endif 11-5
11.5 `include 11-6
11.6 `resetall 11-7
11.7 Predefined macros 11-7
12 Using VPI routines 12-1
12.1 The VPI interface 12-1
12.1.1 VPI callbacks 12-1
12.1.2 VPI access to Verilog-AMS HDL objects and simulation objects 12-2
12.1.3 Error handling 12-2
12.2 VPI object classifications 12-2
12.2.1 Accessing object relationships and properties 12-3
12.2.2 Delays and values 12-4
12.3 List of VPI routines by functional category 12-5


12.4 Key to object model diagrams 12-7
12.4.1 Diagram key for objects and classes 12-8
12.4.2 Diagram key for accessing properties 12-9
12.4.3 Diagram key for traversing relationships 12-10
12.5 Object data model diagrams 12-11
12.5.1 Module 12-12
12.5.2 Nature, discipline 12-13
12.5.3 Scope, task, function, IO declaration 12-14
12.5.4 Ports 12-15
12.5.5 Nodes 12-16
12.5.6 Branches 12-17
12.5.7 Quantities 12-18
12.5.8 Nets 12-19
12.5.9 Regs 12-20
12.5.10 Variables, named event 12-21
12.5.11 Memory 12-22
12.5.12 Parameter, specparam 12-23
12.5.13 Primitive, prim term 12-24
12.5.14 UDP 12-25
12.5.15 Module path, timing check, intermodule path 12-26
12.5.16 Task and function call 12-27
12.5.17 Continuous assignment 12-28
12.5.18 Simple expressions 12-29
12.5.19 Expressions 12-30
12.5.20 Contribs 12-31
12.5.21 Process, block, statement, event statement 12-32
12.5.22 Assignment, delay control, event control, repeat control 12-33
12.5.23 While, repeat, wait, for, forever 12-34
12.5.24 If, if-else, case 12-35
12.5.25 Assign statement, deassign, force, release, disable 12-36
12.5.26 Callback, time queue 12-37
13 VPI routine definitions 13-1
13.1 vpi_chk_error() 13-3
13.2 vpi_compare_objects() 13-4
13.3 vpi_free_object() 13-5
13.4 vpi_get() 13-6
13.5 vpi_get_cb_info() 13-7
13.6 vpi_get_analog_delta() 13-8
13.7 vpi_get_analog_freq() 13-9
13.8 vpi_get_analog_time() 13-10
13.9 vpi_get_analog_value() 13-11
13.10 vpi_get_delays() 13-13
13.11 vpi_get_str() 13-16
13.12 vpi_get_analog_systf_info() 13-17
13.13 vpi_get_systf_info() 13-18
13.14 vpi_get_time() 13-19
13.15 vpi_get_value() 13-20
13.16 vpi_get_vlog_info() 13-26
13.17 vpi_get_real() 13-27
13.18 vpi_handle() 13-28
13.19 vpi_handle_by_index() 13-29
13.20 vpi_handle_by_name() 13-30
13.21 vpi_handle_multi() 13-31
13.21.1 Derivatives for analog system task/functions 13-31
13.21.2 Examples 13-31
13.22 vpi_iterate() 13-35
13.23 vpi_mcd_close() 13-37
13.24 vpi_mcd_name() 13-38
13.25 vpi_mcd_open() 13-39
13.26 vpi_mcd_printf() 13-40
13.27 vpi_printf() 13-41
13.28 vpi_put_delays() 13-42
13.29 vpi_put_value() 13-45
13.30 vpi_register_cb() 13-47
13.30.1 Simulation-event-related callbacks 13-48
13.30.2 Simulation-time-related callbacks 13-50
13.30.3 Simulator analog and related callbacks 13-51
13.30.4 Simulator action and feature related callbacks 13-51
13.31 vpi_register_analog_systf() 13-53
13.31.1 System task and function callbacks 13-54
13.31.2 Declaring derivatives for analog system task/functions 13-54
13.31.3 Examples 13-55
13.32 vpi_register_systf() 13-59
13.32.1 System task and function callbacks 13-59
13.32.2 Initializing VPI system task/function callbacks 13-61
13.33 vpi_remove_cb() 13-62
13.34 vpi_scan() 13-63
13.35 vpi_sim_control() 13-64
A Syntax A-1
A.1 Source text A-1
A.2 Natures A-2
A.3 Disciplines A-3
A.4 Declarations A-3
A.5 Module instantiation A-5
A.6 Mixed-signal A-6
A.7 Behavioral statements A-6
A.8 Analog expressions A-9
A.9 Expressions A-9
A.10 General A-12
B Keywords B-1
B.1 All keywords B-1
B.2 Discipline/nature B-3
B.3 Connect rules B-3
C Analog language subset C-1
C.1 Verilog-AMS introduction C-1
C.1.1 Verilog-A overview C-1
C.1.2 Verilog-A language features C-1
C.2 Lexical conventions C-2
C.3 Data types C-2
C.4 Expressions C-3
C.5 Signals C-3
C.6 Analog behavior C-3
C.7 Hierarchical structures C-3
C.8 Mixed-signal C-4
C.9 Scheduling semantics C-4
C.10 System tasks and functions C-4
C.11 Compiler directives C-4
C.12 Using VPI routines C-4
C.13 VPI routine definitions C-4
C.14 Syntax C-4
C.15 Keywords C-5
C.16 Standard definitions C-5
C.17 SPICE compatibility C-5
C.18 Changes from Verilog-A LRM v1.0 C-5
C.19 Obsolete functionality C-7
C.19.1 Forever C-7
C.19.2 NULL C-7
C.19.3 Generate C-7
D Standard definitions D-1
D.1 The disciplines.vams file D-1
D.2 The constants.vams file D-7
E SPICE compatibility E-1
E.1 Introduction E-1
E.1.1 Scope of compatibility E-1
E.1.2 Degree of incompatibility E-1
E.2 Accessing SPICE objects from Verilog-AMS HDL E-2
E.2.1 Case sensitivity E-2
E.2.2 Examples E-3
E.3 Preferred primitive, parameter, and port names E-4
E.3.1 Independent sources E-5
E.3.2 Unsupported components E-6
E.4 Other issues E-6
E.4.1 Multiplicity factor on subcircuits E-6
E.4.2 Binning and libraries E-7
F Discipline resolution methods F-1
F.1 Discipline resolution F-1
F.2 Resolution of mixed signals F-1
F.2.1 Default discipline resolution algorithm F-1
F.2.2 Alternate expanded analog discipline resolution algorithm F-2
G Glossary G-1

Quadralay Corporation http://www.webworks.com Voice: (512) 719-3399 Fax: (512) 719-3606 sales@webworks.com