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E.1 Introduction
Analog simulation has long been performed with Spice and Spice-like simulators. As such, there is a huge legacy of Spice netlists. In addition, Spice provides a rich set of predefined models and it is considered neither practical nor desirable to convert these models into a Verilog-AMS HDL behavioral description. In order for Verilog-AMS HDL to be embraced by the analog design community, it is important Verilog-AMS HDL provide an appropriate degree of Spice compatibility. This annex describes the degree of compatibility which Verilog-AMS HDL provides and the approach taken to provide that compatibility.
E.1.1 Scope of compatibility
Spice is not a single language, but rather is a family of related languages. The first widely used version of Spice was Spice2g6 from the University of California at Berkeley. However, Spice has been enhanced and distributed by many different companies, each of which has added their own extensions to the language and models. As a result, there is a great deal of incompatibility even among the Spice languages themselves.
Verilog-AMS HDL makes no judgement as to which of the various Spice languages should be supported. Instead, it states if a simulator which supports Verilog-AMS HDL is also able to read Spice netlists of a particular flavor, then certain objects defined in that flavor of Spice netlist can be referenced from within a Verilog-AMS HDL structural description. In particular, Spice models and subcircuits can be instantiated within a Verilog-AMS HDL module. This is also true for any Spice primitives which are built into the simulator.
E.1.2 Degree of incompatibility
There are four primary areas of incompatibility between versions of Spice simulators.
1. The version of the Spice language accepted by various simulators is different and to some degree proprietary. This issue is not addressed by Verilog-AMS HDL. So whether a particular Verilog-AMS simulator is Spice compatible, and with which particular variant of Spice it is compatible, is solely determined by the authors of the simulator.
2. Not all Spice simulators support the same set of component primitives. Thus, a particular Spice netlist can reference a primitive which is unsupported. Verilog-AMS HDL offers no alternative in this case other than the possibility that if the model equations are known, the primitive can be rewritten as a module.
3. The names of the built-in Spice primitives, their parameters, or their ports can differ from simulator to simulator. This is particularly true because many primitives, parameters, and ports are unnamed in Spice. When instantiating Spice primitives in Verilog-AMS HDL, the primitives shall, and parameters and ports can, be named. Since there are no established standard names, there is a high likelihood of incompatibility cropping up in these names.
To reduce this, a list of what names shall be used for the more common components is shown in E.3. However, it is not possible to anticipate all Spice primitives and parameters which could be supported; so different implementations can end up using different names. This level of incompatibility can be overcome by using wrapper modules to map names.
4. The mathematical description of the built-in primitives can differ. As with the netlist syntax, incompatible enhancements of the models have crept in through the years. Again, Verilog-AMS HDL offers no solution in this case other than the possibility that if the model equations are known, the primitive can be rewritten as a module.
E.2 Accessing Spice objects from Verilog-AMS HDL
If an implementation of a Verilog-AMS tool supports Spice compatibility, it is expected to provide the basic set of Spice primitives (see E.3) and be able to read Spice netlists which contain models and subcircuit statements.
Spice primitives built into the simulator are treated in the same manner in Verilog-AMS HDL as built-in primitives. However, while the Verilog-AMS HDL built-in primitives are standardized, the Spice primitives are not. All aspects of Spice primitives are implementation dependent.
In addition to Spice primitives, it is also possible to access subcircuits and models defined within Spice netlists. The subcircuits and models contained within the Spice netlist are treated as module definitions.
E.2.1 Case sensitivity
Spice netlists are case insensitive, whereas Verilog-AMS HDL descriptions are case-sensitive. From within Verilog-AMS HDL, a mixed case name matches the same name with an identical case (if one is defined in a Verilog-AMS HDL description). However, if no exact match is found, the mixed case name shall match the same name defined within Spice regardless of the case.
E.2.2 Examples
This subsection shows some examples.
E.2.2.1 Accessing Spice models
Consider the following Spice model file being read by a Verilog-AMS HDL simulator.
.MODEL VERTNPN NPN BF=80 IS=1E-18 RB=100 VAF=50
+ CJE=3PF CJC=2PF CJS=2PF TF=0.3NS TR=6NS
This model can be instantiated in a Verilog-AMS HDL module as shown in Figure E.1.
module diffPair (c1, b1, e, b2, c2);
electrical c1, b1, e, b2, c2;
vertNPN Q1 (c1, b1, e, );
vertNPN Q2 (.c(c2), .b(b2), .e(e));
endmodule
Unlike with Spice, the first letter of the instance name, in this case Q1 and Q2, is not constrained by the primitive type. For example, they can just as easily be T1 and T2.
The ports and parameters of the BJT are determined by the BJT primitive itself and not by the model statement for the BJT. See E.3 for more details. The BJT has 3 mandatory ports (collector, base, and emitter) and one optional port (the substrate). In the instantiation of Q1, the ports are passed by order. With Q2, the ports are passed by name. In both cases, the optional substrate port is defaulted by simply not giving it.
E.2.2.2 Accessing Spice subcircuits
As an example of how a Spice subcircuit is referenced from Verilog-AMS HDL, consider the following Spice subcircuit definition of an oscillator.
.SUBCKT ECPOSC (OUT GND)
VA VCC GND 5
IEE E GND 1MA
Q1 VCC B1 E VCC VERTNPN
Q2 OUT B2 E OUT VERTNPN
L1 VCC OUT 1UH
C1 VCC OUT 1P IC=1
C2 OUT B1 272.7PF
C3 B1 GND 3NF
R1 B1 GND 10K
C4 B2 GND 3NF
R2 B2 GND 10K
.ENDS ECPOSC
This oscillator can be referenced from Verilog-AMS HDL as:
module osc (out, gnd);
electrical out, gnd;
ecpOsc Osc1 (out, gnd);
endmodule
Note: In Verilog-AMS HDL the name of the subcircuit instance is not constrained to start with X as it is in Spice.
E.2.2.3 Accessing Spice primitives
To show how various Spice primitives can be accessed from Verilog-AMS HDL, the subcircuit in Figure E.1 is translated to native Verilog-AMS HDL.
module ecpOsc (out, gnd);
electrical out, gnd;
vsine #(.dc(5)) Vcc (vcc, gnd);
isine #(.dc(1m)) Iee (e, gnd);
vertnpn Q1 (vcc, b1, e, vcc);
vertnpn Q2 (out, b2, e, out);
inductor #(.l(1u)) L1 (vcc, out);
capacitor #(.c(1p), .ic(1)) C1 (vcc, out);
capacitor #(.c(272.7p)) C2 (out, b1);
capacitor #(.c(3n)) C3 (b1, gnd);
resistor #(.r(10k)) R1 (b1, gnd);
capacitor #(.c(3n)) C4 (b2, gnd);
resistor #(.r(10k)) R2 (b2, gnd);
endmodule
E.3 Preferred primitive, parameter, and port names
Table E.1 shows the required names for primitives, parameters, and ports which are otherwise unnamed in Spice. For connection by order instead of by name, the ports and parameters shall be given in the order listed. The discipline of the ports for these primitives shall be electrical and their descriptions shall be inout.
Primitive name Port name Parameter name resistor
p, n
r, tc1, tc2
capacitor
p, n
c, ic
inductor
p, n
l, ic
vexp
p, n
dc, mag, phase, val0, val1, td0, tau0, td1, tau1 vpulse
p, n
dc, mag, phase, val0, val1, td, rise, fall, width, period vpwl
p, n
dc, mag, phase, wave vsine
p, n
dc, mag, phase, offset, amp1, freq, td, damp, sinephase, ammodindex, ammodfreq, ammodphase, fmmodindex, fmmodfreq iexp
p, n
dc, mag, phase, val0, val1, td0, tau0, td1, tau1 ipulse
p, n
dc, mag, phase, val0, val1, td, rise, fall, width, period ipwl
p, n
dc, mag, phase, wave isine
p, n
dc, mag, phase, offset, amp1, freq, td, damp, sinephase, ammodindex, ammodfreq, ammodphase, fmmodindex, fmmodfreq diode1
a, c
area
bjta
c, b, e, s
area
mosfeta
d, g, s, b
w, l, ad, as, pd, ps, nrd, nrs
jfeta
d, g, s
area
mesfeta
d, g, s
area
vcvs
p, n, ps, ns
gain
vccs
sink, src, ps, ns
gm
tline
t1, b1, t2, b2
z0, td, f, nl
1 The names diode, bjt, jfet, mesfet, and mosfet are never used from within Verilog-AMS HDL because these components require a model. Thus, the model name is used in Verilog-AMS HDL instead of the primitive name.
E.3.1 Independent sources
The parameters associated with each type of independent source are given in Table E.2. "ac" and "dc" parameters are common to each source type and need to be specified to list parameters by order before any waveshape parameters are specified.
E.3.2 Unsupported components
Verilog-AMS HDL does not support the concept of passing an instance name as a parameter. As such, the following components are not supported: ccvs, cccs, and mutual inductors; however, these primitives can be instantiated inside a subcircuit.
E.4 Other issues
This section highlights some other issues
E.4.1 Multiplicity factor on subcircuits
Some Spice simulators support a multiplicity factor (M) parameter on subcircuits without the parameter being explicitly being declared. This factor is typically used to indicate the subcircuit should be modeled as if there are a specified number of copies in parallel. If supported by the implementation, the automatic M factors are supported for subcircuits defined in Spice, but not for subcircuits defined as a modules in Verilog-AMS HDL. Thus, if the Spice subcircuit in E.2.2.2 was instantiated, a multiplicity factor could be specified (assuming the simulator implementation supports multiplicity factors on Spice subcircuits. However, a multiplicity factor can not be specified when instantiating the equivalent Verilog-AMS HDL module shown in E.2.2.3.
E.4.2 Binning and libraries
Some Spice netlists provide mechanisms for mapping an instance to a group of models, with the final determination of which model to use being based on rules encapsulated in the Spice netlist. Examples include model binning or corners support. From within an instance statement, it appears as if the instance is referencing a simple Spice model; supporting these additional capabilities in Verilog-AMS HDL is supported via the instance line by default. Support of model cards are implementation specific (including those using these mechanisms).
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