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This section details the simulation cycles for analog simulation and mixed A/D simulations.
9.1 Analog simulation cycle
Simulation of a network, or system, starts with an analysis of each node to develop equations which define the complete set of values and flows in a network. Through transient analysis, the value and flow equations are solved incrementally with respect to time. At each time increment, equations for each signal are iteratively solved until they converge on a final solution.
9.1.1 Nodal analysis
To describe a network, simulators combine constitutive relationships with Kirchhoff's Laws in nodal analysis to form a system of differential-algebraic equations of the form
These equations are a restatement of Kirchhoff's Flow Law (KFL).
v is a vector containing all node values
t is time
q and i are the dynamic and static portions of the flow
f( ) is a vector containing the total flow out of each node
v0 is the vector of initial conditions
This equation was formulated by treating all nodes as being conservative (even signal flow nodes). In this way, signal-flow and conservative terminals can be connected naturally. However, this results in unnecessary KFL equations for those nodes with only signal-flow terminals attached. This situation is easily recognized and those unnecessary equations are eliminated along with the associated flow unknowns, which shall be zero (0) by definition.
9.1.2 Transient analysis
The equation describing the network is differential and non-linear, which makes it impossible to solve directly. There are a number of different approaches to solving this problem numerically. However, all approaches discretize time and solve the nonlinear equations iteratively, as shown in Figure 91.
The simulator replaces the time derivative operator (dq/dt) with a discrete-time finite difference approximation. The simulation time interval is discretized and solved at individual time points along the interval. The simulator controls the interval between the time points to ensure the accuracy of the finite difference approximation. At each time point, a system of nonlinear algebraic equations is solved iteratively. Most circuit simulators use the Newton-Raphson (NR) method to solve this system.
9.1.3 Convergence
In the analog kernel, the behavioral description is evaluated iteratively until the NR method converges. On the first iteration, the signal values used in expressions are approximate and do not satisfy Kirchhoff's Laws.
In fact, the initial values might not be reasonable, so models need to be written so they do something reasonable even when given unreasonable signal values.
For example, the log or square root of a signal value is being computed, some signal values cause the arguments to these functions to become negative, even though a real-world system never exhibits negative values.
As the iteration progresses, the signal values approach the solution. Iteration continues until two convergence criteria are satisfied. The first criterion is the proposed solution on this iteration, v(j)(t), shall be close to the proposed solution on the previous iteration, v(j-1)(t), and
| vn(j) - vn(j-1) | < reltol (max(| vn(j)| , |vn(j-1)|)) + abstol
where reltol is the relative tolerance and abstol is the absolute tolerance.
reltol is set as a simulator option and typically has a value of 0.001. There can be many absolute tolerances, which one is used depends on the quantity the signal represents (volts, amps, etc.). The absolute tolerance is important when vn is converging to zero (0). Without abstol, the iteration never converges.
The second criterion ensures Kirchhoff's Flow Law is satisfied:
where fni(v(j)) is the flow exiting node n from branch i.
Both of these criteria specify the absolute tolerance to ensure convergence is not precluded when vn or fn(v) go to zero (0). The relative tolerance can be set once in an options statement to work effectively on any node in the circuit, but the absolute tolerance shall be scaled appropriately for its associated signal. The absolute tolerance shall be the largest signal value which is considered negligible on all the signals where it is associated.
The simulator uses absolute tolerance to get an idea of the scale of signals. Absolute tolerances are typically 1,000 to 1,000,000 times smaller than the largest typical value for signals of a particular quantity. For example, in a typical integrated circuit, the largest potential is about 5 volts, so the default absolute tolerance for voltage is 1mV. The largest current is about 1mA, so the default absolute tolerance for current is 1pA.
9.2 Mixed-signal simulation cycle
This section describes the semantics of the initialization and time-sweep phases of a transient analysis in a mixed-signal simulation cycle.
9.2.1 Circuit initialization
The initialization phase of a transient analysis is the process of initializing the circuit state before advancing time.
9.2.2 Transient analysis & A/D algorithm synchronization
In the analog kernel, time is a floating point value. In the digital kernel time is an integer value. Hence, A2D events generally do not occur exactly at digital integer clock ticks.
For the purpose of reporting results and scheduling delayed future events, the digital kernel truncates A2D events down to the earlier tick. Any events which are scheduled with zero (0) delay (as a result of the A2D) are not snapped down. Instead they are processed immediately.
Consequently an A2D event which results in a D2A event being scheduled with zero (0) delay, shall have its effect propagated back to the analog kernel with zero (0) delay.
If the circuit shown in Figure 92 is being simulated with a digital time resolution of 1e-9 (one (1) nanosecond) then all digital events shall be reported by the digital kernel as having occurred at an integer multiple of 1e-9.
If connector A detects a positive threshold crossing the resulting falling edge at connector B, this shall be reported to the analog kernel with no further advance of analog time. However, the digital kernel could to round the time of these events to the nearest nanosecond.
Example:
If A detects a positive crossing as a result of a transient solution at time 5.27e-9, the digital kernel shall report a rising edge at A at time 5.0e-9 and falling edge at B at time 5.0e-9, but the analog kernel shall see the transition at B begin at time 5.27e-9, as shown in Figure 93.
9.2.3 The synchronization loop
The digital and analog kernels shall be synchronized so neither computes results which the other is ineligible to accept. The synchronization algorithm can exploit characteristics of the analog and digital kernels described in the next section. A sample run is shown in Figure 94.
1. The Analog engine begins transient analysis and sends state information to the Digital engine (1, 2).
2. The Digital engine begins to run using its own time steps (3); however, if there is no D2A event, the Analog engine is not notified and the digital engine continues to simulate to until it can not advance its time without surpassing the time of the analog solution (4). Control of the simulation is then returned to the analog engine (5). This process is repeated (7, 8, 9, 10, and 11).
3. If the Digital engine produces a D2A event (12), control of the simulation is returned to the Analog engine (13). The analog engine returns to the point at which the digital engine last surrendered control (14). The Analog engine recalculates the analog solution up to the time when the D2A event occurred (15). The Analog engine then takes the next time step (16).
4. If the Analog engine produces an A2D event, it returns control to the Digital engine (17), which simulates up to the time of the A2D event and then surrenders control (18 and 19).
5. This process continues until transient analysis is complete.
9.2.4 Assumptions about the analog and digital algorithms
1. Advance of time in a digital algorithm
A. The digital simulation has some minimum time granularity and all digital events occur at a time which is some integer multiple of that granularity.
B. The digital simulator can always accept events for a given simulation time provided it has not yet executed events for a later time. Once it executes events for a given time, it can not accept events for an earlier time.
C. The digital simulator can always report the time of the most recently executed event and the time of the next pending event.
2. Advance of time in an analog algorithm
A. The analog simulator advances time by calculating a sequence of solutions. Each solution has an associated time which, unlike the digital time, is not constrained to a particular minimum granularity.
B. The analog simulator can not tell for certain the time when the next solution converges. Thus, it can tell the time of the most recently calculated solution, but not the time of the next solution.
C. In general, the analog solution is a function of one or more previous solutions. Having calculated the solution for a given time, the analog simulator can either accept or reject that solution; it can not calculate a solution for a future time until it has accepted the solution for the current time.
3. Analog to digital events
A. Analog to digital events are generated by conversion elements (which are analog/digital behavioral models) when evaluated by the analog simulator.
B. Analog events (e.g., cross, initial_step, and final_step) cause an analog solution of the time where they occur.
C. Thus, any analog to digital event is generated as the result of a particular transient solution. This means events can stay associated with the solution which produced them until they are passed to the digital simulator, then they can be rejected along with the solution if it is rejected.
4. Digital to analog events shall cause an analog solution of the time where they occur.
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