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This section describes the lexical tokens used in Verilog-AMS HDL source text and their conventions. This section is based on Section 2, Lexical conventions, of IEEE 1364-1995 Verilog HDL. The changes specific to Verilog-AMS HDL can be found in 2.5.3 and 2.7.2.
2.1 Lexical tokens
A Verilog-AMS HDL source text file is a stream of lexical tokens. A lexical token consists of one or more characters. The layout of tokens in a source file is free format-spaces and newlines are not syntactically significant other than being token separators, except escaped identifiers (see 2.7.1).
The types of lexical tokens in the language are as follows:
· white space
· comment
· operator
· number
· string
· identifier
· keyword
2.2 White space
White space token type contains the characters for spaces, tabs, newlines, and formfeeds. These characters are ignored except when they serve to separate other lexical tokens.
2.3 Comments
Verilog-AMS HDL has two forms to introduce comments, as shown in Syntax 21. A one-line comment starts with the two characters // and ends with a newline. Block comments start with /* and ends with */. Block comments can not be nested. The one-line comment token // does not have any special meaning in a block comment.
2.4 Operators
Operators are single, double, or triple character sequences and are used in expressions. Section 4 discusses the use of operators in expressions.
Unary operators appear to the left of their operand. Binary operators appear between their operands. A conditional operator has two operator characters which separate three operands.
2.5 Numbers
Constant numbers can be specified as integer constants or real constants. The syntax for constants is shown in Syntax 22.
2.5.1 Integer constants
Integer constants are specified in decimal format as a sequence of digits 0 through 9, optionally starting with a plus or minus unary operator. The underscore character (_) is legal anywhere in a decimal number except as the first character. The underscore character is ignored. This feature can be used to break up long numbers for readability purposes.
Examples:
27_195_000 // same as 27195000
-659
2.5.2 Real constants
The real constant numbers are represented as described by IEEE STD-754-1985, an IEEE standard for double precision floating point numbers (64-bits).
Real numbers can be specified in either decimal notation (e.g., 14.72) or in scientific notation (e.g., 39e8, which indicates 39 multiplied by 10 to the 8th power). Real numbers expressed with a decimal point shall have at least one digit on each side of the decimal point. The underscore character is legal anywhere in a real constant except as the first character of the constant or the first character after the decimal point. The underscore character is ignored.
Examples:
1.2
0.1
2394.26331
1.2E12 // the exponent symbol can be e or E
1.30e-2
0.1e-0
23E10
29E-2
236.123_763_e-12 // underscores are ignored
The following are invalid forms of real numbers because they do not have at least one digit on each side of the decimal point:
.12
9.
4.E3
.2e-7
2.5.3 Scale factors for real constants
Floating-point numbers can be specified using the following letter symbols for the scale factors indicated. Scale factors and scientific notation are not allowed to be used together in describing a real number.
No space is permitted between the number and the symbol. Scale factors are not allowed to be used in defining digital delays (e.g., #5u).
This form of floating-point number specification is provided in Verilog-AMS HDL in addition to the two methods for writing floating-point numbers described in 2.5.2.
Example:
Short form Expanded form 1.3u
1.3e-6 or 0.0000013
5.46K
5460
2.6 Strings
A string is a sequence of characters enclosed by double quotes ("") and contained on a single line. Strings used as operands in expressions and assignments shall be treated as unsigned integer constants represented by a sequence of 8-bit ASCII values, with one 8-bit ASCII value representing one character.
2.6.1 String variable declaration
String variables are variables of type reg (see IEEE 1364-1995 Verilog HDL) with the width equal to the number of characters in the string multiplied by eight (8).
Example:
To store the twelve-character string "Hello world!" requires a reg 8 * 12 or 96 bits wide
2.6.2 String manipulation
Strings can be manipulated using the Verilog HDL operators. The value being manipulated by the operator is the sequence of 8-bit ASCII values.
Example:
The output is:
Hello world is stored as 00000048656c6c6f20776f726c64
Hello world!!! is stored as 48656c6c6f20776f726c64212121
Note: When a variable is larger than required to hold a value being assigned, the contents on the left are padded with zeros (0) after the assignment. This is consistent with the padding which occurs during assignment of nonstring values. If a string is larger than the destination string variable, the string is truncated to the left and the leftmost characters are lost.
2.6.3 Special characters in strings
Certain characters can only be used in strings when preceded by an introductory character called an escape character. Table 21 lists these characters in the right-hand column, with the escape sequence that represents the character in the left-hand column.
Escape string Character produced byescape string \n New line character \t Tab character \\ \ character \" " character \ddd A character specified in 1-3 octal digits (0 £ d £ 7)
2.7 Identifiers, keywords, and system names
An identifier is used to give an object a unique name so it can be referenced. An identifier can be any sequence of letters, digits, dollar signs ($), and the underscore characters (_).
The first character of an identifier can not be a digit or $; it can be a letter or an underscore. Identifiers are case sensitive.
Examples:
shiftreg_a
busa_index
error_condition
merge_ab
_bus3
n$657
2.7.1 Escaped identifiers
Escaped identifiers start with the backslash character (\) and end with white space (space, tab, newline, or formfeed). They provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126 or 21 through 7E in hexadecimal).
Neither the leading back-slash character nor the terminating white space is considered to be part of the identifier. Therefore, an escaped identifier \cpu3 is treated the same as a non-escaped identifier cpu3.
Examples:
\busa+index
\-clock
\***error-condition***
\net1/\net2
\{a,b}
\a*(b+c)
2.7.2 Keywords
Keywords are predefined non-escaped identifiers which are used to define the language constructs. Preceding a keyword with an escape character (\) causes it to be interpreted as an escaped identifier.
All keywords are defined in lowercase only. Annex B lists all defined Verilog-AMS HDL keywords (including those from IEEE 1364-1995 Verilog HDL).
2.7.3 System tasks and functions
The $ character introduces a language construct which enables development of user-defined tasks and functions. A name following the $ is interpreted as a system task or a system function.
The syntax for a system task or function is given in Syntax 23.
Section 10 lists the standard system tasks and functions for Verilog-AMS HDL.
Any valid identifier, including keywords already in use in contexts other than this construct can be used as a system task or function name.
Examples:
$display ("display a message");
$finish;
2.7.4 Compiler directives
The ` character (the ASCII value 60, called open quote or accent grave) introduces a language construct used to implement compiler directives. The compiler behavior dictated by a compiler directive takes effect as soon as the compiler reads the directive. The directive remains in effect for the rest of the compilation unless a different compiler directive specifies otherwise. A compiler directive in one description file can therefore control compilation behavior in multiple description files.
Section 11 lists the Verilog-AMS HDL compiler directives and their syntax.
Any valid identifier, including keywords already in use in contexts other than this construct can be used as a compiler directive name.
Example:
`define wordsize 8
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