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The description of an analog behavior consists of setting up contributions (see 5.3) for various signals under certain procedural or timing control. This section describes an analog procedural block, procedural control statements, and analog timing control functions.
6.1 Analog procedural block
Discrete time behavioral definitions within IEEE 1364-1995 Verilog HDL are encapsulated within the initial and always procedural blocks. Every initial and always block starts a separate concurrent activity flow. For continuous time simulation, the behavioral description is encapsulated within the analog procedural block. Verilog-AMS HDL allows one analog procedural block in a module definition.
The analog procedural block defines the behavior as a procedural sequence of statements. The conditional and looping constructs are available for defining behaviors within the analog procedural block. Because the description is a continuous-time behavioral description, no blocking event control statements (such as blocking delays, events, or waits) are supported.
The statements allowed within the analog block are separated into two categories, analog_statements and (non analog) statements. The analog_statements are restricted to the analog block whereas the (non analog) statements can appear anywhere within the module scope, including an analog block. The distinction is based upon the visibility and usage of these behavioral constructs within a Verilog-AMS HDL module definition.
The syntax for analog block is shown in Syntax 61.
The statements within the analog block are used to define the continuous-time behavior of the module. The behavioral description is a mathematical mapping of input signals to output signals. The mapping is done with contribution statements using the form
signal <+ analog_expression ;
or by an indirect branch assignment. The analog_expression can be any combination of linear, nonlinear, or differential expressions of module signals, constants, and parameters (see Section 5).
All analog blocks contained in various modules in a design are considered to be executing concurrent with respect to each other.
6.2 Block statements
The block statements, also referred to as sequential blocks, are a means of grouping two or more statements together so they act syntactically like a single statement. The block statements are delimited by the keywords begin and end. The procedural statements in a block statement are executed sequentially in the given order.
6.2.1 Sequential blocks
The syntax for sequential blocks is shown in Syntax 62.
An analog_seq_block is a seq_block which encapsulates one or more analog_statements.
6.2.2 Block names
A sequential block can be named by adding a :block_identifier after the keyword begin. The naming of a block allows local variables to be declared for that block.
All local variables are static-that is, a unique location exists for all variables and leaving or entering blocks do not affect the values stored in them.
The block names give a means of uniquely identifying all variables at any simulation time.
6.3 Procedural assignments
In Verilog-AMS HDL, branch contributions and indirect branch assignments are used for modifying signals. Procedural assignments are used for modifying integer and real variables. The syntax for procedural assignments shown in Syntax 63.
The left-hand side of a procedural assignment shall be an integer or real identifier or an element of an integer or real array. The right-hand side expression can be any arbitrary expression constituted from legal operands and operators as described in Section 4.
An analog_procedural_assignment is defined as a procedural assignment whose right-hand side expression is an analog_expression involving analog operators.
6.4 Conditional statement
The conditional statement (if-else statement) is used to determine whether a statement is executed or not. The syntax of a conditional statement is shown in Syntax 64.
If the expression evaluates to True (that is, has a non-zero value), the true_statement shall be executed. If it evaluates to False (has a zero value (0)), the true_statement shall not be executed. If there is an else false_statement and expression is False, the false_statement shall be executed.
Since the numeric value of the if expression is tested for being zero (0), certain shortcuts are possible (see 4.1).
6.4.1 Examples
For example, the following two statements express the same logic:
if (expression)
if (expression != 0)
Because the else part of an if-else is optional, there can be confusion when an else is omitted from a nested if() sequence. This is resolved by always associating the else with the closest previous if() which lacks an else.
In the example below, the else goes with the inner if(), as shown by indentation.
if(index > 0)
if (i > j)
result = i;
else // else applies to preceding if
result = j;
If that association is not desired, a begin-end shall be used to force the proper association, as shown below.
if (index > 0) begin
if (i > j)
result = i;
end
else result = j;
Nesting of if statements (known as an if-else-if construct) is the most general way of writing a multi-way decision. The expressions are evaluated in order; if any expression is True, the statement associated with it shall be executed and this action shall terminate the whole chain. Each statement is either a single statement or a sequential block of statements.
6.4.2 Analog conditional statements
Analog conditional statements are syntactically equivalent to conditional statements except the True and/or False statement are analog_statements, as shown in Syntax 65. The conditional expression shall be a genvar_expression. (See the discussion in 4.4.1 regarding restrictions on the usage of analog operators.)
6.5 Case statement
The case statement is a multi-way decision statement which tests if an expression matches one of a number of other expressions, and if so, branches accordingly. The case statement has the syntax shown in Syntax 66.
The default-statement is optional. Use of multiple default statements in one case statement is illegal.
The case-expression and the case_item expression can be computed at runtime; neither expression is required to be a constant expression.
The case_item expressions are evaluated and compared in the exact order in which they are given. During this linear search, if one of the case_item expressions matches the case-expression given in parentheses, then the statement associated with that case_item is executed. If all comparisons fail, and the default item is given, then the default item statement is executed; otherwise none of the case_item statements are executed.
The casex and the casez versions of the case statement are described in 8.3.2 and IEEE 1364-1995 Verilog HDL.
6.5.1 Analog case statements
Analog case statements are syntactically equivalent to case statements except the case item statements can also be analog_statements, as shown in Syntax 67. The conditional expression shall be a genvar expression. See the discussion in 4.4.1 regarding restrictions on the usage of analog operators.
The casex and the casez versions of the case statement are described in 8.3.2 and IEEE 1364-1995 Verilog HDL.
6.5.2 Constant expression in case statement
A constant expression can be used for a case expression. The value of the constant expression shall be compared against case_item expressions.
Examples:
The following example demonstrates the usage by modeling a 3-bit priority encoder.
integer [2:0] encode ;
case (1)
encode[2] : $display("Select Line 2") ;
encode[1] : $display("Select Line 1") ;
encode[0] : $display("Select Line 0") ;
default $strobe("Error: One of the bits expected ON");
endcase
The case expression here is a constant expression (1). The case_items are expressions (array elements) and are compared against the constant expression for a match.
6.6 Looping statements
There are several types of looping statements: repeat(), while(), and for(). These statements provide a means of controlling the execution of a statement zero (0), one (1), or more times.
The for() looping statements can be used to describe analog behaviors using analog operators.
Analog operators are not allowed in the repeat(), while(), and for() looping statements. They are allowed in analog_for and generate statements.
6.6.1 Repeat and while statements
repeat() executes a statement a fixed number of times. Evaluation of the expression decides how many times a statement is executed.
while() executes a statement until an expression becomes False. If the expression starts out False, the statement is not executed at all.
The repeat and while expressions shall be evaluated once before the execution of any statement in order to determine the number of times, if any, the statements are executed. The syntax for repeat() and while() statements is shown in Syntax 68.
6.6.2 For statements
The for() statement is a looping construct which controls execution of its associated statement(s) using an index variable. If the associated statement is an analog_statement, then the control mechanism shall consist of genvar_assignments and genvar_expressions to adhere to the restrictions associated with the use of analog operators. If the associated statements are not analog_statements, the for() statement can use procedural assignments and expressions, including genvar_expressions.
The for() statement controls execution of its associated statement(s) by a three-step process:
1. it executes an assignment normally used to initialize an integer which controls the number of loops executed.
2. it evaluates an expression-if the result is zero (0), the for-loop exits; otherwise, the for-loop executes its associated statement(s) and then performs Step 3.
3. it executes an assignment normally used to modify the value of the loop-control variable and repeats Step 2.
Syntax 69 shows the syntax for the two forms of the for() statements.
analog_for statements are syntactically equivalent to for() statements except the associated statement is also an analog statement (which contains analog operations). The analog statement puts the additional restriction upon the procedural assignment and conditional expressions of the for-loop to be statically evaluatable. Verilog-AMS HDL provides genvar-derived expressions for this purpose.
Examples:
module genvarexp(out, dt);
parameter integer width = 1;
output out;
input dt[1:width];
electrical out;
electrical dt[1:width];
genvar k;
real tmp;
analog begin
tmp = 0.0;
for (k = 1; k <= width; k = k + 1) begin
tmp = tmp + V(dt[k]);
V(out) <+ ddt(V(dt[k]));
end
end
endmodule
See the discussion in 4.4.1 regarding other restrictions on the usage of analog operators.
6.7 Events
The analog behavior of a component can be controlled using events. events have the following characteristics:
· events have no time duration
· events can be triggered and detected in different parts of the behavioral model
· events do not block the execution of an analog block
· events can be detected using the @ operator
· events do not hold any data
· there can be both digital and analog events
There are two types of analog events, global events (6.7.4) and monitored events (6.7.5). Null arguments are not allowed in analog events.
6.7.1 Event detection
Analog event detection consist of an event expression followed by a procedural statement, as shown in Syntax 610.
The procedural statement following the event expression is executed whenever the event described by the expression changes. The analog event detection is non-blocking, meaning the execution of the procedural statement is skipped unless the analog event has occurred. The event expression consists of one or more signal names, global events, or monitored events separated by the or operator.
The parenthesis around the event expression are required.
6.7.2 Event OR operator
The "OR-ing" of events indicates the occurrence of any one of the events specified shall trigger the execution of the procedural statement following the event. The keyword or is used as an event OR operator.
Examples:
analog begin
@(initial_step or cross(V(smpl)-2.5,+1)) begin
vout = (V(in) > 2.5);
end
V(out) <+ vout;
end
Here, initial_step is a global event and cross() returns a monitored event. The variable vout is set to zero (0) or one (1) whenever either event occurs.
6.7.3 Event triggered statements
The following two restrictions apply to statements which are evaluated as a result of an event being triggered.
· The statement can not have expressions which use analog operators. This statement can not maintain its internal state since it is only executed intermittently when the corresponding event is triggered.
· The statement can not be a contribution statement because it can generate discontinuity in analog signals.
6.7.4 Global events
Global events are generated by a simulator at various stages of simulation. The user model can not generate these events. These events are detected by using the name of the global event in an event expression with the @ operator.
Global events are pre-defined in Verilog-AMS HDL. These events can not be redefined in a model.
The pre-defined global events are shown in Syntax 611.
initial_step and final_step generate global events on the first and the last point in an analysis respectively. They are useful when performing actions which should only occur at the beginning or the end of an analysis. Both global events can take an optional argument, consisting of an analysis list for the active global event.
Examples:
For example,
@(initial_step("ac", "dc")) // active for dc and ac only
@(initial_step("tran")) // active for transient only
Table 61 describes the return value of initial_step and final_step for standard analysis types. Each column shows the return-on-event status. One (1) represents Yes and zero (0) represents No. A Verilog-AMS HDL simulator can use any or all of these typical analysis types. Additional analysis names can also be used as necessary for specific implementations. (See 4.5.1 for further details.)
Analysis1 DCOPOP TRANOP p1 pN ACOP p1 pN NOISEOP p1 pN initial_step() 1 0 0 1 0 0 1 0 0 initial_step("ac") 0 0 0 1 0 0 0 0 0 initial_step("noise") 0 0 0 0 0 0 1 0 0 initial_step("tran") 1 0 0 0 0 0 0 0 0 initial_step("dc") 0 0 0 0 0 0 0 0 0 initial_step(unknown) 0 0 0 0 0 0 0 0 0 final_step() 0 0 1 0 0 1 0 0 1 final_step("ac") 0 0 0 0 0 1 0 0 0 final_step("noise") 0 0 0 0 0 0 0 0 1 final_step("tran") 0 0 1 0 0 0 0 0 0 final_step("dc") 0 0 0 0 0 0 0 0 0 final_step(unknown) 0 0 0 0 0 0 0 0 0
1 pX designates analysis point X, X = 1 to N; OP designates the Operating Point.
Examples:
The following example measures the bit-error rate of a signal and prints the result at the end of the simulation.
module bitErrorRate (in, ref) ;
input in, ref ;
electrical in, ref ;
parameter real period=1, thresh=0.5 ;
integer bits, errors ;
analog begin
@(initial_step) begin
bits = 0 ;
errors = 0 ;
end
@(timer(0, period)) begin
if ((V(in) > thresh) != (V(ref) > thresh))
errors = errors + 1 ;
bits = bits + 1 ;
end
@(final_step)
$strobe("bit error rate = %f%%", 100.0 * errors / bits ) ;
end
endmodule
initial_step and final_step take a list of quoted strings as optional arguments. The strings are compared to the name of the analysis being run. If any string matches the name of the current analysis name, the simulator generates an event on the first point and the last point of that particular analysis, respectively.
If no analysis list is specified, the initial_step global event is active during the solution of the first point (or initial DC analysis) of every analysis. The final_step global event, without an analysis list, is only active during the solution of the last point of every analyses.
6.7.5 Monitored events
Monitored events are detected using event functions (see Syntax 612) with the @ operator. The triggering of a monitored event is implicit due to change in signals, simulation time, or other runtime conditions.
6.7.5.1 cross function
The cross() function is used for generating a monitored analog event to detect threshold crossings in analog signals when the expression crosses zero (0) in the specified direction. In addition, cross() controls the timestep to accurately resolve the crossing.
The general form is
cross ( expr [ , dir [ , time_tol [ , expr_tol ] ] ] ) ;
where expr is required, and dir, time_tol, and expr_tol are optional. All arguments are real expressions, except dir (which is an integer expression). If the tolerances are not defined, then the tool (e.g., the simulator) sets them. If either or both tolerances are defined, then the direction shall also be defined.
The direction indicator can only evaluate to +1, -1, or 0. If it is set to 0 or is not specified, the event and timestep control occur on both positive and negative crossings of the signal. If dir is +1 (or -1), the event and timestep control only occur on rising edge (falling edge) transitions of the signal. For any other transitions of the signal, the cross() function does not generate an event.
expr_tol and time_tol are defined as shown in Figure 61. They represent the maximum allowable error between the estimated crossing point and the true crossing point.
If expr_tol is defined, time_tol shall also be defined and both tolerances shall be satisfied at the crossing.
Examples:
The following description of a sample-and-hold illustrates how the cross() function can be used.
module sh (in, out, smpl) ;
output out ;
input in, smpl ;
electrical in, out, smpl ;
real state ;
analog begin
@(cross(V(smpl) - 2.5, +1))
state = V(in) ;
V(out) <+ transition(state, 0, 10n) ;
end
endmodule
The cross() function maintains its internal state and has the same restrictions as analog operators. In particular, it shall not be used inside an if(), case(), casex(), or casez() statement unless the conditional expression is a genvar expression. In addition, cross() is not allowed in the repeat() and while() iteration statements. It is allowed in the analog_for statements.
6.7.5.2 timer function
The timer() function is used to generate analog events to detect specific points in time.
The general form is
timer ( start_time [ , period [ , time_tol ] ] ) ;
where start_time is required; period and time_tol are optional arguments. All arguments are real expressions.
The timer() function schedules an event which occurs at an absolute time (start_time). The analog simulator places a time point within timetol of an event. At that time point, the event evaluates to True.
If time_tol is not specified, the default time point is at, or just beyond, the time of the event. If the period is specified as greater than zero (0), the timer function schedules subsequent events at multiples of period.
Examples:
A pseudo-random bit stream generator is an example how the timer function can be used.
module bitStream (out) ;
output out ;
electrical out ;
parameter period = 1.0 ;
integer x ;
analog begin
@(timer(0, period))
x = $random + 0.5 ;
V(out) <+ transition( x, 0.0, period/100.0 ) ;
end
endmodule
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