Message-ID: <4D5EAC90.7030905@freescale.com>
Date: Fri, 18 Feb 2011 11:29:52 -0600
From: Dave Miller <David.L.Miller@freescale.com>
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To: Verilog-AMS LRM Committee <verilog-ams@eda.org>
Subject: Verilog-AMS Committee Meeting Minutes - 17th Feb 2011
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Meeting - Thursday 17th February 2011

Attendees:
Sri Chandra 	(Freescale)
Geoffrey Coram 	(Analog Devices)
Scott Little 	(Freescale)
David Miller 	(Freescale)


* Update from recent SV committee meeting
Sri recently participated in the System Verilog committee meeting and discussed 
what we plan to do with respect to the System Verilog-AMS merge.
Main discussion was with respect to the document.
Discussed both option:
1. get all chapters and incorportate analog entensions to produce one fully 
contained System-Verilog-AMS document.
2. Just obtain the style sheets and generate an extensions document. This would 
be similar to what we have now with the Verilog-AMS 2.3.1 and 1364-2005.

The SV board was a lot more comfortable with 2.

It also means we don't have to do a complete review of our document every time 
the parent P1800 document changes especially since our time lines may not sync up.

The next item that was discussed was the BNF, do we want to have an appendix 
that is just the AMS changes to the P1800 or do we want to support a single 
merged BNF? Still undecided, but feel the most useful option is a single merged 
BNF. Yes, it does mean we need to keep it up to date with changes in the parent 
P1800 BNF, but changes in the BNF are not quite as drastic as the potential 
document changes between revisions.

Lynn Horobin is working with Accellera and P1800 to get the necessary 
permissions in place to access the documents.

We made need some sort of restrictive access, or access list put in place, this 
is still being looked into.

There was some discussion on how VHDL 1076 works, with the 1076.1 dot standard 
for the AMS extensions being a similar work effort to what we are undertaking. 
It is referred to as a superset of 1076 and does mention that it may not be in 
sync with the parent 1076 standard.

* Other items
Achim sent some requests for enhancements to the Verilog-AMS standard. They 
have been lodged as Mantis item: 3392.

Dave asked a question related to the request by Jonathan regarding detecting of 
floating node conditions during run time.

Geoffrey explained that they are not ideal floating nodes, but situations where 
for example, a MOS device is turned off. The node may exhibit a very tiny 
conductance and be very loosely controlled. It is these high impedance nodes 
that people are interested in detecting. If the tools could detect these 
conditions, it would be very useful.

The next call will be Thursday 3rd March.

An agenda will be distributed two days prior to the call.

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-- 
==============================================
-- It's a beautiful day
-- Don't let it get away
--
-- David Miller
-- Design Technology (Austin)
-- Freescale Semiconductor
-- Ph : 512 996-7377 Fax: x7755
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