`define CYCLE 10
`timescale 1ns/1ns
module clk_init2;
  logic clk;

  initial begin
    clk <= '0;
    forever #(`CYCLE/2) clk = ~clk;
  end

  tb T (.*);
endmodule

program tb (input logic clk);
  logic rst_n;

  default clocking cb0 @(negedge clk);
  endclocking

  initial begin
    INIT_RESET;
    FINISH(10); // run for 10 cycles and finish
  end

  task INIT_RESET (int cnt=1);
    rst_n = '0;
    ##(cnt) rst_n = '1;
  endtask

  task FINISH (int cnt=1);
    ##(cnt) $finish;
  endtask

  initial begin
    $timeformat(-9,0,"ns",6);
    $monitor("%t: clk=%b  rst_n=%b", $time, clk, rst_n);
  end
endprogram