module testcase;

  logic [7:0] [10:0] mem_addr; 
  logic [10:0] addr;
  logic inc=0, clk=1'b1;
   
  function logic[7:0] get_index();
	$display("No argument: mem_addr[2] =%d", mem_addr[2]);
	
    if(mem_addr[2]==addr) get_index=2;
	else get_index=0;
  endfunction : get_index 

  function logic[7:0] get_index2(logic [7:0] [10:0] mem_addr);
    $display("With argument: mem_addr[2] =%d", mem_addr[2]);	
    if(mem_addr[2]==addr) get_index2=2;
	else get_index2=0;
  endfunction : get_index2	

  
  property p_write;
      int   v_index;
      logic [10:0] v_addr;
 	   (inc, v_addr=addr, v_index=get_index()) |=>
				   mem_addr[v_index] == v_addr+1'b1;
  endproperty : p_write
  ap_write : assert property(@ (posedge clk) p_write);

  property p_write2;
      int   v_index;
      logic [10:0] v_addr;
 	   (inc, v_addr=addr, v_index=get_index2(mem_addr)) |=>
				   mem_addr[v_index] == v_addr+1'b1;
  endproperty : p_write2
  ap_write2 : assert property(@ (posedge clk) p_write2);

  initial forever #5 clk=!clk;
  
   initial begin
	for (int i=0; i<8; i=i+1)
	  mem_addr[i]=i;
	repeat (3) @ (posedge clk);
     mem_addr[2] <= 11'b00000001100;
	 @ (posedge clk) inc <= 1'b1;
	 addr <= 11'b00000001100;
	 @ (posedge clk) mem_addr[2] <= 11'b00000001101;
	 inc <= 1'b0;
	 repeat(5) @ (posedge clk);
	  $finish;
   end 
	 
  endmodule : testcase