Minutes SV-AC 08/11/03
Written by: Stephen Meier

SV-AC v3.1a Meetings:
	Every other Monday 9AM, next meeting August 25th
        Domestic: 888-635-9997
        International: 763-315-6815
        Participant: 959066#


Attendance Record
	Legend:
		x = attended
		- = missed
		r = represented
		. = not yet a member
		v = valid voter (3 out of last 4 or 75% overall)
		n = not valid voter

v[xxx] Faisal Haque (Cisco, Chairman)
v[xxx] Steve Meier (Synopsys, Co-Chair)
v[---] Roy Armoni (Intel)
v[xxx] Surrendra Dudani (Synopsys)
v[---] Cindy Eisner (IBM)
v[xxx] John Havlicek (Motorola)
n[---] Richard Ho (0-in)
v[-xx] Adam Krolnik (LSI)
v[xxx] Joseph Lu (Sun)
v[--r] Erich Marschner (Cadence)
n[---] Andrew Seawright (0-in)
v[xxx] Bassam Tabbara (Novas)
v[---] Tej Singh (Mentor)
n[-x-] Connie O'dell (Consultant)
n[xx-] Hillel Miller (Motorola)
	
==+------------------------- 07/27/03

Historical Attendance from SV3.1 through 4/21/03

v[xxxxxxxxxxxxxxxxxxxx----x.] Faisal Haque (Cisco, Chairman)
v[xxxxxxxxxxxxxxxxxxxx-x-x-x] Steve Meier (Synopsys, Co-Chair)
v[xxxxxxx-xxxxxxxxxxx-xxx--x] Roy Armoni (Intel)
v[xxrxxxxxrxxxxxxx-x-xxxrxx.] Surrendra Dudani (Synopsys)
v[rxxxxxxxxxxxxxxxxxxxxxrxrx] Cindy Eisner (IBM)
v[xxxxxxxxxxxxxxxxxrxx-xxx..] John Havlicek (Motorola)
n[--xxx--xxrxxxxxx-xx-xxxxx.] Richard Ho (0-in)
v[-xxxxxx-xxxx-xxxxxxxxxxrx-] Adam Krolnik (LSI)
v[xxxxxxxxxxx-xxxxxxxxx---xx] Joseph Lu (Sun)
v[rxxxrx--xxxxxxxxxxxx--xxxx] Erich Marschner (Cadence)
v[-xxx-x-xxxrxxxx-x-xxxxxx-x] Andrew Seawright (0-in)
v[x-xxxxxxxxxxxxxxxxx-xrxxxx] Bassam Tabbara (Novas)
v[-xxxx-x-xxxxx.............] Tej Singh (Mentor)
n[x-x--xx-xxxx..............] Connie O'dell (Consultant)
n[---xx-x-xxx-x--xxx-x--xx-x] David Lacey (HP, OVL Chairman)
n[-x--x-xxxxx---x...........] Hillel Miller (Motorola)
n[-----xxxx.................] Kurt Shultz (Motorola)
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==+------------------------- 04/21/03

1. Enhancement List

Commitments review, due be COB today!

Joseph signed up for immed_assume and seq_params.

Discussion:

	Clock gating: Adam indicated that Steve had summarized his input incorrectly.  Adam restated that the enhancement is to allow an enabled version of past to allow access to prior values of variables within gated limits.  So the enhancement is to provide a form of access to prior values under clock gating control.


2. Errata List

Review of Surrendra Dudani email dated Fri, 08 Aug 2003 14:48:29 -0400 

081003.AC1) throughout associativity

	Change the associativity of throughout to right. Currently, it is defined as 
	left in Table 17.1 
		Left associativity does not work as it creates 
			a throughout b throughout c ##! d;  	(1) 
			(a throughout b) throughout c ##! d;  	(2) 
		(2) is incorrect as the first term must be a boolean, while (a throughout b)  
		is a sequence 


	Question of whether there is any other right associative operator ?  John indicated
	that nested implication would likely be right. General agreement on the change

081003.AC2) unary ## should have the higher precedence than binary ##,

	Change to perhaps just below "," in Table 	17.1. 
	This make it more intuitive, such as 
	##1 a ##1 b #1 c 
	(##1 a) ## 1 b ##1 c, rather than 
	##1 ( a ##1 b #1 c) 
	Also, it works like arithmetic +, where unary + has a higher precedence than binary + 

Discussion on whether unary operators exists in v3.1a as a specific distinguished.  Steve and Surrendra pointed out that it is not explicitly listed, yet it is allowed in syntax and covered in formal semantics.  Two points of view. a) let it exist but do not promote and keep as independent initial delay b) model specifically as unary operator and specify its precedence.  This will be resolved through more discussion later.

081003.AC3) Allow clocked sequences(including multi-clock) to be parenthesized 

	This will allow examples as 
		sequence name; 
 		    (@clk seq); 
		endsequence 
		sequence name; 
  		   (@clk s1 ## @clk s2); 
		endsequence 
		sequence name; 
    		 (@clk s1) ## (@clk s2); 
		endsequence 
  
		property name; 
		   (@clk s1) |-> (@clk s2); 
		endproperty 

	John clarified if these would require specific productions and Surrendra agreed, John 	indicated that he included it withing formal semantics abstract syntax.

081003.AC4) Question on whether, the language force parenthesis around the expression with local 	variable assignments, such as:

	a ##1 (b, l1 = 4, l2 = 5) ##1 c 
	Currently, you can write the above as 
	a ##1 b, l1 = 4, l2 = 5 ##1 c


	In other places in Verilog () is used whenever ", " is used for assignments. Also, it 			makes it clear that ", "is tied to the preceding boolean, rather than the sequence 

	Adam feels that useful as optional, but not to be required.



3. PSL Status

Faisal inquire on status of PSL with John.  John indicated good progress at writing mapping and down to minor issues fixing bugs in the mapping.

Meeting Concluded