module enableclk;

reg clk;

reg enable;
reg [3:0] d, q, q1;

initial begin
  clk = 0;
  forever clk = #10 ~clk;
  end


initial 
  begin
  $display(" q uses clk & enable.");
  $display("q1 uses clk iff enable.");
  $display("      time clk d  e  q  q1");
  $monitor($stime,,, clk,, d,,, enable,, q,, q1);
  end

always @(posedge clk)  if (enable) q1 <= d;
always @(posedge (clk & enable))   q <= d;

initial begin
  d = 0;
  repeat (20) @(posedge clk) d <= d + 1'b1;
  $finish;
  end

initial begin

  enable = 0;

  repeat (10)
    begin
    @(posedge clk);
    enable = 1'b1;
    @(posedge clk);
    enable = 1'b0;
    @(posedge clk);
    end
  end

endmodule