Minutes SV-AC 02/20/03
Written by: Stephen Meier

ATTN: Next SV-AC Meeting Tue Feb 25th 9:30-10:30AM PST 
	Dial-In = 888-830-6260
	Intl: 1-505-242-2420
	PartID = 908704

Legend:
x = attended
- = missed
r = represented
. = not yet a member
v = valid voter (3 out of last 4)
n = not valid voter

v[xxxxxxxxxxxx----x.] Faisal Haque (Cisco, Chairman)
v[xxxxxxxxxxxx-x-x-x] Steve Meier (Synopsys, Co-Chair)
v[xxxxxxxxxxx-xxx--x] Roy Armoni (Intel)
v[rxxxxxxx-x-xxxrxx.] Surrendra Dudani (Synopsys)
v[xxxxxxxxxxxxxxrxrx] Cindy Eisner (IBM)
v[xxxxxxxxxrxx-xxx..] John Havlicek (Motorola)
v[xrxxxxxx-xx-xxxxx.] Richard Ho (0-in)
v[xxxx-xxxxxxxxxxrx-] Adam Krolnik (LSI)
v[xxx-xxxxxxxxx---xx] Joseph Lu (Sun)
v[xxxxxxxxxxxx--xxxx] Erich Marschner (Cadence)
v[xxrxxxx-x-xxxxxx-x] Andrew Seawright (0-in)
v[xxxxxxxxxxx-xrxxxx] Bassam Tabbara (Novas)
v[xxxx-x-xxxxx-xxxx-] Prakash Narain (Real Intent)
v[xxxxx.............] Tej Singh (Mentor)
v[xxxx..............] Connie O'dell (Consultant)
v[xxx-x--xxx-x--xx-x] David Lacey (HP, OVL Chairman)
v[xxx---x...........] Hillel Miller (Motorola)

n[x.................] Kurt Shultz (Motorola)
n[--xx-xxx-rx-xxxrrx] Harry Foster (Verplex)
n[---xx-----xxxxxxx.] Ambar Sarkar (Paradigm Works)
n[-----xxxxx........] Yaron Wolfsthal (IBM)
n[----x.............] Glenn Wesley (Consultant)
n[------xxx-xxxxxxxx] Gail Dagan (Intel)
n[-------xxxxxxxxxx-] Rajeev Ranjan (Real Intent)
n[--------x.........] Sagi Katz (Gallileo)
n[-------xxxx-x-x...] Richard Stolzman (Verplex)
n[------xxx-xxxxxxrx] Tom Fitzpatrick (Synopsys)
n[------x--x-x-x--xr] Tom Anderson (0-in)
n[-----------------x] Jason Andrews (Axis)
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1. Issue Review

Issue 1: Sequential Implication - vote on Surrendra proposed syntax, only has directives at the named property level, or in other words there is no nesting of property directives.

Issue 1.1: Separate vote on whether to allow nesting for variable sampling

Issue 4: always is implicit, if never changes to not, then initial can co-occur with not.  Proposal is

Issue 5 (Sem5): Cindy would like to make a proposal moving dynamic variable declaration to property level.  2nd by Adam, 3rd by Bassam.  Cindy will email proposal on Sunday.

Issue 2: check construct removal

Issue 6 and 9 combined

Issue 9: Vote only one of
	a) Cindy: add additonal non-overlapping version
	b) Adam: change to non-overlapping version

steve took action to prepare sample ballot for review on Friday and voting on Monday.  Feedback on ballot is due by Sunday 12noon.

2. Clock and Context Extraction

Steve presented presentation svac_context_extraction2 to review additional details and examples under Section 11.10.2.

Some of the key points of discussion were:

Adam asked if clocking domain applies to only module or if it has any hierarchical application under module hierarchy.  Steve took action to get an answer.  Initial guess is that it only applies to the module.

Pg 8: It was pointed out that property and assert have same problem of multiple extraction that sequence and bool have.  It was also noted that multiple extraction likely has no negative side effect (conjoining same variable).  The point was made (by Cindy) that if the declarations are alowed in procedural context that most users would assume context extraction.  Comments indicated that allowing declarations was useful functionality.

There was discussion on Adam's example of function with embedded assertion.  There was agreement that it is valuable to support assertions embedding in functions and tasks and that clock and condition extraction should be supported for these.

It was also pointed out that in the multiple extraction case (pg 12) that the variables could be conjoined together as opposed to having nested implication.

An action was taken to provide semantic description of assertion evaluation wrt. to behavior of the condition signal evaluations.  The desire is to have specific reference to the blocking/non-blocking behavior of variable assignments.  [Steve comment: the behavior is the same as all signal sampling as defined in scheduling semantic.  The variables are sampled at the sampling clock edge.  In the scheduling document this is clearly documented, we will schedule review of this in SV-AC].

There was discussion of whether the intial directive is appropriate in a procedural context.  Most of the group indicated that there was no clear need for this functionality.

3. Section Review

{11.10.1} Embedding Properties in Procedural Code
this was covered in context discussion.

{11.11) Grouping Assertions as a Library

{11.12} Binding Properties to Scopes or instances

Adam asked why not bind templates directly.  Steve indicated that program block is more general and can contain template instantiations within it.

Adam why not create some mechansim to extend module definition like deriving (or extending) an object in OOP programming.  Adam felt that this would be natural way of extending module with any verilog code.  Steve indicated that this was designed to only allow verification code that would be read-only and not allow any room for side effects into the design code.  Steve agreed that extensions may be another way to achieve similar functionality.

Review Concluded of Rev 0.8 Concluded

Meeting Concluded