Minutes SV-AC 02/06/03 Written by: Stephen Meier ATTN: Next SV-AC Meeting Feb 13th 9:30-11AM PST Dial-In = 888-830-6260 Intl: 1-505-242-2420 PartID = 908704 Legend: x = attended - = missed r = represented . = not yet a member v = valid voter (3 out of last 4) n = not valid voter v[xxxxxxxxxx----x.] Faisal Haque (Cisco, Chairman) v[xxxxxxxxxx-x-x-x] Steve Meier (Synopsys, Co-Chair) v[xxxxxxxxx-xxx--x] Roy Armoni (Intel) v[xxxxxx-x-xxxrxx.] Surrendra Dudani (Synopsys) v[xxxxxxxxxxxxrxrx] Cindy Eisner (IBM) v[xx-xxx-rx-xxxrrx] Harry Foster (Verplex) v[xxxxxxxrxx-xxx..] John Havlicek (Motorola) v[xxxxxx-xx-xxxxx.] Richard Ho (0-in) v[xx-xxxxxxxxxxrx-] Adam Krolnik (LSI) v[x-xxxxxxxxx---xx] Joseph Lu (Sun) v[xxxxxxxxxx--xxxx] Erich Marschner (Cadence) v[-xxxx-x-xxxxxx-x] Andrew Seawright (0-in) v[xxxxxxxxx-xrxxxx] Bassam Tabbara (Novas) v[xx-x-xxxxx-xxxx-] Prakash Narain (Real Intent) v[xxx.............] Tej Singh (Mentor) n[-xx-----xxxxxxx.] Ambar Sarkar (Paradigm Works) n[x-x--xxx-x--xx-x] David Lacey (HP, OVL Chairman) n[---xxxxx........] Yaron Wolfsthal (IBM) n[xx..............] Connie O'dell (Consultant) n[--x.............] Glenn Wesley (Consultant) n[x---x...........] Hillel Miller (Motorola) n[----xxx-xxxxxxxx] Gail Dagan (Intel) n[-----xxxxxxxxxx-] Rajeev Ranjan (Real Intent) n[------x.........] Sagi Katz (Gallileo) n[-----xxxx-x-x...] Richard Stolzman (Verplex) n[----xxx-xxxxxxrx] Tom Fitzpatrick (Synopsys) n[----x--x-x-x--xr] Tom Anderson (0-in) n[---------------x] Jason Andrews (Axis) ==|||||||||||||||| ==|||||||||||||||+- 7/9/02 ==||||||||||||||+-- 7/25/02 ==|||||||||||||+--- 8/1/02 ==||||||||||||+---- 8/8/02 ==|||||||||||+----- 8/15/02 ==||||||||||+------ 8/22/02 ==|||||||||+------- 9/5/02 ==||||||||+-------- 9/12/02 ==|||||||+--------- 9/19/02 ==||||||+---------- 9/26/02 ==|||||+----------- 10/3/02 ==||||+------------ 10/31/02 ==|||+------------- 12/03/02 ==||+-------------- 01/23/03 ==|+--------------- 01/30/03 ==|+--------------- 02/06/03 1. Issue Discussion on Sec 11.1 - 11.8 Issue: Sem1 {11.4} Sequential Implication: Cindy, Erich, John John and Surrendra submitted proposals. John indicated that they both achieve the same effect of moving to the higher level (above sequences). Surrendra walked through his proposal. Cindy expressed concern that the proposal supports nesting and this is the first time there is notion of formula layer (nesting above sequences). We reviewed example of nesting (Adam's issue) in which the nesting is used to provide mechanism for sampling of the variable. Bassam indicates concern of too much expressiveness with nesting that may allow for properties to be created that are overly complex and too hard to understand. Discussion on asscociativity, clarified that it is right associativity and the syntax provides for explicit use of () for explicit association. The intent to not allow left association ? All agree to have at least the sequence_expr => sequence_expr at the top level. Open issue: Whether to support sequence_expr => prop_expr (i.e.) nesting. Actions: Surrendra will provide an example and description of nesting Members will review syntax and prepare proposal if there are alternate proposals to be due by Monday. Issue: Sem2 Remove check construct, Owner = Adam Prakash has concerns that there are some corners which only this functionality can support. Prakash will provide justification examample by email by Friday. Issue will be voted by email Monday. Issue: Syn1 Remove unary delay, Owner = Cindy Cindy discussed a potential proposal with John to preserve unary delay, but remove binary delay. The idea is to have the meaning the same whether the parantheses are used or not. Standalone leading [0] would be explicitly not allowed. Surrendra proposal was provided which Cindy awknowleges meets the desire of her issue. Surrendra indicates that it removes unnecessary parantheses. Erich indicated that it does not provide for leading delay. The proposal provides for parameterized delays of any non-zero integer value wherever delays appear. Cindy will prepare a proposal following John's suggestions by Sunday. Issue: Syn2 Replace seq by sequence Decision to have sequence, no objections. 2) New Issues {11.4} true as keyword by Adam, 2nd by John, 3rd by Cindy, 4th by Bassam Unnecessary keyword - all agree to remove. {11.6.3, 11.6.5} change and, or and intersect to &, |, && by Cindy Cindy feels that and, or are ugly and suggest using existing boolean operators in verilog. Surrendra indicates that or and and are already keywords. Steve indicated that there would be hard to understand and distinguish the boolean operators from the sequence operators. Also proposal for && for and, | for or and & for intersect. Roy indicates & has different precedence in verilog. Bassam indicates that style should be consistent either all characters or all keywords but not a mix of both. Steve expressed strong concern on DWG process for language design should be basis for review and SV-AC should not undertake language design from first principles. {11.6.8} Addition of non-overlapping sequence implication (->) by Cindy, second Erich, third John See email by Cindy. She suggests sequence implication to allow operator to have an operator (i.e. ->) in which the left operator starts one cycle later than the match of the right operator. Others indicated that there may not be sufficient need as the form can be achieved by starting a sequence by "1 ; ". 3) Review of document {11.9} System Tasks Steve indicated document is in process of update with DAS v1.0 system functions. {11.10} Property definition Erich suggested that property directives should be provided at the property level. Cindy suggsted that always be made explicit and require user to invoke one of them as opposed to having an implicit always. {11.11) Property instantiation in module There was clarification that properties can be instantiated in module as well as instances. Action is to update the document with explicit clarification on where property, sequence delcarations can be made. Review concluded at Sec 11.11 Meeting Concluded