Minutes SV-AC 10/31/02
Written by: Steve Meier

ATTN: Next SV-AC Meeting Nov12 9-12PST "face2face" 
	Location: SanJose,location specifics TBD
	Dial-in will be provided

Legend:
x = attended
- = missed
r = represented
. = not yet a member

[xxxxxx----x.] Faisal Haque (Cisco, Chairman)
[xxx-xxxxxxrx] Tom Fitzpatrick (Synopsys, Co-Chair)
[x--x-x-x--xr] Tom Anderson (0-in)
[-----------x] Jason Andrews (Axis)
[xxxxx-xxx--x] Roy Armoni (Intel)
[xxx-xxxxxxxx] Gail Dagan (Intel)
[--x-x--xxxxx] Simon Davidmann (Co-Design)
[xx-x-xxxrxx.] Surrendra Dudani (Synopsys)
[xxxxxxxxrxrx] Cindy Eisner (IBM)
[-----xxrrrxx] Peter Flake (Co-Design)
[xx-rx-xxxrrx] Harry Foster (Verplex)
[xxxrxx-xxx..] John Havlicek (Motorola)
[xx-xx-xxxxx.] Richard Ho (0-in)
[--x.........] Sagi Katz (Gallileo)
[xxxxxxxxxrx-] Adam Krolnik (LSI)
[-xxx-x--xx-x] David Lacey (HP, OVL Chairman)
[xxxxxxx---xx] Joseph Lu (Sun)
[xxxxxx--xxxx] Erich Marschner (Cadence)
[xxxxxx-x-x-x] Steve Meier (Synopsys)
[x...........] Hillel Miller (Motorola)
[-----------x] Paul Menchini (Menchini & Associates)
[-xxxxx-xxxx-] Prakash Narain (Real Intent)
[-xxxxxxxxxx-] Rajeev Ranjan (Real Intent)
[----xxxxxxx.] Ambar Sarkar (Paradigm Works)
[-xxxx-x-x...] Richard Stolzman (Verplex)
[x-x-xxxxxx-x] Andrew Seawright (0-in)
[xxxxx-xrxxxx] Bassam Tabbara (Novas)
[xxxx........] Yaron Wolfsthal (IBM)
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+------------ 10/31/02

Administrative:

Tom Fitzpatrick is resigning as co-chair to pursue other opportunities.
Stephen Meier has been appointed SV-AC co-chair.

1. Requirements Review
=======================
Scoring: 1 point for yes, -1 point for no
sorted by score

Tom: guidance to DWG, will definitely meet the core requirements

Adam: Concern on R74, there is need to have additional modeling to
support assertions such as a companion FSM.  There needs to be
an ability to preserve logic for verification tools (formal) similar
to defacto standard // synopsys translate_off.  Gail and Tom commented
that IFDEF could be used to meet this requirement and that exists within
System Verilog.  Adam commented that some tools (DC) require additional
steps (vpp) in order to utilize IFDEF's.

Richard: What is process within DWG, which requirements are getting addressed.

Tom: Focus of DWG effort is on the highest priorities, but some of the lower 
priorities may get covered in course of design.

Steve: DWG will report back which items are fulfilled in working document at
each step in process to track progress versus requirements.  Any requirement with
positive vote may be considered.  Negative vote indicates a requirement that
will not be considered without meeting SV-AC objections or clarification.

2. ICCAD Face to Face Meeting:
===========================
Faisal: Propose a face to face meeting Tues Nov 12th 9-12noon.  Erich offered
if Cadence can host and provide a teleconference bridge #.  Efforts were made to
accomodate known schedules and remote dialin will be scheduled.

3. Document Review
===============
Tom walk through Rev 0.6.5 of DWG working document.  The status within DWG of working document, combination of decisions (on semantics) and proposals in various status towards decision.  It has been shared as a status update and interim view of DWG progress to date.

4. Review Issues
=============

4.1 Issue raised about timeshift when N = 0, the results are not the same.

4.2 Clarification: sequences are more complex than illustration 11-3, need to indicate concurrent assertions can start at same time, document will be updated to reflect this.

4.3 Harry, Erich raised issues raised on syntax for regular expressions in terms of ability for users to make simple mistakes.  Needs further review

4.4 Clarification:  non-consecutive means that sequence may or may not be consecutive

4.5 Joseph:  How to specify sequence which must repeat until end of simulation (infinitely)
Erich: only way to do this is *[inf]

4.6 Erich: what is definition of sequence, needs further definition.

4.7 Adam: inconsistency in 11.6 BNF.  Tom indicates that intent is to allow multiple sequences in single statment, so BNF will be corrected.

4.8 Erich: current document only allows sequences with single clock.

4.9 Erich: semantics of sequence operations need more rigorous definitions including the infinite extension of sequences in formal.  

5.0 John:  Question on whether sequence operations with difference sample clocks can be combined.  Steve: The current document only assumes sequence operands with the single clock.  The resolution of multiple clocks is an open topic within DWG. 

5.2 Erich:  11.7.5 is still open proposal

5.3 Gail: what is support of clock synchronization in 11.7.5.  Tom indicates that the matched (and ended) provide means of referencing sequence completion as a condition for implication.  John indicated that matched only provides occurance of the end of sequence (not the start of sequence).

5.4 Erich: 11.9.1 proposed syntax may not support composition of properties, see it as an important issue.

5.5 Harry/Erich/Tom: Discussion on semantics of procedural instantation. Tom indicates that the semantics are designed to avoid false negatives.  Topic more discussion and analysis.


Meeting Concluded