Subject: Re: [sv-ac] Constraint implication, sequence implication, and transitions
From: John Havlicek (john.havlicek@motorola.com)
Date: Fri Nov 14 2003 - 13:55:49 PST
All:
I agree with Adam's points.
J.H.
> Date: Mon, 10 Nov 2003 17:25:50 -0600
> From: Adam Krolnik<krolnik@lsil.com>
> X-Accept-Language: en-us, en
> Cc: <sv-ec@eda.org>, <sv-ac@eda.org>
> Sender: owner-sv-ac@eda.org
> Precedence: bulk
>
>
> Hi Jay;
>
> It seems lavish to have 4 "implication" operators. [Verilog 2001 has none.]
>
> >---------------------
> >Summary of operators:
> >---------------------
>
> > => overlapping constraint implication
> > |-> overlapping sequence implication
> > |=> non-overlapping sequence implication
> > -> non-overlapping transition
>
> Seeing this summary, it does appear inconsistent when viewing the (non)overlapping
> attribute. Consistency would argue for at least swapping "->" and "=>".
> SV-AC has a proposal for constraints to be property instances, so one may see
> properties and boolean constraints together.
>
> I would hope we could switch constrain and covergroup operators to match the
> assertion implication operators.
>
>
> -> overlapping constraint implication
> |-> overlapping sequence implication
> |=> non-overlapping sequence implication
> => non-overlapping transition
>
>
> If coverage transitions are the only use of "=>", maybe we should consider
> reusing another operator which more closely matches the next cycle operation.
>
> coverpoint mode {
> bins sl = (small ##1 large);
>
>
> Thanks Jay!
>
> Adam Krolnik
> Verification Mgr.
> LSI Logic Corp.
> Plano TX. 75074
>
>
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