Subject: Re: [sv-ac] Constraint implication, sequence implication, and transitions
From: Adam Krolnik (krolnik@lsil.com)
Date: Mon Nov 10 2003 - 15:25:50 PST
Hi Jay;
It seems lavish to have 4 "implication" operators. [Verilog 2001 has none.]
>---------------------
>Summary of operators:
>---------------------
> => overlapping constraint implication
> |-> overlapping sequence implication
> |=> non-overlapping sequence implication
> -> non-overlapping transition
Seeing this summary, it does appear inconsistent when viewing the (non)overlapping
attribute. Consistency would argue for at least swapping "->" and "=>".
SV-AC has a proposal for constraints to be property instances, so one may see
properties and boolean constraints together.
I would hope we could switch constrain and covergroup operators to match the
assertion implication operators.
-> overlapping constraint implication
|-> overlapping sequence implication
|=> non-overlapping sequence implication
=> non-overlapping transition
If coverage transitions are the only use of "=>", maybe we should consider
reusing another operator which more closely matches the next cycle operation.
coverpoint mode {
bins sl = (small ##1 large);
Thanks Jay!
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
This archive was generated by hypermail 2b28 : Mon Nov 10 2003 - 15:29:54 PST