Subject: RE: [sv-ac] unnecessary semicolon?
From: Bassam Tabbara (bassam@novas.com)
Date: Tue Nov 04 2003 - 12:19:11 PST
John/Adam,
Which semicolon you mean ? Anyway, both as I recall were additions by
the "syntax committee" under "like-Verilog" additions. So I think (vote
?) better stick to as is.
sequence e1; // <<<<<< this one ?
@(posedge clk) $rose(ready) ##1 proc1 ##1 proc2 ; // <<< I think you
mean this one, right ?
endsequence
Thx.
-Bassam.
-- Dr. Bassam Tabbara Technical Manager, R&D Novas Software, Inc.http://www.novas.com (408) 467-7893
> -----Original Message----- > From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On > Behalf Of Adam Krolnik > Sent: Monday, November 03, 2003 1:57 PM > To: john.havlicek@motorola.com > Cc: sv-ac@eda.org > Subject: Re: [sv-ac] unnecessary semicolon? > > > > > I'll vote for optional semicolons. > > Precedence for the next standard... > > Adam > > >
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