Subject: RE: [sv-ac] Property definition in $root
From: David W. Smith (david.smith@synopsys.com)
Date: Tue Oct 28 2003 - 11:21:43 PST
Greetings,
Not only are properties and sequences allowd in $root but they are also
allowed in packages (as defined in the proposal which is not in BC but in
the separate compilation working group). The limitation does not single out
assertion statement but refer to a whole class of statements that have been
suggested to be removed from $root. This proposal is currently being voted
on by the working group to move it to the next step in the process.
Regards
David
-----Original Message-----
From: owner-sv-ac@eda.org [mailto:owner-sv-ac@eda.org] On Behalf Of Armoni,
Roy
Sent: Tuesday, October 28, 2003 8:43 AM
To: System Verilog Assertion
Subject: [sv-ac] Property definition in $root
Hi everyone,
I see in <http://www.eda.org/sv-bc/sep_comp/Packages_Sep_V5.pdf>
http://www.eda.org/sv-bc/sep_comp/Packages_Sep_V5.pdf that BC are proposing
to disallow assert statements in $root. I believe this is o.k. as long as
it is allowed to define properties in $root, otherwise, we may need to
compile the same property over and over in every module.
What do you think?
Regards,
Roy
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