Re: [sv-ac] Call to vote: Due May 2

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> Mantis 3213 ____ Yes __x__ No
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> http://www.verilog.org/mantis/view.php?id=3213
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> http://www.eda-stds.org/mantis/file_download.php?file_id=4961&type=bug
> <http://www.eda-stds.org/mantis/file_download.php?file_id=4961&type=bug>
>
>
>

Why not simplify this proposal? Instead of defining the new concept of
"concurrent context", and doing a global substitute of "sampled value",
why not just state the concept as follows:

1. The sampled value of a variable is the value that was sampled in
     the preponed region. (No change from current LRM)
2. Variables used in concurrent assertions are evaluated as follows:
     1. Static variables use the sampled value
     2. Automatic variables use the current value
     3. Sequence methods such as triggered() use the current value
     4. Checker inputs use the sampled value.
     4. Free checker variables use the current value.

This definition would give all the functionality you want, but the LRM
would not be making absurd statements like, "The sampled value of a free
  checker variable is the current value"

Then, we can do one of the following:

Either change the definition of the $sampled function so that it returns
the value of its expression argument evaluated according to the rules in
sec 16.x.y

OR

Keep the definition of $sampled the same and introduce a new function
which does evaluate according to the above rules.

The resulting proposal would be much simpler, there would be less change
to the LRM, and I think much more understandable.

Tom

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