[sv-ac] Asynchronous techniques Versus Global Clock (Cycle based Semantic s)


Subject: [sv-ac] Asynchronous techniques Versus Global Clock (Cycle based Semantic s)
From: Vassilios.Gerousis@Infineon.Com
Date: Sat Aug 24 2002 - 02:00:02 PDT


My thanks for Ambar and Adam for continued discussions on this.

 I can summarize the discussion from Ambar's point of view of how to define and use assertion on block boundaries that do not have clocking techniques (Global Asynchronous and local synchronous - GALS). This is usually done on the basis of handshake signals (such as request, acknowledge, grant and complete transactions). This can be modeled into two MOCs (one is event driven and the other one is transaction based). The two MOCs can be supported with SystemVerilog language (event driven and the interface mechanism). Cycle based semantics is not appropriate for this design techniques. Although Cycle Based speed up execution, it should be understood, that we must have assertion capabilities to support all three MOCs (model of computations). I believe that SystemVerilog 3.0 supports all of these MOCs in the assertion based methodology. The assertion improvement through PSL and OVA should not prohibit the use of assertions in the transaction MOC or the event driven MOC.

GALS and other techniques like self timed logic are becoming increasingly important for nano-based designs where global clocks is extremely harder to implement and to control (both timing and power). SystemVerilog assertions should not prohibit the use of these design techniques.

Best Regards

Vassilios

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