Synthesis Interoperability Working Group - siwg/hm By Thread
- International HDL Conference 2000 CALL FOR PAPERS Jayaram Bhasker (Fri Dec 10 1999 - 11:22:45 PST)
- 23-1 to 23-17: Allow clock edges in procedures Rich Hatcher (Wed Dec 15 1999 - 13:48:25 PST)
- 23-18 to 23-20 Allow clock edges in procedures Rich Hatcher (Wed Dec 15 1999 - 14:57:11 PST)
- Attribute Discussion for Level 2 Sanjiv Narayan (Thu Dec 16 1999 - 15:47:50 PST)
- Re: VHDL Synthesis Interoperability Working Group: Agenda for Dec 17 teleconference Jayaram Bhasker (Fri Dec 17 1999 - 06:32:39 PST)
- 99-12-17 Meeting minutes Tim Davis (Fri Dec 17 1999 - 13:46:51 PST)
- 18-1: Support initial values Rich Hatcher (Mon Dec 20 1999 - 10:08:04 PST)
- Forward: An example David Bishop (Tue Dec 21 1999 - 18:42:27 PST)
- FW: Questions David Bishop (Tue Dec 28 1999 - 10:21:54 PST)
- [Fwd: Re: FW: Questions David Bishop (Thu Dec 30 1999 - 09:38:07 PST)
- Re: 5: Support user defined attributes lancet@us.ibm.com (Thu Dec 30 1999 - 12:30:06 PST)
- 14: Extend arithmetic operator support lancet@us.ibm.com (Thu Dec 30 1999 - 13:23:15 PST)
- 16: Multiple index constraints lancet@us.ibm.com (Thu Dec 30 1999 - 13:36:35 PST)
- 18: Support initial value lancet@us.ibm.com (Fri Dec 31 1999 - 08:25:17 PST)
- how to search the mailing list lily@khorshid.ece.ut.ac.ir (Sun Jan 02 2000 - 23:43:01 PST)
- Y2K Test David Bishop (Tue Jan 04 2000 - 17:52:27 PST)
- VHDL Synthesis Interoperability Working Group: Agenda for Jan 21 teleconference Jayaram Bhasker (Wed Jan 12 2000 - 10:57:26 PST)
- Re: HDL Conference info now on-line! Jayaram Bhasker (Thu Jan 20 2000 - 12:36:15 PST)
- SIWG Teleconference minutes: Jan 21, 2000 Jim Lewis (Fri Jan 21 2000 - 13:48:45 PST)
- Call for Papers IEEE/DATC EDP 2000 David Bishop (Fri Jan 21 2000 - 17:29:58 PST)
- [Fwd: RE: SIWG Teleconference minutes: Jan 21, 2000] David Bishop (Mon Jan 24 2000 - 12:08:28 PST)
- [Fwd: RE: SIWG Teleconference minutes: Jan 21, 2000] David Bishop (Mon Jan 24 2000 - 12:09:48 PST)
- [Fwd: Re: SIWG Teleconference minutes: Jan 21, 2000] David Bishop (Mon Jan 24 2000 - 12:41:04 PST)
- #23 Allow clock edges in procedures VhdlCohen@aol.com (Mon Jan 24 2000 - 17:43:44 PST)
- [Fwd: Reals and Will it be Supported] David Bishop (Fri Jan 28 2000 - 06:36:49 PST)
- 33: Support for floating point types lancet@us.ibm.com (Fri Jan 28 2000 - 12:58:56 PST)
- FW: A Compromise? (Floating Point Package Issue) David Bishop (Sun Jan 30 2000 - 16:21:19 PST)
- (no subject) owner-siwg@eda.org (Sat Feb 05 2000 - 09:25:36 PST)
- 33: Support for Real Numbers : Proposal Tim Davis (Sun Feb 06 2000 - 21:30:37 PST)
- [Fwd: JOURNAL OF SYSTEMS ARCHITECTURE, Final Call For Papers] David Bishop (Tue Feb 08 2000 - 10:13:34 PST)
- VHDL Synthesis Interoperability Working Group: Agenda for Feb 18 teleconference Jayaram Bhasker (Tue Feb 08 2000 - 12:54:10 PST)
- 23-21 Allo clock edges in procedures Rich Hatcher (Wed Feb 09 2000 - 06:00:45 PST)
- Minutes for Today's Phone Conference Patrick Bryant (Fri Feb 18 2000 - 12:41:38 PST)
- Call for Papers IEEE/DATC EDP 2000 - DEADLINE, 2/25/2000] David Bishop (Fri Feb 18 2000 - 12:51:03 PST)
- 1076.6 level 2 enhancement status lancet@us.ibm.com (Fri Feb 18 2000 - 14:07:31 PST)
- 29: Extend support of global signals Rich Hatcher (Tue Feb 22 2000 - 08:29:23 PST)
- 1076.6 Level 1 error Rich Hatcher (Tue Feb 22 2000 - 08:36:13 PST)
- [Fwd: RE: 1076.6 Level 1 error] David Bishop (Tue Feb 22 2000 - 09:48:08 PST)
- Feb 18 meeting minutes CORRECTION Jayaram Bhasker (Tue Feb 22 2000 - 11:07:40 PST)
- AW: 29: Extend support of global signals Wolfgang.Ecker@infineon.com (Sat Feb 26 2000 - 10:31:48 PST)
- (no subject) lily@khorshid.ece.ut.ac.ir (Tue Feb 29 2000 - 05:55:41 PST)
- Re: RTL Synthesis Standard ... Jayaram Bhasker (Tue Feb 29 2000 - 06:12:30 PST)
- Generics Tim Davis (Wed Mar 01 2000 - 10:43:18 PST)
- March 8th Meeting Location for 1076.6 Patrick Bryant (Thu Mar 02 2000 - 09:00:36 PST)
- VHDL Synthesis Interoperability Working Group: Agenda for Mar 8 face2face Jayaram Bhasker (Fri Mar 03 2000 - 09:48:58 PST)
- Group Direction Jim Lewis (Mon Mar 20 2000 - 08:23:53 PST)
- #35 + #35 subclass, Combinational Logic After Clock (?35.??) Jim Lewis (Mon Mar 20 2000 - 08:23:37 PST)
- SIWG Meeting March 8, 2000 Jim Lewis (Mon Mar 20 2000 - 07:13:54 PST)
- Bill Anker - where are you? Jayaram Bhasker (Mon Mar 20 2000 - 12:22:10 PST)
- IEEE/DATC EDP 2000 - Advance Program David Bishop (Sun Mar 26 2000 - 18:13:57 PST)
- VHDL Synthesis Interoperability Working Group: Agenda for Apr 10 teleconference Jayaram Bhasker (Mon Apr 03 2000 - 11:55:44 PDT)
- Level 2 standardization approach Rich Hatcher (Thu Apr 27 2000 - 12:28:32 PDT)
- VHDL Synthesis Interoperability Working Group: Agenda for May 24 teleconference Jayaram Bhasker (Wed May 03 2000 - 10:47:49 PDT)
- Meeting Minutes April 11??? Jim Lewis (Fri May 05 2000 - 23:15:36 PDT)
- level 2 syntax status Lance Thompson (Tue May 16 2000 - 19:59:06 PDT)
- 33: Support floating point types Lance Thompson (Tue May 16 2000 - 20:25:00 PDT)
- [Fwd: Re: Support floating point types David Bishop (Wed May 17 2000 - 05:10:38 PDT)
- [Fwd: Re: Support floating point types] David Bishop (Wed May 17 2000 - 18:10:02 PDT)
- [Fwd: Re: 33: Support floating point types] David Bishop (Thu May 18 2000 - 11:59:40 PDT)
- Using the SIWG list David Bishop (Thu May 18 2000 - 12:10:22 PDT)
- Meeting minutes: Telecon on May 24 Jayaram Bhasker (Thu Jun 01 2000 - 06:12:12 PDT)
- Telecon WG meeting in June cancelled Jayaram Bhasker (Sun Jun 04 2000 - 04:34:18 PDT)
- AW: [Fwd: Re: Support floating point types] Wolfgang.Ecker@infineon.com (Wed Jun 14 2000 - 02:28:37 PDT)
- 33: Support for Floating Point Types Jim Lewis (Wed Jun 14 2000 - 08:27:34 PDT)
- VHDL Synthesis Interoperability Working Group: Agenda for July 28 teleconference Jayaram Bhasker (Fri Jul 14 2000 - 11:54:33 PDT)
- SIWG Agenda (for Synthesis Semantics discussion on 28th July) Vinaya Kumar (Tue Jul 25 2000 - 01:01:59 PDT)
- SEM 9: LoadEnable + Clock, Semantics Issue Jim Lewis (Fri Jul 28 2000 - 10:51:40 PDT)
- SEM 2: Alternate form of Asynchronous Resets Jim Lewis (Fri Jul 28 2000 - 11:01:11 PDT)
- SEM 2: Priority of Reset and Set Jim Lewis (Fri Jul 28 2000 - 11:05:31 PDT)
- Scan FF from the TI data book Rich Hatcher (Fri Jul 28 2000 - 11:30:04 PDT)
- case statement with cock edge -- an example VhdlCohen@aol.com (Fri Jul 28 2000 - 11:31:13 PDT)
- SEM 6: Multiple Clock Edges Jim Lewis (Fri Jul 28 2000 - 12:02:42 PDT)
- AW: SEM 9: LoadEnable + Clock, Semantics Issue Wolfgang.Ecker@infineon.com (Mon Jul 31 2000 - 23:07:59 PDT)
- SEM 13: Alternate form of Asynchronous Resets Jayaram Bhasker (Tue Aug 01 2000 - 08:39:52 PDT)
- Are feedback circuits prohibited by the standard? Tim Davis (Tue Aug 01 2000 - 12:02:10 PDT)
- Updated semantic Issues list Vinaya Kumar (Thu Aug 03 2000 - 06:38:24 PDT)
- VHDL Synthesis Interoperability Working Group: Agenda for Aug 11'00 Jayaram Bhasker (Thu Aug 03 2000 - 11:56:37 PDT)
- SEM15: Wait on Jim Lewis (Fri Aug 11 2000 - 10:36:11 PDT)
- AW: SEM15: Wait on Wolfgang.Ecker@infineon.com (Fri Aug 11 2000 - 11:23:41 PDT)
- IEEE Library Tim Davis (Tue Aug 15 2000 - 17:05:22 PDT)
- Meeting Minutes for SIWG meeting on Aug 11, 2000. Vinaya Singh (Wed Aug 16 2000 - 05:17:21 PDT)
- VHDL Synthesis Interoperability Working Group: Agenda for Sept 8'00 Jayaram Bhasker (Tue Aug 29 2000 - 09:09:45 PDT)
- [Fwd: Final Call for Papers, NOTE 9/22/00 deadline extension] David Bishop (Fri Sep 15 2000 - 10:57:29 PDT)
- SEM-16 (Generic modeling for edge sensitive storage) Vinaya Kumar (Mon Sep 18 2000 - 03:47:36 PDT)
- SEM-15: "Wait on ... until" Vinaya Kumar (Mon Sep 18 2000 - 05:29:44 PDT)
- SEM-6 (Signal assigned under different clock edges) Vinaya Kumar (Tue Sep 19 2000 - 00:21:00 PDT)
- Semantic Issues List Vinaya Kumar (Tue Sep 19 2000 - 01:10:33 PDT)
- SEM-16 (Generic modeling for edge sensitive storage) Vinaya Kumar (Wed Sep 20 2000 - 07:15:02 PDT)
- Goals of Level 2?, Sem 16, ... Jim Lewis (Wed Sep 20 2000 - 08:59:30 PDT)
- SEM16, Asynchronous Loads Jim Lewis (Wed Sep 20 2000 - 08:40:47 PDT)
- VHDL Synthesis Interoperability Working Group: Agenda for Sept 29'00 Jayaram Bhasker (Fri Sep 22 2000 - 09:18:49 PDT)
- Re: Floating point library? Help! J. Bhasker (Fri Sep 22 2000 - 12:09:14 PDT)
- Re: Floating point library? Help! lancet@us.ibm.com (Fri Sep 22 2000 - 13:53:16 PDT)
- dual-edge clocking Evan Lavelle (Thu Oct 12 2000 - 08:25:03 PDT)
- [Fwd: http://www.eda.org/siwg/] Sanjiv Narayan (Thu Oct 12 2000 - 23:28:04 PDT)
- SIWG telecon for Oct 20 is CANCELLED Jayaram Bhasker (Fri Oct 13 2000 - 09:53:36 PDT)
- Re: SLR Balloting Feedback Request (fwd) Jayaram Bhasker (Mon Oct 16 2000 - 11:25:56 PDT)
- Output netlists: naming conventions Evan Lavelle (Wed Oct 18 2000 - 07:31:22 PDT)
- Are we allowing Unconstrained Arrays in components? VhdlCohen@aol.com (Thu Oct 19 2000 - 09:50:15 PDT)
- Re: Joanne DeGroat J. Bhasker (Thu Nov 02 2000 - 13:51:01 PST)
- Lost track: Are we allowing text files for definition of ROMs? VhdlCohen@aol.com (Sun Nov 05 2000 - 17:07:53 PST)
- VHDL Synthesis Interoperability Working Group: Agenda for Nov 17'00 J. Bhasker (Mon Nov 13 2000 - 11:34:04 PST)
- Re: VHDL Synthesis Interoperability Working Group: Agenda for Nov17'00 meeting Vinaya Singh (Thu Nov 16 2000 - 18:21:25 PST)
- Re: VHDL Synthesis Interoperability Working Group:Agenda for Nov 17'00 Vinaya Singh (Mon Nov 20 2000 - 18:36:25 PST)
- SEM-10 Modeling : Guarded example VhdlCohen@aol.com (Wed Nov 22 2000 - 20:58:45 PST)
- SEM-10 Modeling : Guarded example Rich W Hatcher (Mon Nov 27 2000 - 13:37:25 PST)
- SEM 16: Generic modeling for edge sensitive storage, when "<clock_edge>" is in the condition Vinaya Kumar (Fri Dec 01 2000 - 03:42:02 PST)
- Re: SEM 16: Generic modeling for edge sensitive storage, when "<clock_edge>" is in the condition Vinaya Singh (Mon Dec 04 2000 - 04:56:22 PST)
- SEMSEM3: Modeling edge-sensitive storage elements using the "wait until" statement Vinaya Kumar (Thu Dec 07 2000 - 05:01:48 PST)
- SEM 16: Generic modeling for edge sensitive storage, when "<clock_edge>" is in the condition Vinaya Kumar (Thu Dec 07 2000 - 05:07:32 PST)
- Re: SEMSEM3: Modeling edge-sensitive storage elements using the "wait until" ... VhdlCohen@aol.com (Sat Dec 09 2000 - 15:22:07 PST)
- Sensitivity Lists & Level 2 Jim Lewis (Sun Dec 10 2000 - 12:25:49 PST)
- SEM 17: Modeling a storage element with dual clock edges. Vinaya Kumar (Tue Dec 12 2000 - 04:15:47 PST)
- Re: SEMSEM3: Modeling edge-sensitive storage elements using the "wait until" statement Vinaya Kumar (Tue Dec 12 2000 - 05:22:28 PST)
- VHDL Synthesis Interoperability Working Group: Agenda for Dec 15 '00 J. Bhasker (Wed Dec 13 2000 - 11:49:17 PST)
- [Fwd: FDL'01 CFP] David Bishop (Thu Dec 14 2000 - 06:04:54 PST)
- Re: VHDL Synthesis Interoperability Working Group: Agenda for Dec 15 '00 Vinaya Kumar (Fri Dec 15 2000 - 08:35:56 PST)
- SEM3: non-static loop -- what about the following? VhdlCohen@aol.com (Fri Dec 15 2000 - 16:20:40 PST)
- Is Level 2 as good as Behavioral AMICAL ? VhdlCohen@aol.com (Sun Dec 17 2000 - 17:54:25 PST)
- Dual edge clocking in Synopsys Rich W Hatcher (Wed Dec 20 2000 - 14:15:47 PST)
- SEM-3: Should we extend level 2 into behavioral synthesis? VhdlCohen@aol.com (Mon Dec 25 2000 - 15:01:44 PST)
- Re: Should we extend level 2 into behavioral synthesis? Rich W Hatcher (Wed Jan 03 2001 - 06:54:50 PST)
- AW: Should we extend level 2 into behavioral synthesis? Wolfgang.Ecker@infineon.com (Wed Jan 03 2001 - 12:21:14 PST)
- SEM4: Modeling Level Sensitive Latches Vinaya Kumar (Fri Jan 12 2001 - 07:15:24 PST)
- SEM 18+ : Sensitivity Lists and Registers Jim Lewis (Tue Jan 16 2001 - 12:20:50 PST)
- Next 1076.6 WG meeting with IHDL conference on Feb 27 J. Bhasker (Wed Jan 17 2001 - 06:52:09 PST)
- SEM4: Modeling Level Sensitive Latches Vinaya Kumar (Fri Jan 19 2001 - 02:34:30 PST)
- Submission deadline extension for the Special Sessions on Modern Digital System Synthesis at SCI'2001] David Bishop (Wed Feb 07 2001 - 07:50:52 PST)
- SIWG Meeting At IHDL 2/27/2001 Jim Lewis (Wed Mar 07 2001 - 03:51:22 PST)
- Vice Chair for 1076.6 J. Bhasker (Wed Mar 07 2001 - 13:07:29 PST)
- VHDL Synthesis Interoperability Working Group: Agenda for Mar 23, '01 J. Bhasker (Tue Mar 20 2001 - 09:11:50 PST)
- Attributes for Level 2 (v1.3, 06/99) Sanjiv Narayan (Thu Mar 22 2001 - 09:17:09 PST)
- Attributes for Level 2 (v1.0, 01/98) Sanjiv Narayan (Thu Mar 22 2001 - 09:16:19 PST)
- SEM15:Modeling edge-sensitive storage with a "wait on ... until" or "wait until ... Vinaya Kumar (Fri Mar 23 2001 - 06:07:41 PST)
- Re: SEM15:Modeling edge-sensitive storage with a "wait on ... until" or "wait until ... Vinaya Kumar (Fri Mar 23 2001 - 06:47:24 PST)
- SEM3: Modeling edge-sensitive storage elements using the "wait until" or "wait on ... until" statements Vinaya Kumar (Fri Mar 23 2001 - 06:50:19 PST)
- Survey: Meeting for DAC Jim Lewis (Thu Mar 29 2001 - 14:00:44 PST)
- VHDL Synthesis Interoperability Working Group: Agenda for May 18, '01 J. Bhasker (Tue May 15 2001 - 07:17:14 PDT)
- Re: VHDL Synthesis Interoperability Working Group: Agenda for May 18, '01 Vinaya Kumar (Fri May 18 2001 - 05:43:21 PDT)
- Minutes of SIWG Telecon of Mar 23, 2001 Sanjiv Narayan (Fri May 18 2001 - 06:12:44 PDT)
- FDL 2001 Advance Program Announcement Jayaram Bhasker (Wed Jul 11 2001 - 07:58:20 PDT)
- SIWG upcomming teleconference meetings Jim Lewis (Wed Jul 18 2001 - 10:01:48 PDT)
- Modeling ROMs and RAMs VhdlCohen@aol.com (Wed Jul 18 2001 - 10:50:42 PDT)
- HDLCon 2002 Call for Papers Jayaram Bhasker (Thu Jul 19 2001 - 08:40:54 PDT)
- Fwd: Semantic Issues: SIWG Meeting Agenda Jim Lewis (Wed Jul 25 2001 - 12:39:03 PDT)
- VHDL SWIG Meeting Agenda for Friday July 27 Jim Lewis (Wed Jul 25 2001 - 12:40:08 PDT)
- Re: SEM15:Modeling edge-sensitive storage with a "wait on ... until" or "wait until ... Vinaya Kumar (Wed Jul 25 2001 - 23:03:10 PDT)
- Attribute discussion for July 27 Teleconference Sanjiv Narayan (Thu Jul 26 2001 - 06:20:51 PDT)
- Meeting Minutes from 27 July, 2001 Pat Bryant (Mon Jul 30 2001 - 09:36:12 PDT)
- Test -- Please ignore VhdlCohen@aol.com (Mon Jul 30 2001 - 09:50:13 PDT)
- Assigning / testing different sizes -- shouldn't we restrict the use? VhdlCohen@aol.com (Fri Aug 03 2001 - 14:10:34 PDT)
- Implementation Selection Directives Sanjiv Narayan (Tue Aug 14 2001 - 05:01:33 PDT)
- My Comments: Implementation Selection Directives Pat Bryant (Wed Aug 15 2001 - 10:38:36 PDT)
- SEM4: Modeling Level Sensitive Latches Vinaya Kumar (Wed Aug 15 2001 - 21:49:51 PDT)
- Modeling Style updates Vinaya Kumar (Wed Aug 15 2001 - 22:25:12 PDT)
- Callin details for tomorrow's 1076.6 WG mtg Jayaram Bhasker (Thu Aug 16 2001 - 06:38:53 PDT)
- State Machine Directives Sanjiv Narayan (Fri Aug 17 2001 - 05:12:40 PDT)
- Minutes of SIWG meeting of Aug 17 Sanjiv Narayan (Sat Sep 01 2001 - 04:29:15 PDT)
- SIWG upcomming teleconference meetings Jim Lewis (Mon Oct 01 2001 - 14:50:30 PDT)
- Call details for WG mtg on Oct 26, 2001 J. Bhasker (Fri Oct 19 2001 - 13:35:58 PDT)
- Modeling Style Updates Vinaya Kumar (Thu Oct 25 2001 - 05:50:46 PDT)
- Multiplexer directives Jim Lewis (Thu Oct 25 2001 - 20:59:05 PDT)
- Meeting Reminder: Friday Oct 26th Jim Lewis (Thu Oct 25 2001 - 22:07:40 PDT)
- Multiplexer directives Jim Lewis (Thu Oct 25 2001 - 22:07:46 PDT)
- Semantics of assigning to 'X' and '-' Jim Lewis (Fri Oct 26 2001 - 11:29:31 PDT)
- Minutes of SIWG meeting of Oct 26 Jim Lewis (Fri Oct 26 2001 - 11:29:36 PDT)
- Teleconference on Nov 26 J. Bhasker (Wed Nov 21 2001 - 12:39:58 PST)
- Meeting Reminder: Nov 26th 7:30am PST, 10:30am EST Jim Lewis (Sun Nov 25 2001 - 20:00:44 PST)
- Multiplexer directives in VHDL Synthesis Sanjiv Narayan (Mon Nov 26 2001 - 01:28:38 PST)
- Attribute for Latch Gate Identification Jim Lewis (Mon Nov 26 2001 - 14:13:06 PST)
- Meeting meeting for 26th November, 2001 Pat Bryant (Wed Nov 28 2001 - 12:37:43 PST)
- HDL Con Paper: Extensions to the VHDL RTL Synthesis Standard Jim Lewis (Tue Dec 11 2001 - 09:45:40 PST)
- VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper: VhdlCohen@aol.com (Tue Dec 11 2001 - 21:23:08 PST)
- Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper Jim Lewis (Wed Dec 12 2001 - 00:49:57 PST)
- Fwd: Implicit FSMs style with mutiple clocks VhdlCohen@aol.com (Wed Dec 12 2001 - 13:45:33 PST)
- VHDL Synthesis Interoperability Working Group meeting: Dec 17, 2001 J. Bhasker (Wed Dec 12 2001 - 14:11:07 PST)
- Re: Implicit FSMs style with mutiple clocks VhdlCohen@aol.com (Fri Dec 14 2001 - 23:31:11 PST)
- Sem 4.1 (variables) / ?4.2? Jim Lewis (Sun Dec 16 2001 - 23:22:19 PST)
- ROM definitions in VHDL VhdlCohen@aol.com (Sun Dec 16 2001 - 23:22:12 PST)
- Attributes Proposal Sanjiv Narayan (Mon Dec 17 2001 - 03:59:14 PST)
- Telecon details for VHDL Synthesis Interoperability WG Meeting on Jan 21, 2002 J. Bhasker (Wed Jan 16 2002 - 09:32:54 PST)
- More Meetings Jim Lewis (Wed Jan 16 2002 - 12:51:13 PST)
- Need clarification on Numeric_Unsigned/Signed/Extra & IEEE VhdlCohen@aol.com (Fri Jan 18 2002 - 13:50:19 PST)
- Meeting Reminder: Monday 10:15 am EST. Jim Lewis (Sun Jan 20 2002 - 23:25:17 PST)
- [Fwd: Re: VHDL Synthesis Interoperability Working Group meeting: Dec 17, 2001] Vinaya Singh (Mon Jan 21 2002 - 04:13:14 PST)
- Next Meeting 2/11 Jim Lewis (Mon Jan 21 2002 - 07:58:53 PST)
- FW: FW: Need clarification on Numeric_Unsigned/Signed/Extra & IEE E Pat Bryant (Tue Jan 22 2002 - 09:51:44 PST)
- Merging 1076.3 and 1076.6 Pat Bryant (Tue Jan 22 2002 - 12:55:27 PST)
- Numeric_Unsigned/Signed/Extra suggestions for next packages VhdlCohen@aol.com (Wed Jan 23 2002 - 11:14:00 PST)
- Request for DC non-compliance examples. Robert Anderson (Fri Jan 25 2002 - 16:39:53 PST)
- Draft 1.9 Jayaram Bhasker (Mon Jan 28 2002 - 07:27:30 PST)
- AW: Request for DC non-compliance examples. Wolfgang.Ecker@infineon.com (Tue Jan 29 2002 - 01:48:23 PST)
- Re: Draft 1.9 // syn_encoding vs syn_state_machine VhdlCohen@aol.com (Wed Jan 30 2002 - 12:21:26 PST)
- syn_noprune vs syn_keep VhdlCohen@aol.com (Wed Jan 30 2002 - 12:25:16 PST)
- VHDL Synthesis Interoperability WG meeting: Feb 11, 2002: call details Jayaram Bhasker (Mon Feb 04 2002 - 10:57:07 PST)
- Meeting Monday 2/11 at 10:15 am EST (7:15 am PST) Jim Lewis (Sun Feb 10 2002 - 19:43:37 PST)
- Attributes for todays meeting Sanjiv Narayan (Mon Feb 11 2002 - 05:13:40 PST)
- SIWG Meeting Jim Lewis (Mon Feb 11 2002 - 15:39:36 PST)
- attributes Robert Anderson (Mon Feb 11 2002 - 18:17:41 PST)
- Need to get moving onNumeric_Unsigned/Signed/Extra and more VhdlCohen@aol.com (Sun Feb 17 2002 - 11:18:00 PST)
- From Ben: Re: SEM4: Modeling Level Sensitive Latches Jim Lewis (Mon Feb 25 2002 - 11:18:22 PST)
- VHDL Synthesis WG: Next meeting: Mar 4 - call details Jayaram Bhasker (Mon Feb 25 2002 - 11:26:31 PST)
- FF models as per LEVEL2 Vinaya Singh (Tue Feb 26 2002 - 07:13:53 PST)
- CFP FDL'02 Ch. Grimm (Wed Feb 27 2002 - 05:38:37 PST)
- Meeting Monday 3/4 at 10:15 am EST (7:15 am PST)] Jim Lewis (Sun Mar 03 2002 - 22:50:23 PST)
- Agenda Change: Meeting Monday 3/4 at 10:15 am EST (7:15 am PST) Jim Lewis (Mon Mar 04 2002 - 06:58:48 PST)
- Fwd: Re: FF models as per LEVEL2 Sanjana Nair (Mon Mar 04 2002 - 09:49:18 PST)
- [Fwd: Re: Meeting Monday 3/4 at 10:15 am EST (7:15 am PST)]] Vinaya Singh (Tue Mar 05 2002 - 07:05:55 PST)
- SIWG meeting at HDLCon Jim Lewis (Thu Mar 07 2002 - 07:32:54 PST)
- SEM4: Further Questions Jim Lewis (Thu Mar 07 2002 - 08:49:02 PST)
- No Meeting at HDLCon Jim Lewis (Fri Mar 08 2002 - 12:55:54 PST)
- Next Meeting is Monday 3/18 10:15 EST Jim Lewis (Fri Mar 08 2002 - 13:48:05 PST)
- Meeting Reminder: Monday 3/18 10:15 EST Jim Lewis (Fri Mar 15 2002 - 16:54:00 PST)
- Attributes draft for discussion Sanjiv Narayan (Mon Mar 18 2002 - 06:32:54 PST)
- Latest copy of the HDLCon Paper Jim Lewis (Mon Mar 18 2002 - 09:32:11 PST)
- one_hot Multiplexers Jim Lewis (Mon Mar 18 2002 - 09:19:41 PST)
- FDL 2002 - Deadline approaching! Ch. Grimm (Tue Mar 19 2002 - 02:43:23 PST)
- Deadline approaching - FDL 2002! Ch. Grimm (Wed Mar 27 2002 - 02:35:56 PST)
- April 1 Meeting Details Jim Lewis (Fri Mar 29 2002 - 11:57:07 PST)
- ROM / RAM Update VhdlCohen@aol.com (Sun Mar 31 2002 - 19:24:12 PST)
- Minutes of the Telecon of 3/18/02 Sanjiv Narayan (Mon Apr 01 2002 - 03:03:37 PST)
- Meeting Minutes, 4/1/02 Jim Lewis (Mon Apr 01 2002 - 09:46:25 PST)
- Renaming "Pragma" Chapter to "Synthesis Directives" Sanjiv Narayan (Mon Apr 01 2002 - 10:27:56 PST)
- [Fwd: Re: SEM4: Modeling Level Sensitive Latches] Vinaya Singh (Tue Apr 09 2002 - 05:28:19 PDT)
- Re: Gated clock Vinaya Singh (Wed Apr 10 2002 - 21:33:36 PDT)
- Fw: Gated clock Pat Bryant (Thu Apr 11 2002 - 09:35:12 PDT)
- RE: Gated clock Jayaram Bhasker (Fri Apr 12 2002 - 06:12:51 PDT)
- Floating point synthesis, call for participation David Bishop (Fri Apr 12 2002 - 19:53:37 PDT)
- Meeting: Monday, April 22, 10:15 am EST Jim Lewis (Thu Apr 18 2002 - 13:33:26 PDT)
- Meeting: Monday, May 6, 10:15 am EST Jim Lewis (Sat May 04 2002 - 07:49:14 PDT)
- Meeting Minutes for 6 May 2002 Pat Bryant (Mon May 06 2002 - 11:27:17 PDT)
- VHDL Synthesis Interoperability Working Group Meeting: Monday May 20, 2002 Jayaram Bhasker (Mon May 13 2002 - 06:49:47 PDT)
- Re: Subj: Comments on P1076.6 (some) + (more) Jim Lewis (Mon May 20 2002 - 11:48:07 PDT)
- Phone Meeting Monday, June 3, 10:30 EST, 7:30 AM PST Jim Lewis (Fri May 31 2002 - 06:58:26 PDT)
- Minutes of May 20 SIWG Telecon Sanjiv Narayan (Mon Jun 03 2002 - 02:33:00 PDT)
- Meeting should have been listed at 10:15 am Jim Lewis (Mon Jun 03 2002 - 07:01:04 PDT)
- Meeting Minutes Monday, June 3 Jim Lewis (Mon Jun 03 2002 - 15:15:14 PDT)
- Re: Meeting Minutes Monday, June 3 VhdlCohen@aol.com (Mon Jun 03 2002 - 16:08:32 PDT)
- Re: Meeting Minutes Monday, June 3 Lance Thompson (Tue Jun 04 2002 - 08:45:59 PDT)
- LOG: John AI Status John Michael Williams (Tue Jun 04 2002 - 19:17:49 PDT)
- RTL_SYNTHESIS OFF for assertions John Michael Williams (Tue Jun 04 2002 - 19:26:23 PDT)
- Re: Meeting Minutes Monday, June 3 Lance Thompson (Thu Jun 06 2002 - 06:20:44 PDT)
- RE: Meeting Minutes Monday, June 3 Jayaram Bhasker (Thu Jun 06 2002 - 07:41:31 PDT)
- RE: Meeting Minutes Monday, June 3 Lance Thompson (Thu Jun 06 2002 - 07:58:30 PDT)
- RE: Meeting Minutes Monday, June 3 Jayaram Bhasker (Thu Jun 06 2002 - 09:22:06 PDT)
- Re: Meeting Minutes Monday, June 3 Lance Thompson (Thu Jun 06 2002 - 13:55:53 PDT)
- Re: Meeting Minutes Monday, June 3 Lance Thompson (Fri Jun 07 2002 - 08:46:56 PDT)
- Re: FW: Meeting Minutes Monday, June 3 Jbhasker7@aol.com (Wed Jun 12 2002 - 12:01:38 PDT)
- Action Items : Meeting Minutes Monday, June 3 Vinaya Singh (Sun Jun 16 2002 - 23:41:52 PDT)
- LOG: John AI Status John Michael Williams (Tue Jun 04 2002 - 19:48:42 PDT)
- Change in my contact info Jbhasker7@aol.com (Tue Jun 11 2002 - 06:03:13 PDT)
- [Fwd: Protected Types] Jim Lewis (Wed Jun 12 2002 - 11:45:50 PDT)
- Looking for peace in the VHDL and Verilog Attributes Jim Lewis (Thu Jun 13 2002 - 11:13:13 PDT)
- Analysis of Verilog Directives Sanjiv Narayan (Thu Jun 13 2002 - 13:08:18 PDT)
- Memory Modeling Attributes Sanjiv Narayan (Thu Jun 13 2002 - 12:27:23 PDT)
- Attribute Proposal: Latch_enable Jim Lewis (Thu Jun 13 2002 - 11:19:33 PDT)
- Meeting Monday June 17th 10:15 am until ... Jim Lewis (Fri Jun 14 2002 - 21:56:42 PDT)
- State Encoding Style Jim Lewis (Mon Jun 17 2002 - 05:40:54 PDT)
- June 17th Meeting Minutes Pat Bryant (Wed Jun 19 2002 - 11:03:21 PDT)
- Status of Conference Calls Jim Lewis (Tue Jul 09 2002 - 09:28:08 PDT)
- Status - Using the Reflector to get work done Jim Lewis (Wed Jul 24 2002 - 06:36:07 PDT)
- Proposal: SEM to Document Jim Lewis (Wed Jul 24 2002 - 06:40:06 PDT)
- Attributes discussion for Aug 12 meeting Sanjiv Narayan (Fri Aug 09 2002 - 05:26:18 PDT)
- Reminder for SIWG Teleconference on Aug 12, 2002 Sanjiv Narayan (Sun Aug 11 2002 - 23:06:24 PDT)
- Reminder for SIWG Teleconference on Aug 19, 2002 Sanjiv Narayan (Mon Aug 19 2002 - 06:03:27 PDT)
- Pats detailed minutes on Implementation Jim Lewis (Mon Aug 19 2002 - 12:37:11 PDT)
- Re: Suggestions for synthesis tools Jim Lewis (Fri Oct 18 2002 - 19:59:58 PDT)
- Review of 1076.6 draft 4.0 Jayaram Bhasker (Tue Oct 22 2002 - 06:47:22 PDT)
- Attribute KEEP vs NO_DUPLICATE & "clock uncertainty". VhdlCohen@aol.com (Tue Oct 22 2002 - 07:31:27 PDT)
- Draft 4.0 review Jayaram Bhasker (Wed Oct 23 2002 - 13:37:29 PDT)
- More Draft 4.0 review Jayaram Bhasker (Fri Oct 25 2002 - 04:55:13 PDT)
- More on 6.1.3.1 Jayaram Bhasker (Fri Oct 25 2002 - 14:00:00 PDT)
- FW: comment draft 1076.6D4 Jayaram Bhasker (Tue Oct 29 2002 - 04:50:53 PST)
- RE: Draft 4.0 review: IEEE Style Guide Jayaram Bhasker (Tue Oct 29 2002 - 04:54:02 PST)
- 6.1.3.2 review Jayaram Bhasker (Tue Oct 29 2002 - 12:00:06 PST)
- "Draft review -- Subprograms" Mohammad R.kakoee (Sat Nov 02 2002 - 03:14:54 PST)
- "Draft 4.0 review-- 8.1.2.1" Mohammad R.kakoee (Mon Nov 04 2002 - 07:38:49 PST)
- 1076.6 Draft v. 4.01 Posted John Michael Williams (Mon Nov 04 2002 - 10:07:04 PST)
- ENUM_ENCODING Extension + attribute FSM_INVALID_STATE Jim Lewis (Mon Dec 16 2002 - 16:42:59 PST)
- FW: Review Draft 1076.6 D5.00 is Posted Jayaram Bhasker (Tue Dec 31 2002 - 08:23:23 PST)
- RE: Feedback on Draft 5.0.0 Jayaram Bhasker (Tue Dec 31 2002 - 09:02:45 PST)
- RE: Review Draft 1076.6 D5.00 is Posted Jayaram Bhasker (Tue Dec 31 2002 - 09:27:43 PST)
- RE: More on ONE_HOT and ONE_COLD Jayaram Bhasker (Tue Dec 31 2002 - 12:04:04 PST)
- Review 6.3 onwards Jayaram Bhasker (Fri Jan 03 2003 - 12:24:57 PST)
- RE: More Draft 5.0.0 Comments (Clause 7) Jayaram Bhasker (Fri Jan 03 2003 - 13:06:35 PST)
- [siwg] Comments on sec 7 Jayaram Bhasker (Tue Jan 14 2003 - 06:18:20 PST)
- [siwg] RE: Review of Clause 8 and Annex A Jayaram Bhasker (Tue Jan 14 2003 - 10:51:44 PST)
- [siwg] Re:Review Draft 1076.6 D5.00 is Posted Vinaya Singh (Tue Jan 14 2003 - 22:51:31 PST)
- [siwg] More feedback on draft : ch 8 and beyond Jayaram Bhasker (Wed Jan 15 2003 - 13:06:56 PST)
- [siwg] <grammar> Review 5.1. Note 1, page 19 - Jim Lewis (Fri Jan 24 2003 - 07:51:31 PST)
- [Fwd: Re: [siwg] p1076.6 Draft 5.1 is Posted] Jim Lewis (Fri Jan 24 2003 - 10:31:11 PST)
- [siwg] async_condition + more on sync_condition Jim Lewis (Fri Jan 24 2003 - 12:09:20 PST)
- [siwg] Re: .... Sync_Condition rewording Jim Lewis (Thu Jan 30 2003 - 02:09:51 PST)
- [siwg] Register boundry conditions Jim Lewis (Fri Jan 31 2003 - 12:53:56 PST)
- [siwg] Final draft 1076.6 Jayaram Bhasker (Fri Feb 07 2003 - 12:27:56 PST)
- [siwg] FW: Invitation to Shape VHDL 1076-200x Jayaram Bhasker (Mon Feb 24 2003 - 05:05:24 PST)
- [siwg] Please Review Draft. IEEE process has been initiated. Jim Lewis (Mon Mar 03 2003 - 12:06:21 PST)
- [siwg] Additional Example for section 6.1.3.3 Jim Lewis (Wed Mar 05 2003 - 11:48:36 PST)
- [siwg] Call for Contributions FDL 2003 David Bishop (Thu Mar 13 2003 - 14:55:49 PST)
- [siwg] FDL'03 David Bishop (Tue Mar 18 2003 - 11:45:38 PST)
- [siwg] 1076.6 D6.0 is Posted John Michael Williams (Fri Apr 18 2003 - 18:53:33 PDT)
- [siwg] Section 6.1.3.3 Jim Lewis (Mon Apr 21 2003 - 12:49:25 PDT)
- [siwg] Re: Dual-edge triggered FF, 1076.6 RTL style Jim Lewis (Wed Apr 23 2003 - 12:56:54 PDT)
- [siwg] Re: Dual-edge triggered FF, 1076.6 RTL style Jim Lewis (Wed Apr 23 2003 - 13:45:42 PDT)
- [siwg] Invitation to Ballot for P1076.6/D6 Revision Jim Lewis (Thu May 29 2003 - 09:46:19 PDT)
- [siwg] DVCon 2004 Call For Papers Jayaram Bhasker (Tue Jul 01 2003 - 07:57:03 PDT)
- [siwg] 1076.6 (VHDL Synthesis) Rev passes IEEE ballot Jayaram Bhasker (Tue Aug 19 2003 - 11:24:47 PDT)
- [siwg] FW: DASC: draft procedures on web site Jayaram Bhasker (Fri Nov 07 2003 - 08:19:09 PST)
- [siwg] Re: [siwg-pilot] Ballot resolution PA61 Jim Lewis (Tue Nov 18 2003 - 13:50:50 PST)
- [siwg] Re: Read variable before WRITE Jim Lewis (Tue Dec 16 2003 - 22:03:09 PST)
- [siwg] Re: [vhdl-200x] re: Read variable before WRITE Jim Lewis (Thu Dec 18 2003 - 07:40:24 PST)
- [siwg] Fwd: [vhdl-200x] re: Read variable before WRITE VhdlCohen@aol.com (Thu Dec 18 2003 - 08:11:49 PST)
- [siwg] Fwd: [vhdl-200x] re: Read variable before WRITE Rich W Hatcher (Thu Dec 18 2003 - 10:16:36 PST)
- [siwg] Resolved Draft D7 Posted for Review John Michael Williams (Wed Jan 28 2004 - 20:17:47 PST)
- [siwg] [Fwd: Last Call for Papers - EDP 2004 - Design Process Workshop] David Bishop (Fri Feb 13 2004 - 18:00:17 PST)
- [siwg] Testing - please ignore Jayaram Bhasker (Mon Mar 08 2004 - 12:37:59 PST)
- [siwg] [Fwd: P1076.6 passed ballot] David Bishop (Sun Mar 14 2004 - 15:59:46 PST)
- [siwg] FW: P1076.6 passed ballot Jayaram Bhasker (Mon Mar 15 2004 - 06:29:19 PST)
- [siwg] FW: P1076.6 Approval Notification David Bishop (Tue May 18 2004 - 06:12:11 PDT)
- [siwg] IEEE1076.6-2004 Revision standard is official! Jayaram Bhasker (Tue May 18 2004 - 07:07:05 PDT)
- [siwg] IEEE Std 1076.6-2004: If you need a copy of the standard, then . . . Jayaram Bhasker (Tue May 18 2004 - 11:29:53 PDT)
- [siwg] 1076.6 made it to the press . . . Jayaram Bhasker (Wed May 19 2004 - 10:08:38 PDT)
- [siwg] 1076.6 is an ANSI standard too! Jayaram Bhasker (Wed Sep 01 2004 - 10:30:46 PDT)
- [siwg] IEEE 1076.6 Matarazzo, Robert \(US SSA\) (Mon Feb 28 2005 - 08:21:17 PST)
- [siwg] multidimensional array in IEEE Std 1076.6-2004 yannick.grugni_at_..... (Thu Mar 10 2005 - 05:33:45 PST)
- [siwg] FW: IEEE Std 1076.6-2004 and IEEE Std 1364.1-2002 Jayaram Bhasker (Wed Apr 06 2005 - 08:25:44 PDT)
- [siwg] Industry adoption of RTL_SYNTHESIS OFF/ON Farrell Ostler (Fri Aug 19 2005 - 09:52:19 PDT)
- [siwg] Process Synthesis plotfi_at_..... (Sat May 06 2006 - 02:14:01 PDT)
- Last message date: Sat May 06 2006 - 03:20:09 PDT
- Archived on: Sat May 06 2006 - 03:20:34 PDT