2nd ANNUAL RASSP CONFERENCE PAPERS
- Advanced Technology Laboratories’ Path to 4X Improvements
- Approximate Processing and Incremental Refinement Concepts
- Architectures for a RASSP Signal Processor
- Autocoding in the Lockheed Martin ATL/Camden RASSP Hardware/Software Codesign
- Automated Generation of Accurate VLSI Behavioral Processor Models for Simulation and Synthesis
- Collaborative VHDL Modeling within the RASSP Program Demonstration Project
- Creating a "Plug and Play" Architecture to Support Hierarchical Virtual Enterprise Design Process Management
- Developing Re-useable Performance Models for Rapid Evaluation of Computer Architectures Running DSP Algorithms
- Environment and Tools for an Integrated RDE (ENTIRE)
- Evaluating Distributed Multiprocessor Designs
- A Framework for the Development of Hybrid Models
- Hardware/Software Codesign in the Lockheed Martin Advanced Technology Laboratories’ RASSP Program
- Implementation of the RASSP SAR Benchmark on the Intel Paragon
- Integration of DFT into RASSP
- Integrated Process Control and Data Management in RASSP Enterprise
- Integrated Reliability and Performance Evaluation using Information Flow Models
- KINDLING: A RASSP Application Case Study
- Lockheed Martin Advanced Technology Laboratories RASSP Second Year Overview
- Managing the RASSP Virtual Enterprise
- Projecting RASSP Benefits
- Rapid Design and Exploration of Signal Processing System Using a VHDL Model Generator Based Paradigm
- Rapid Prototyping of Application-Specific Signal Processors: Educator/Facilitator Current Practice (1993) Model and Challenges
- Rapid Prototyping Applied to Underwater Acoustic Modem Research & Development
- RASSP Benchmark 1: Virtual Prototyping of a Synthetic Aperture Radar Processor
- RASSP Benchmark-1 and -2: A Preliminary Assessment*
- RASSP Process Management
- RASSP Program Overview
- RASSP: The Road to 4X
- RASSP Technology Insertion into the Synthetic Aperture Radar Image Processor Application
- RASSP VHDL Modeling Terminology and Taxonomy
- Real Time IRST Development Using RASSP Methodology and Process
- Reuse-Oriented Model Year Architectures for Rapid Prototyping
- Support for Model-Year Upgrades in VHDL Test Benches
- TRW RASSP Model Year 1 Spread Spectrum Processor
- VHDL to Hardware: A TIREP Success Story
- VHDL Modeling, Test and Distribution
- VHDL-Based Performance Modeling and Virtual Prototyping
- Workflow Modeling for Implementing complex, CAD-Based, Design Methodologies
Advanced Technology Laboratories' Path to 4X Improvements
Jeff Pridmore
Abstract
To provide 4X improvements in time-to-market, life-cycle cost, and design
quality, Lockheed Martin's Advanced Technology Laboratories is uniquely
combining the three elements of the RASSP technology triad -- Methodology,
Model Year Architecture, and Infrastructure/Design Environment -- into an
integrated, rapid prototyping environment.
Approximate Processing and Incremental Refinement Concepts
J. Winograd , J. Ludwig, H. Nawab , A. Chandrakasan and
A. Oppenheim
Abstract
Approximate processing and incremental refinement concepts are
needed for applications where it is desirable to provide a
systematic tradeoff between the quality of signal processing
results and the availability of resources, such as time, bandwidth,
memory, and power. We examine the impact of these concepts for three
distinct application areas: (1) low-power frequency-selective FIR filtering, (2) real-time time frequency
analysis of signals and (3) DCT-based image encoding/decoding. Results from approximate processing of signal data
illustrate the practical utility of these types of systems.
Architectures for a RASSP Signal Processor
Fred Shirley, Bob Bassett andJ. P. Letellier
Abstract
This paper summarizes the various elements of a RASSP
architecture and describes the architecture selection process
that is used to identify a particular architecture for a
given system problem. RASSP architectural approaches
address general attributes of the signal processor under
development, including the communications methods and
the type of processing elements used. Architectures of
interest span multiple system application areas and lend
themselves to periodic model-year upgrades in concert
with the RASSP development methodology. Experiences
from our Demonstration and Benchmark teams are used
to illustrate the alternative results that can arise from different
problem constraints. In the case of the Demonstration,
the architectural solution consisted of custom
interface cards on an industry standard bus using commercially
available processors. In the case of the Benchmark
the solution consisted of a custom interface and a
custom processing card connected through an industry
standard bus. Differences in space and power constraints
in the two problems account for the two different solutions.
Autocoding in the Lockheed Martin ATL/Camden RASSP Hardware/Software Codesign
Christopher B. Robbins
Abstract
Autocoding provides the Lockheed
Martin Advanced Technology Laboratories Camden
(LM-ATL Camden) RASSP hardware/software
wdesign process the means to rapidly realize
implementations of the wdesign software
architectures. Management Communications and
Control, Inc. (MCCI) autocoding tools automate
translation of software architecture specifications to
designs and their implementations for functional and
detailed hardware/software wsimulation, unit
testable modules, and wmplete application load
image specifications. The tools support an open
application programmers interface to the codesign
process. Autocoding tools support the wdesign
processes objective of providing a seamless
translation of applications from math tool level
functional algorithm specifications to target
architecture load images. Autocoding technology is
directed at reducing the labor content of software
design and coding, enabling rapid development of
the software elements of application specific signal
processing systems.
Automated Generation of Accurate VLSI Behavioral Processor Models for Simulation and Synthesis
Yong-kyu Jung, Vijay K. Madisetti and John W. Hines
Abstract
A new process for automating the creation of Full- Behavioral (FBM)
and Instruction Set Architecture (ISA) models in VHDL for complex
processors and components is described, with results from the automation
of a PowerPC 601 described in some detail. A number of advantages to this
approach are described together with its impact on the hardware/software
codesign and system prototyping processes.
Collaborative VHDL Modeling within the RASSP Program Demonstration Project
Ray Dreiling and Paul Kalutkiewicz
Abstract
This paper describes experiences and lessons learned in executing
a top down VHDL based design with a distributed multi-company
team. The Sanders RASSP Demonstration team used a virtual
company concept for developing a VHDL description of an IRST
(Infrared Search and Track) processor This work spanned three
companies across the county and involved all aspects of the
project, i.e. design, analysis, fabrication, and test. This paper
describes the communications and coordination methods used
across the virtual company including the processes to support a
distributed design database, source code coherence across
multiple networks, and secure communications. The result of these
efforts were that the team was able to complete all its modeling
and designs without a single collocated design review and with
successful completion of all the hardware development.
Creating a "Plug and Play" Architecture to Support Hierarchical Virtual Enterprise Design Process Management
Scott Majdecki and John Purchase
Abstract
Supporting a "Plug & Play" architecture that allows the users choice of tools in the
Workflow Manager area is as important as in the individual tool areas. However, like
integrating EDA tools, designing an environment that would allow multiple workflow
management applications interoperate poses some challenge. This paper will discuss an
architecture that will allow a hierarchical design process to be successfully managed by
multiple workflow manager applications in a Virtual Enterprise Environment. It will use the
Module Design workflow as an example to illustrate an implementation of this architecture.
Developing Re-useable Performance Models for Rapid Evaluation of Computer Architectures Running DSP Algorithms
Hormazd P. Commkkat, Dr. F. Gail Gray, Dr. James R Armstrong and Dr. Geoffrey A Frank
Abstract
This paper discusses the issues in
the construction and use of multiprocessor
performance models based on an externally
developed library of component descriptions.
The component models used were initially
developed by another RASP contractor
(Honeywell), but they were upgraded modified
and customized to suit our needs. We compare
the simulation times for the VHDL models of the
three different architectures, all running a
variation of the synthetic aperture radar
benchmark provided by MT Lincoln Labs. The
three architectures studied are: 1) a common
global bus, 2) a two level bus hierarchy with
multiple local busses and a single global bus,
and 3) a system of local busses connected via a
crossbar interconnection. Variations in key
performance characteristics of the systems that
are used for tradeoff decisions including
component utilization, algorithm latency, and
algorithm throughput for the three architectures
running the same algorithm are recorded.
Environment and Tools for an Integrated RDE (ENTIRE)
Rick Ong, Rob Costantino and Rodger Philips
Abstract
This paper describes the features of Release 1.0 of the
RASSP Design Environment (RDE). This release is the
fourth internal build of the RDE. The RDE development
effort utilized previously developed RDE utilities in
conjunction with the RASSP process of software
development. This release of the RDE contains a common
set of core services for use in a wide range of
applications: common desktop, automatic metrics
collection, metrics analysis, reuse utility, technical review
utility, problem reporting utility, log utility, and remote
data access. The RDE is being tailored for use on our
Model Year I demonstration to include domain specific
tools, translators, libraries, and process support. A
preliminary list of applications for the Demonstration are
given in the paper. The fully populated and tailored
design environment is described as the ENTlRE concept
(ENvironment and Tools for an Integrated RDE).
Evaluating Distributed Multiprocessor Designs
Todd Steeves, Fred Rose, Todd Carpenter, John Shackleton and Otto von der Hoff
Abstract
Successful multiprocessor system design for complex real-time embedded
applications requires powerful and comprehensive, yet cost-effective,
productive, and maintainable modeling. The multi-disciplinary, VHDL-based
modeling library developed by the Honeywell Technology Center, and
enhanced for the RASSP community, places heavy emphasis on multiprocessing
and distributed communications. These models focus on detailed hardware
performance analysis along with multiple abstraction levels for software
representation and evaluation.
A Framework for the Development of Hybrid Models
Moshe Meyassed, Robert McGraw, James Aylor, Robert Klenke, Ronald Williams,
Fred Rose and John Shackleton
Abstract
Rapid prototyping of complex digital systems requires a well defined design
flow. A typical top-down design flow starts with a construction of a performance
model of the system under design, which helps in making architectural design
decisions. Unless this model is used for later phases of the design process, a
model continuity problem exists. This problem results from having to model and
simulate systems using different design environments for different levels of
design detail. Most of the levels of the design process do not exhibit the model
continuity problem. However, this problem is prevalent between the performance
and functional modeling levels. The work presented here allows for the true
step-wise refinement of a performance (uninterpreted) model into a functional
or behavioral (interpreted) model. The critical hurdle to the realization of
this methodology is the ability to do hybrid modeling. Hybrid modeling is the
capability of mixing high-level performance constructs and functional components
in a common analysis environment. Hybrid modeling supports the model refinement
design flow by providing an interface to bridge the information gap between performance
models and behavioral implementations.
Hardware/Software Codesign in the Lockheed Martin Advanced Technology Laboratories RASSP Program
W. Bernard Schaming and Arnold D. Bard
Abstract
A major goal of the RASSP program is to change the way signal processors
are designed. One of the key elements in changing the design process is
establishing a methodology and an implementation of that methodology that
embraces the notion of hardware/software (HW/SW) codesign. The objective
of this paper is to define HW/SW codesign and describe the overall
codesign process as they are implemented in Lockheed Martin Advanced
Technology Laboratories' RASSP program.
Implementation of the RASSP SAR Benchmark on the Intel Paragon
Curtis P. Brown,Richard A. Games and John J. Vaccaro
Abstract
A software design process for mapping real-time applications onto massively
parallel processors is described. The design methodology incorporates a software
test bench used to evaluate the level of real-time performance the processing nodes
are capable of delivering. The final integration step maintains the simple test
bench interfaces and reduces the complexity of integrating the components to satisfy
the timing requirements of the overall application. The process is applied to
implement the RASSP SAR benchmark on an Intel Paragon. The initial implementation
uses 12 Paragon GP nodes for a single polarization. Under OSF/1 this 12 node
configuration satisfies all the real-time requirements. Under SUNMOS, a streamlined
high performance operating system available on the Paragon, the throughput improves
significantly with sustained processor utilization approaching 40%. A projected
implementation of the RASSP SAR benchmark on the Embedded Touchstone suggests that
all three polarizations can be processed (including I/O) using 14 out of its 16 MP nodes.
Integration of DFT into RASSP
John Evans, Richard M. Sedmak and Patrick McHugh
Abstract
This paper describes the integration of Design-For-Testability (DFT)
processes, tools, and methodologies into the RASSP System, which consists
of the Design Environment and Enterprise System. The blueprint for the DFT
developments is the DFT Methodology, which is highly automated, hierarchical,
and spans the entire life cycle, contributing significantly to the RASSP
goals of 4x improvement in cycle time, design quality, and life cycle costs.
Key concepts of the DFT methodology are covered. A preferred testability
architecture that encompasses embedded test resources (BIST), external
test resources (ATE), and testbenches for design verification is described.
Integration of the DFT methodology and testability architecture into the
RASSP system is covered. The paper concludes with a discussion of the
contribution of DFT to meeting the RASSP goals.
Integrated Process Control and Data Management in RASSP Enterprise Systems
John Welsh, Biju Kalathil, Bipin Chadha, Mary Catherine Tuck, William Selvidge,
Elisa Finnie and Arne Bard
Abstract
The RASSP Enterprise System provides key automation support for teams of
signal processing/electrical design engineers in the execution of complex
development projects. As a result, the system facilitates greatly improved
productivity, as well as efficient program control and orderly management
of design configurations. Core concepts of the RASSP Enterprise System
include integration of tools and tool frameworks into an enterprise
environment; program execution control through workflows; integrated data
management functions; concurrent engineering team support; and integration
of design engineering and manufacturing. This paper presents a strategy
for the use of the RASSP environment, methodology/workflows, and information
models to improve efficiency in task execution and information management
on signal processor development projects.
Integrated Reliability and Performance Evaluation using Information Flow Models
Ramesh Rao, Barry W. Johnson, Ronald D. Williams and James H. Aylor
Abstract
Information flow models provide a natural and convenient representation of the structure,
function, and data/control flow of digital electronic systems at a high level of
abstraction and interpretation. Design engineers prefer to use such models for
performance trade-offs and analysis. Adding the capability to model and analyze the
dependability characteristics of a system within such a paradigm allows design engineers,
as opposed to reliability engineers, to perform dependability analysis and trade-offs at
the early stages of the design process. A design environment supporting such a philosophy
would bring dependability analysis and trade-offs into the mainstream of the design process.
The Advanced Design Environment Prototype Tool (ADEPT) is based on such a philosophy. This
paper presents an overview of ADEPT with a focus on the dependability modeling paradigm. The
various solution paths for the evaluation of dependability metrics are presented. The paper
will demonstrate the capabilities of ADEPT by modeling the controller for a jet engine magnetic
bearing.
KINDLING: A RASSP Application Case Study
Robert H. Paulson
Abstract
The KINDLING case study is applying RASSP
processes to develop algorithmic and performance
models of an existing subsystem in order
to explore architectural options for in-creased
performance and functionality. This
subsystem is common to several projects in the
Lockheed-Martin Information Processing
Systems (IPS) business area. Its current implementation
consists of a VME board with either
5 or 24 DSP32C processors and classified soft-ware
which runs on these processors.
This paper will describe the accomplishments
to date and plans for the remainder of the project.
Requirements and initial high level design
have been captured with RDD-100; a functional
model of the signal processing algorithms is
currently being created using SPW (Signal Processing
Work System) and GEDAE (Graphical
Entry Distributed Application Environment);
and performance models in VHDL for the entire
subsystem will be created. Architectural
variations to be considered in the case study include
processing a signal with one versus multiple
DSPs and varying the DSP processor:
SHARC, TMS320C40, Mercury architecture
with i86Os or SHARCs, and DSP32C are options.
Delay parameters for software blocks in
the performance models will be determined us-ing
actual processors, development tools, or
ISA models for each processor option. Metrics
from performance models will be compared
against performance metrics from previous implementations.
An additional goal is to investigate
automated code generation, loading, and
benchmarking in target systems using GEDAE.
GEDAE already supports Mercury Raceway
bus systems with i860processors, and soon will
be ported to C40 SPOX systems. Process metrics
will be recorded during KINDLING and
compared with process metrics from the current
implementations. The study will also evaluate
the applicability of RASSP tools to this
task, especially in a classified environment;
make recommendations; and suggest improvements.
Lockheed Martin Advanced Technology Laboratories RASSP Second Year Overview
James E. Saultz
Abstract
The goal of the Prototyping of Application-Specific Signal Processors (RASSP)
program is to improve by at least a factor of four the cost and time needed
to develop and manufacture signal processors. The approach to reaching the
program's goalis based on three technology thrusts; methodology, Model Year
Architecture, and infrastructure (Enterprise). Using this triad of technology
thrusts, Lockheed Martin Advanced Technology Laboratories' (ATL) RASSP team
composed of an alliance of companies has implemented the first baseline
RASSP system, which represents a significant advance over today's state-of-the-art.
The methodology and tools have been used to demonstrate cost and design cycle
improvements on the benchmark virtual prototype (VP) and have resulted in the
development of a hardware/software system that demonstrated first-pass success.
Additional developments being performed during the last two years of the program
will provide further benefits, enabling demonstration of 4X improvements in cost
and time to market. This paper provides an overview/update of the progress since
the 1994 Annual Review.
Managing the RASSP Virtual Enterprise
Bruce Bullock, Ken Streeter, George Muncaster,
Mark Hoffman and Mike McCollough
Abstract
The Lockheed-Sanders RASSP development team is
composed of four companies: Sanders, Motorola,
Hughes, and ISX. These four geographically disparate
companies work together daily across all facets of the
RASSP program including: Program Management; System
Engineering; RASSP Design Environment (RDE)
Development; Process Development; Demonstration
Work; Benchmark Efforts; and product and process Proliferation.
Each major program element involves collaboration
by all team members. The associated work
products are the result of highly integrated activities.
How is this successfully accomplished?
continuing RDE development. This paper details the
methodologies, tools, and standards that enable the Virtual
Corporation to operate successfully and illustrates their
use and benefits to its members.
An area not addressed in this paper but recognized by
the RASSP team as a key issue in the instantiation of a
virtual enterprise are the limits, controls, and restrictions
involved in:
This paper describes a set of tools, methodologies, and
standards developed and utilized by the team to enable the
establishment and operation of the RASSP virtual corporation.
Projecting RASSP Benefits
James C. Anderson
Abstract
Benefits of a RASSP-based design approach have been identified
as a result of benchmarks defined and evaluated by MIT Lincoln
Laboratory. One benchmark task, development of a synthetic aperture
radar signal processor, serves to illustrate the effects of design
trade-offs and tool usage on acquisition cost, development time and
life cycle cost. Parametric cost estimation tools are used to predict
the benefits of a RASSP-based design approach relative to standard
practice, and one example demonstrates a factor of four cost reduction.
Rapid Design and Exploration of Signal Processing System Using a VHDL Model Generator Based Paradigm
Scott R. Powell and Thomas M. Cesear
Abstract
An upgradable design methodology is described for the rapid design
and implementation of ASIC-based embedded DSP systems; with results
from a detailed design example. The design methodology is based around
a library of VHDL model generators which create application-specific
simulatable and synthesizable VHDL models of DSP algorithms. The VHDL
model generators are extensively parameterized to encapsulate microarchitectural
design expertise and elevate it to higher level design activities where
there is a greater amount of leverage. Generators provide a cost-effective
means to explore the area, speed, and power tradeoffs of algorithmic,
architectural, and microarchitectural design alternatives at very early
stages in the design process. An expanding library of application-specific,
parameterized VHDL model generators is described which is oriented toward
common signal processing functions. The library is hierarchical with model
complexity ranging from single arithmetic operators to large core functions
to entire VLSI chips. The VHDL generator library has been used to design
several DSP ASICs; a specific design example is presented demonstrating a
3 to 5 times reduction in overall design time from system specification to
mask-level layout.
Rapid Prototyping of Application-Specific Signal Processors: Educator/Facilitator Current Practice (1993) Model and Challenges
Vijay K. Madisetti, Jack Corley and Gary A. Shaw
Abstract
The Rapid Prototyping of Application-Specific Signal Processors (RASSP)
project of the US Department of Defense (ARPA and Tri-Services) targets
a 4X improvement in the design, prototyping, manufacturing, and support
processes (relative to current practice). The authors present a current
practice (circa 1993)" model for the design and prototyping of
application-specific signal processors developed as part of the RASSP
Educator/Facilitator (E&F) Program. A number of limitations in current
design practice are highlighted together with challenges faced by
candidate solutions. The E&F Program proposes that this model be used
as a baseline in the evaluation of newer RASSP prototyping methodologies
and processes.
Rapid Prototyping Applied to Underwater Acoustic Modem Research & Development
Paul D. Fiore, Eric Will, Geoffrey Edelson and David Herold
Abstract
Rapid prototyping is well suited to address the signal processing
design tasks encountered in research applications.
The applications differ from defense or industrial applications
in that the signal processing requirements are either
evolving or poorly understood. In the field of underwater
acoustic (I/WA) communications, practical solutions, and
thus their implementations, are still maturing. Sanders
and WHOI are using the development of an improved
UWA modem to exercise the processes and environments
being developed at Sanders under the RASSP program.
This paper represents an update to our work previously
published. In this paper we provide an overview of
the signal processing requirements for UWA communications.
We outline the impact of these requirements on system
design and describe the application of RASSP
processes to system architecture specification. Finally,
several potential paths for future development are
described, both for system upgrades and for new applications.
key aspects of the RASSP process will be evaluated upon
completion of this project.
RASSP Benchmark 1: Virtual Prototyping of a Synthetic Aperture Radar Processor
Eric A. Rundquist, Jr.
Abstract
A virtual prototype of a synthetic aperture radar
processor is being created by Lockheed Sanders. It
includes VHDL models and Ada application code. The
virtual prototype is a behavioral and structural model
which matches the hardware architecture which was
selected as part of this effort. As part of the RASSP
program, we are answering the question: "How can one
use VHDL /Ada to validate hardware / software tradeoffs
and reduce the life cycle cost of digital systems? "
The current status is that the virtual prototype has
been completed and we are developing a hardware
prototype which will validate the virtual prototype.
RASSP Benchmark-1 and -2: A Preliminary Assessment*
A. H. Anderson, G. S. Downs, G. A. Shaw
Abstract
These two benchmarks required the development of a virtual prototype and
a hardware prototype, respectively, of a Synthetic Aperture Radar processor.
The two RASSP Developers chose different approaches: one used COTS components
on custom boards with a methodology emphasis on detailed VHDL prototyping and
board design and one used COTS computer boards with a methodology emphasis on
efficient VHDL modeling and automatic code generation. Both efforts are briefly
described. A preliminary assessment of Benchmark-1, which has been completed,
is offered with emphasis on the experience with VHDL modeling. Based on this
assessment, some recommendations for improvement are made.
RASSP Process Management
J. Malley, R. Bassett, M. Falco, G. Bruggemann, G. Muncaster
Abstract
IEEE P-1220 as a basis, and is documented in IDEFO format for
dissemination to applications both internal and at Beta sites. As
the Sanders’ RASSP Team has developed, evaluated and
experimented with the process, descriptors use text, hypertext, and
graphics. The success of the process evolution has been
demonstrated in its successful application. This paper discusses
the Sanders’ Team’s process evolution, optimization. and
application during the first two years of the program.
RASSP Program Overview
W. Hood, M. Hoffman, J. Malley, C. Myers, R. Ong,
E. Rundquist, L. Scanlan,F. Shirley, D. Uyemura
Abstract
This Sanders-led team of Motorola, Hughes and ISX has
met all of the primary RASSP program objectives during
the first two years of the program. This paper reviews the
goals of the program, and the unique ways in which our
team is meeting them. The flexible methodology and
design environment are described along with the progress
made in creating a standard enterprise framework. The
progress of the demonstration and benchmarking effort is
detailed, as is the work towards proliferation of the
RASSP process. The emphasis on VHDL and Ada-based
virtual prototyping and its impact on Model Year
Upgrades is discussed. The creation of the Virtual RASSP
Corporation and the special Internet communication protocols
developed to support the program are reviewed.
Accomplishments in each of the program areas are
reviewed along with specific goals for the next year of the
program. Particular emphasis is placed on our Model
Year 0 demonstration in which we designed, fabricated,
and tested Infrared Search and Track (IRST) flight hard-ware
in less than a year. Comparison of the time and
resources required to perform Model Year 0 with a comparable
non-RASSP development demonstrates that we
have already achieved a factor of more than 2.2 X
improvement in development time and development cost.
RASSP: The Road to 4X
Larry Scanlan, Ph.D. and LeRoy Fisher
Abstract
The RASSP Program has ambitious goals: 4X decrease
in product development cycle-time, 4X decrease in life-cycle
costs and 4X increase in product quality. Reaching
these goals requires a map so we can choose the route that
leads to the desired destination while avoiding financial
mountains too high to climb or technology gaps too wide
to jump. With the map we can expend all of our energy
navigating the routes that will accelerate our progress.
In the sections that follow, the factors that contribute to
cycle-time and quality will be identified along with the
barriers to change. Next we describe some of the
approaches being taken by the Lockheed Sanders RASSP
team to take advantage of the enabling factors. We will
then summarize the results of a product development task
analysis to show how each RASSP process reduces cycle-time
and improves quality. Finally, we will assess the
progress of the IRST Signal Processor Demonstration
Team towards achieving 4X.
RASSP Technology Insertion into the Synthetic Aperture Radar Image Processor Application
Junius Pridgen, Richard Jaffe, William Kline
Abstract
This paper describes the development on RASSP Benchmark 1 and 2 of the
synthetic aperture radar (SAR) image processor using the RASSP design
environment. The overall process flow developed by Lockheed Martin's
Advanced Technology Laboratories, as applied on the SAR processor, is
illustrated. Results from using executable specifications; parametric
cost estimating tools and VHDL-based performance modeling for architecture
tradeoffs; hardware/software codesign; virtual prototyping for architecture
verification; software generated by autocode; and VHDL-based, top-down
hardware development are shown. This paper discusses the implementation
strategy and lessons learned on the RASSP benchmark activities.
RASSP VHDL Modeling Terminology and Taxonomy
Carl Hein, Todd Carpenter, Paul Kalutkiewicz, Vijay Madisetti
Abstract
VHDL modeling taxonomy and terminology conventions are emerging from the on-going
efforts of the Terminology Working Group (TWG). Based upon examination and comparison
of previously published modeling taxonomies, the working group is evolving a multi-axis
taxonomy designed to describe the information content of RASSP model types and
abstraction levels and to facilitate selection and construction of interoperable
models. The TWG used the taxonomy to concisely refine modeling terms applying to
system, hardware, and software models; abstraction levels; structural hierarchies;
and modeling paradigms. The refined definitions for several of the modeling terms
especially important in RASSP are listed and discussed.
Version 1.0 was presented at the conference. This document has been revised and the most current version is provided. This document may be accessed
at anytime from the "Side or Bottom" VHDL Taxonomy button.
Real Time IRST Development Using RASSP Methodology and Process
Michael Vahey , Decker Bushman, Steve Dabell, Ted Ennis, Paul Kalutkiewicz, Win0 Lee,
Mike McCollough, Brian Nelson, Kathryn Russell, David Uyemura, and Howard Wanke
Abstract
The development of a real-time infrared search and
track (IRST) processing system served as a real-world
application of the on-going development of methodologies
and processes intended to achieve a four time improvement
of cycle time at the end of the four year program.
This development is an integral part of the Rapid Prototyping
of Application Specific Signal Processors (RASSP)
program. Real world applications are used to validate and
provide metrics on the effectivity of the methodology and
processes. A key part of the development methodology is
virtual prototyping, a VHDL technique for validating a
hardware and software design before hardware is developed.
This paper describes the RASSP virtual prototype
and overall results achieved by the demonstration team.
Reuse-Oriented Model Year Architectures for Rapid Prototyping
G. Caracciolo and J. Pridmore
Abstract
The Rapid Prototyping of Application-Specific Signal Processors (RASSP)
program is striving to change the way embedded signal processor design
is performed, providing >4X improvements in time-to-market, cost, and
design quality. These improvements will be achieved using a methodology
that stresses hardware and software reuse in conjunction with Model Year
Architectures that facilitate reusability and upgradability through open
interface standards. This paper will describe a Model Year Architecture
approach for the development of cost-effective signal processors can be
applied to a wide range of military and commercial applications.
Support for Model-Year Upgrades in VHDL Test Benches
Geoffrey A. Frank, James R. Armstrong, Gail Gray
Abstract
The RASSP model-year concept requires a
design system that supports evolving
system requirements such as changes in
sensors, system platforms, targets, and
clutter characteristics. Virtual prototyping
with VHDL is seen as an essential part of
rapid system design in an environment of
changing system requirements. Test bench
development is often 50% or more of the
effort of building a virtual prototype, so
effective and efficient means of upgrading
test benches is essential to achieving the
RASSP goal of a factor of 4 reduction in
design costs and time to market.
This paper describes two techniques that
the Virginia Tech/Research Triangle
Institute team is using to support rapid and
correct modification of high level VHDL
test benches for virtual prototypes. First,
the team has been creating VHDL test
benches by converting test benches in other
tools into VHDL. Second, the team has
been developing automated links between
requirements databases, test bench
component libraries, and VHDL test
benches.
TRW RASSP Model Year 1 Spread Spectrum Processor
Carolyn Kuttner
Abstract
TRW is using the Martin RASSP system to
develop a Spread Spectrum Preprocessor (SSPP)
targeted for the requirements of the Integrated Sensor
System (ISS) and Joint Advanced Strike Technology
(JAST) programs. Spread Spectrum processing is used
to improve communication in noise and jamming and
is a key part of many communication links, including
JTIDS (Joint Tactical Data Information Distribution
System). EPLRS (Enhanced Position Location
Reporting System) , and WNA (Wideband Network
Access). Spread Spectrum processing is done early in
the signal processing flow and so requires a very high
computational bandwidth -- 2-channel JTIDS needs 5
BOPS and four-channel EPLRS requires 50 BOPS.
The overall programmatic goals of ISS and JAST are
in line with RASSP’s new capabilities -- including
reducing life cycle costs with simulation and affordable
upgrades to open systems. The specific SSPP
requirements are also in line with RASSP,
emphasizing physical and logical scalability and
flexibility. This paper describes the RASSP process
being used status, and lessons learned to date.
VHDL to Hardware: A TIREP Success Story
Ed Woods, Darin York, Gary Hout, John Miles, L.J.Ceder,
Charles Rogers, David Broadhead, Louie Kitcoff, Lindsay Skidmore
Abstract
Electronics obsolescence in military systems is one of the most expensive
and elusive challenges facing the Department of Defense today. This one
issue is costing millions of dollars a year in re-engineering, special
orders, volume buys and redesign costs. Development of new techniques,
tools and processes for maintenance of legacy systems and integration of
new technology in an era of life cycle extension and funding reduction
is essential. The Technology Independent Representation of Electronic
Products (TIREP) project was funded by the Standard Hardware Acquisition
and Reliability Program (SHARP) and the Flexible Computer Integrated
Manufacturing (FCIM) program offices to address these repair, reliability,
and obsolescence issues in the maintenance of legacy systems. TIREP is
a joint effort between the Naval Research Lab (NRL), Washington DC,
the Naval Air Warfare Center - Aircraft Division Indianapolis (NAWC-ADI),
and the Naval Surface Warfare Center (NSWC) - Crane Division. TIREP
has developed a seamless process to cost effectively recreate a form,
fit, and function replacement of electronic circuit card assemblies from
a digital functional behavioral description such as the Very High Speed
Integrated Circuit(VHSIC) Hardware Description Language (VHDL) along
with other related standards.
VHDL Modeling, Test, and Distribution
Vincent L. Sanders, Robert B. Reese, Aubrey K. Knight, J. Scott Calhoun
Abstract
This paper presents the ongoing effort of the Mississippi State University / Microsystems
Prototyping Laboratory (MSU/MPL) executed as part of the RASSP Technology Base Program. The
research underway includes: VHDL model development, VHDL test bench synthesis, and utilization
of the World Wide Web (WWW) to document and distribute models, tools, and information.
To date, modeling guide lines have been implemented for PROMs, SRAMs, Dual–Port SRAMs,
FIFOs, and PLDs. Successful models have been developed using these guidelines. Guidelines
for CPLDs and FPGAs are currently being developed.
A VHDL Test Bench Synthesis Tool has been developed and is scheduled for beta
testing in July 1995. This tool automatically generates VHDL test benches and
allows for vendor independent testing methodologies of VHDL designs.
The World Wide Web (WWW) is being used to document and release the VHDL models
developed. Complete datasheets for sample models have been developed and posted
to the Web as an example of hierarchical electronic datasheets.
VHDL-Based Performance Modeling and Virtual Prototyping
Carl Hein and David Nasoff
Abstract
The need for top-down, hierarchical, simulation processes in RASSP has
pushed the use of VHDL at levels of abstraction above where it has
typically been used. Selection of an appropriate modeling abstraction
level permits rapid exploration of many alternative software and hardware
solutions while achieving accurate yet efficient simulation. Performance
and virtual prototype models facilitate the integrated design and
development of the software and the hardware subsystems in a hardware/
software codesign process. In this paper, the Lockheed Martin Advanced
Technology Laboratories (ATL) RASSP team will present methods for producing
an efficient VHDL-based performance model of a Digital Signal Processor
(DSP) system, which is then extended to form a comprehensive virtual
prototype of a full multi-processor DSP system that is both timing- and
data-faithful. The system models provide early design verification via
simulation of software, as partitioned, mapped, and executed on the
hardware architecture. This paper will focus on VHDL-specific issues and
techniques for this type of very abstract modeling.
Workflow Modeling for Implementing Complex, CAD-Based, Design Methodologies
J. Stavash, J. Wedgwood, M. Forte, W. Selvidge, M.C. Tuck,
A. Bard and E. Finnie
Abstract
A specific goal of the Rapid Prototyping of Application-Specific Signal
Processors (RASSP) program is to achieve a 4X improvement in design cycle
time, cost of the design, and the quality of the final product. In order to
achieve these 4X improvements, Lockheed Martin Advanced Technology
Laboratories (ATL) is developing design methodologies that make use of
concurrent engineering, design object reuse, and the spiral model of
development for rapid prototyping. Lockheed Martin ATL, Rockwell
International, Intergraph, and Aspect Development are collaborating on
developing workflow models to implement these design methodologies, as
well as the data management and CAD tool environment to support them.
|
