1st ANNUAL RASSP CONFERENCE PAPERS
Adapting Algorithms to Architectures Through TransformationsG.A. Frank, B.E. Clark, W.G. RansdellAbstractThe Research Triangle Institute (RTI) is developing a tool to assist the system architect in partitioning and mapping signal processor algorithms onto signal processor architectures that is based on the transformation process. The toll provides feedback to the architect about latency of algorithm nodes, utilization of hardware components and memory occupancy rates. RTI has been using Lincoln Laboratories' RASSP benchmark Synthetic Aperture Radar (SAR) algorithm as a driving problem to demonstrate that a small number of transformations can achieve an appropriate partitioning for a notional architecture. ADEPT: A Unified System Level Modeling Design EnvironmentSanjaya Kumar, Robert Klenke, James H. Aylor, Barry W. Johnson, Ronald D. Williams and Ronald WaxmanAbstractThis paper presents an evolving integrated design environment called ADEP (Advanced Design Environment Prototyping Tool). ADEPT supports both performance and reliability analysis in a common design environment using a collection of predefined library elements called ADEPT modules. These modules have a VHDL description as well as an underlying colored Petri Net representation associated with them. As a result both simulation-based and analytical approaches for analysis can be employed. Algorithms for Signal ProcessingAlan V. Oppenheim, S. Hamid Nawab, George C. Verghese and Gregory W. WornellAbstractDesign and prototyping of signal processors must inherently take into account the structure of signal processing algorithms. Many of the emerging classes of algorithms stem from new models and approaches, and current design tools and implementation structures are not necessarily well matched to these algorithms. In this paper we summarize our work on three classes of new algorithms with an eventual goal of exercising and challenging the RASSP tools and process, and hopefully providing specific input for a real or hypothetical next generation of design tools and process. Applications of Formal Model of VHDLDavid Benz, Xianzhi Fan, and Philip A. WilseyAbstractBesides a formal syntax definition, few formal semantic models for Hardware Description Languages (HDLs) are ever constructed. Furthermore, informal (English) specifications of "so called" standard languages allow for numerous interpretations where only one is desired. This paper reports our efforts to construct formal models for the hardware description language VHDL. In particular, a static model for VHDL is presented with a set of transforms that allows the rewriting of VHDL models into a reduced form. This reduced form simplifies (i) the construction of CAD tools and (ii) the construction of a formal dynamic semantics for defining correct simulation of VHDL. The dynamic semantics is under development and the reductions have greatly simplified the language constructs that the dynamic semantics have to characterize. Board and MCM Level Synthesis for Embedded Systems: The Comet Cosynthesis EnvironmentRanga Vemuri, Hal Carter and Perry AlexanderAbstractCOMET is a cosynthesis environmental for application-specific electronic signal processing modules. COMET is capable of automatically synthesizing multicomponent hardware-software systems at the board and MCM levels. CAD Tool Interoperability Through StandardsDonald R. Cottrell and John J. TeetsAbstract
With this project proposal CAD Framework Initiative, Inc. (CFI) is taking a bold, new approach to achieve CAD
interoperability by engaging a select team of the industry's leading user companies and tool vendors to develop a functional
CFI standards-based front-end design flow. The project will focus on interoperation of tools within the core of the design
cycle, where closer correlation of delay and timing results among multiple vendor tools and more rapid design iteration is
required. This core set of design tools (synthesis, delay, timing, floor-planning, associated analysis tools) is key to the
effective design of sub-micron technologies of today and tomorrow.
Design and Simulation of Heterogeneous Systems using PtolemyB. L. Evans, A. Kamas, and E. A. LeeAbstractThe ambitious objectives of the Ptolemy project include practically all aspects of designing signal processing systems, ranging from the design and simulation of algorithms to the generation of hardware and software, the parallelizing of algorithms, and the prototyping of realtime systems. To manage these abilities, it is essential that the design software be highly modular and extensible, so that the development of subprojects of manageable scope can proceed unencumbered and in parallel, while at the same time allowing subprojects to interact and to be combined into a complete working system description. Since subprojects must use the best available tools (which are often domain-specific), the tools must also be able to interact. The Ptolemy software architecture shows one way in which such interaction can be achieved, using object-oriented principles of polymorphism and information hiding. Estimating the Requirements of Signal Processing AlgorithmsBenjamin FriedlanderAbstractMAT2DSP is a MATLAB toolbox, currently under development, whose function is to estimate the implementation requirements of algorithms specified in the form of a MATLAB program. This toolbox is aimed at providing researchers developing advanced signal and image processing algorithms, a quick and convenient way of estimating what would be needed to implement their algorithm on a specified processor. This information can be used to do cost/performance trade-offs early in the design process, and to concentrate the research effort on the development of algorithms which are likely to meet the system constraints. While the current project focuses on MATLAB, the same approach can be used to develop similar tools for other mathematical software packages. The paper describes the components of the MAT2DSP program and provides some details on its current status. Image Signal Processor DemonstrationMichael VaheyAbstractTo test a RASSP design Environment, the Lockheed/Hughes/Motorola/ISX team is developing a 192-element infrared-search-and-track multiprocessor. The team plans three increasingly complex development cycles to assess the effectiveness of RASSP tools and process improvements in prototyping and building an embedded signal processor system. Martin Marietta RASSP Program OverviewJames E. Saultz
AbstractThe goal of the ARPA/Tri Services sponsored Rapid Prototyping of Application Specific of Signal Processors (RASSP) program as executed by Martin Marietta Corporation, is to improve by at least a factor of four the cost and time needed to develop and test signal processors. The approach to reaching the program's goal is based on three technology thrusts; methodology, Model Year Architecture, and infrastructure (enterprise). Using this triad of technology thrusts, Martin Marietta's RASSP team, composed of an alliance of companies, strives to implement virtual prototypes which can build evolving simulatable hardware and software models that are fully verified before manufacturing. Overview of the RACE Hardware and Software ArchitectureDarry S. IsensteinAbstractThe RACE architecture for multicomputers provides a high bandwidth, low latency system for solving real-time applications. This paper describes an interconnect technology built with a scalable crossbar building block. An overview of the software architecture that exploits this flexibility is also presented. Discussion focuses on the evolutionary growth path of the RACE architecture. Predicting the Future with RASSP BenchmarksJames C. AndersonAbstractCommercial computer programs for cost estimation are used to incrementally predict RASSP benchmark progress in many different areas, and serve as an aid in establishing a current-practice baseline for comparison. The programs are also used to predict costs beyond the scope of the benchmarks such as life cycle costs and costs for platforms not benchmarked. Processes and Experiences in VHDL Top-Down DesignRay DreilingAbstractDescribed are VHDL related methods and experiences from the RASSP programs model year effort. The "Virtual Prototype" development methodology is presented highlighting specific VHDL model views and their interactions with software design. Performance and Instruction Set Architecture modeling areas of the methodology are elaborated drawing from the experiences of the Demonstration team. Finally, ongoing work with multi-threaded operating system and cycle based VHDL simulators is explored as CAE technology solutions for growing design and analysis complexity. Rapid Prototyping of Digital Systems with COTS/ASIC ComponentsShahram FamorzadehAbstractElectronic Systems Design Automation (ESDA) is one of the challenging tasks in rapid prototyping and verification of digital systems. The goals of rapid prototyping include --- (i) Reduction in the design and verification time by an order of magnitude, (ii) Reduction in the cost of the design and lifecycle support process, and (iii) Capability for rapid insertion of new technology and algorithmic innovations into existing prototypes. This paper discusses the models and views in rapid prototyping, facilitated by VHDL, that allow rapid design and verification of large digital systems. Rapid Prototyping and the RASSP Design Environment (RDE)Jim SummersAbstractRASSP is an initiative to create a new process for the development of military signal processors. The objective is to specify a process and produce an environment that reduces both the development cycle time and the life cycle support cost while increasing the product quality, all by a factor of four (4x improvement. Motorola is a member of the Lockheed Sanders RASSP team and is the lead on the development of the RASSP Design Environment (RDE). The RDE is one component of the RASSP system that facilitates the achievement of these 4x improvement goals. RASSP Benchmark Program Overview G.A. Shaw
AbstractDuring the course of the RASSP development program, four major releases of the RASSP Design Environment (RDE) are planned by each of the two principal developers. The evolutionary RDE represented in each of these releases will encompass a growing number of electronic design automation tools coupled with architectural concepts and design methodologies appropriate for embedded signal processor development. The RASSP program is structured to involve many users in the evaluation of each release of the RASSP system. The benchmark component of the RASSP program represents a formalization of the evaluation process for the purpose of assessing performance of the RDE development early and frequently in the program, thereby influencing RDE development. This paper describes the benchmark component of the RASSP program and presents the goals, approach and status of the benchmarking activity. RASSP Education and FacilitationJack Corley, Vijay Madisetti, James Aylor, Anthony Gadient, Joe Wong, and Hal Carter
AbstractThe RASSP (Rapid Prototyping of Application Specific Signal Processing) Education and Facilitation (RASSP E&F) program is developing the innovative education and facilitation system needed to make RASSP technology widely used. The RASSP E&F team has three primary objectives: 1)to transfer the RASSP knowledge and technology into use in defense and commercial industry 2) to transfer the RASSP knowledge and technology into university curricula. 3)to facilitate the continuous improvement of RASSP through rapid information feedback. To accomplish these objectives, the RASSP E&F program is providing university and continuing education; a single point source for all RASSP information; and facilitating technology transfer to industry and academia. RASSP Methodology OverviewJeffrey S. Pridmore and W. Bernard SchamingAbstractThe goal of the Rapid Protyping of Application Specific Signal Processors (RASSP) program is to provide an improvement of (at least) a factor of four in the time required to conceptualize, design/upgrade, and field signal processor designs, with similar improvements in design quality and life-cycle cost. This paper focuses on describing the RASSP design methodology, which is the cornerstone for defining the requirements that will drive the Model Year architecture and design automation portions of the program. Elements emphasized in the methodology to support rapid prototyping include concurrent engineering, hardware/software codesign, and the iterative development of the processor as an evolving information medel that results in fully verified virtual prototypes throughout the design cycle. The RASSP Program: Overview and AccomplishmentsMark A. RichardsAbstractThe Rapid Prototyping of Application Specific Signal Processors (RASSP) program is a new four and one-half year, $150 million ARPA/Tri-Service initiative intended to dramatically improve the process by which complex digital systems, particularly embedded digital signal processors, are designed, manufactured, upgraded, and supported. RASSP seeks an improvement of at least a factor of four in the time required to take a design from concept to fielded prototype or to upgrade an existing design, with similar improvements in design quality and life cycle cost. The motivation for RASSP is the need to provide affordable embedded signal processors for a wide range of DoD systems that are state-of-the-art when they are fielded, rather than when they are first defined. RASSP Technology Base R&D OverviewDr. John Hines and Darrell Barker
AbstractThe Goal of the rapid Prototyping of Application Specific Signal Processors (RASSP) Technology Base Research and Development programs are to provide significant advancements beyond the current generation of design automation technology. This is in contrast to the two RASSP Development and Demonstration programs which are integrating and making the most of the currently available technologies. From the DOD's perspective the tech-base programs are very important because design automation technology will be the single most important factor in fielding timely and affordable systems with fewer resources. Many of the programs are aimed at the large complex digital signal processing (DSP) systems that are prevalent in the DOD, but they will also have widespread application beyond DSP design. These tech-base efforts will provide models where there are none available and automation to areas where the use of manual methods is normal. The set of programs is quite diverse but they follow a small set of themes including: innovative algorithms for digital signal processing, advanced design synthesis technology, hardware/software codesign and high level system trade-off tools, design automation infrastructure support, and the development of public domain VHDL models. This paper provides an overview of the RASSP tech-base effort, brief descriptions of the complete set of tech-base programs, and identifies technical points of contact for these efforts. RASSP Technology InsertionsJeffrey S. Pridmore, John S. Evans, Eric T. Pancoast, Robert Graybill and Thomas J. FritschAbstractMartin Marietta Corporation is pursuing the application of the RASSP program using two approaches. The first approach is to proliferate RASSP methodology, Model Year architecture, and infrastructure (enterprise) on a large scale through Martin Marietta's Engineering Productivity Initiative (EPI). The EPI approach focuses on selecting the best design process and tools, and institutionalizing them across the Martin Marietta engineering community of thousands of engineers at 10 major locations. The second approach is to work with specific, signal-processing program areas to apply RASSP methodology and tools. Currently, Martin Marietta is addressing the application of RASSP methodology to the four program areas below:
RASSP: Viewpoint from a Prime DeveloperWilliam R. Hood and Corey S. MyersAbstractThe Lockheed-led team of Motorola, Hughes and ISX has met all of the primary RASSP program objectives during the first year of the program. This paper reviews the goals of the program, and the unique ways in which Lockheed is meeting them. The flexible methodology and design environment are described along with the progress made in creating a standard enterprise framework. The progress of the demonstration effort is detailed as is the work towards proliferation of the RASSP process. The emphasis on VHDL and Ada-based virtual prototyping and its impact on Model Year Upgrades is discussed. The creation of the Virtual RASSP Corporation and the special Internet communication protocols developed to support the program are reviewed. The commercial spin-off of RASSP is discussed. Accomplishments in each of the program areas are reviewed along with specific goals for the next year of the program. Test Bench Development for RASSP DSP ModelsJames R. Armstrong, Geoffrey Frank, et al.AbstractGeneration of test benches for large DSP behavioral models is a complicated, labor intensive task. Also, tests generated manually satisfy no formal definition of completeness. To address these needs, high level approaches to test bench development are employed which relieve the modeler of the details of test bench development. CASE tools are used to develop the test bench VHDL code, i.e.state machine behavior is specified with Ilogix Express VHDL and sensor behavior with Comdisco SPW. An intelligent interface prompts the user for high level test bench information, and inserts this information into the test bench code. The intelligent interface also allows the user to specify and control file I/O as a data source. Conceptually speaking, two approaches are being explored: (1) Behavioral - CASE tools develop complete high level models of the test bench and (2) Structural - a library of primitive components is developed so that a conventional schematic capture tool, e.g. Synopsys Graphical Environment can be used to construct the test bench. Time Insensitive Binary to Binary Translation of Real Time SystemsBryce Cogswell and Z. SegallAbstractBinary to Binary Translation (BBT) provides a solution to the problem of migrating software from older architectures to newer, faster ones through direct translation of a program executable from one instruction-set to another, without the need for recompilation. While BBT technology is well established for traditional programs, the BBT transformation of real-time programs has additional constraints which are only now addressed. .... TRW's Communication Navigation Identification (CNI)Carolyn KuttnerAbstractTrw will demonstrate and validate the RASSP methodology and supporting computer-aided design (CAD) tool suite by developing integrated communication, navigation, and identification (CNI) prototype systems. CNI systems implement a number of established radio links, used operationally to exchange voice, tactical data, navigational data, and to identify friendly platforms versus foes. CNI is an excellent domain for RASSP because the exsisting waveform functions are well defined and don't change over time or across platforms. This means that CNI is very amenable to the concept of re-use central to RRASSP because the existing waveform functions are well defined and don't change over time or across platforms. This means that CNI is very amenable to the concept of re-use central to RASSP. The CNI requirements which change (and have in the past caused expensive redesign) are to reduce the cost and weight per CNI function, to add new functions, and to improve "ilities". These requirements are the type of model year upgrades which RASSP will make affordable. TRW will build two model year upgrades of CNI systems, demonstrating a minimum of a four fold reduction of cost and schedule. This paper describes the CNI domain to show how CNI designers can capitalize on multi-level re-use and the smooth insertion of digital technology for model year upgrades. This paper also presents CNI developer's point of view of some of the key features of RASSP system which will be used to build the prototypes - architecture for reuse, risk-driven virtual prototyping and hardware/software codesign. This paper gives the motivation for TRW's commitment to RASSP - why RASSP is needed and why TRW believes RASSP will support breakthrough improvements in productivity. SAR Processing for RASSP ApplicationB. Zuerndorfer and G.A. ShawAbstractDesign exercises, or benchmarks, in the RASSP program are undertaken as a vehicle to assess performance of the RASSP system. Application areas for these benchmarks are intended to present realistic challenges to RASSP and should be of interest to a broad community of users. The application chosen for the first series of RASSP benchmarks is that of synthetic aperture radar (SAR). SAR is an important tool for the collection of high-resolution, all-weather image data and has application to tactical military systems as well as civilian systems for remote sensing. SAR can also be used to identify man-made objects in the ground or in the air. Such object identification typically requires SAR processing to be performed in real-time by means of an embedded signal processor. The substantial computational throughput and memory requirements associated with image formation process alone make SAR a good application vehicle for use in benchmarking the RASSP design process. The Value of Lockheed Sanders RASSP ApproachJoseph F. TrepanierAbstractThis talk will present how Lockheed Sanders, Inc. is applying RASSP to a variety of programs across several divisions of the company. Lockheed Sanders produces diverse electronics products for a wide variety of mission areas and applications. Mr. Trepanier will describe how Lockheed Sanders perceives the value of RASSP to its business and will briefly discuss selected programs and the value added by the application of RASSP to them. VHDL Executable RequirementsAllan H. Anderson, Gary A. Shaw and Chris T. SungAbstractIn a top-down design methodology, requirements can be specified in an executable format to remove much of the ambiguity associated with written specifications. The VHSIC Hardware Description Language (VHDL) represents a potentially attractive vehicle for representing executable requirements. In connection with the first RASSP benchmark, a VHDL executable requirement was constructed to capture the interface timing and functional requirements of a real-time embedded processor for forming synthetic aperture radar (SAR) images. This paper discusses the implementation strategy, accuracy, and efficiency of the executable requirement. The associated test bench and metric for assessing image fidelity are presented. Methods for reducing execution time and plans for further work are discussed. VHDL Performance ModelingFred Rose, Todd Steeves and Todd CarpenterAbstractThe design and development of high performance computing systems is becoming incresingly complex. A primary ingredient of a sound design methodology is a detailed system performance model. A performance model expressed in VHDL serves as a simulatable specification, aids the identification of bottlenecks, and support performance validation. This document outlines an approach based on the VHDL performance models developed by Honeywell. VLSI Discrete Wavelet Transform ArchitecturesKeshab K. Parhi and Tracy C. DenkAbstract
Discrete wavelet transform (DWT) is based on time-scale rather than time-frequency representation. Wavelets are represented by
scaling or dilation equations as opposed to difference equations. The use of wavelet transform in video coding applications can
eliminate perceptual degradation at the block boundaries.
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