RASSP Educational Activities

by Maximo Salinas, James Aylor, Robert Klenke,
Harold Carter, Vijay Madisetti,
and Anthony Gadient

1. Introduction

Today, digital system design education is focused on a limited subset of embedded digital system applications. The academic focus tends to be on applications that are limited in complexity, lack real-time constraints, and can generally be satisfied by “hardware-only” implementations due to their limited flexibility [1,3]. The design of larger systems is taught via extrapolation of this approach.

Industry needs engineers that are trained in the latest, most effective embedded digital system design technologies. To meet this industrial need, the educational modus operandi must be updated to incorporate the revolutionary new design techniques being developed in the RASSP program and elsewhere.

To ensure the successful transfer of RASSP program technologies in the longer term, RASSP technologies need to be reflected in the curricula of our academic institutions. To accomplish this goal, a novel RASSP Education & Facilitation (RASSP E&F) program was defined and a team was tasked with leading the RASSP education efforts. The RASSP E&F program was awarded in June 1994 to a team led by SCRA with team members from the Georgia Institute of Technology, the University of Virginia, Raytheon, the University of Cincinnati, Arthur D. Little and Enterprise Integration Technologies (EIT). The mission statement for the education team was fairly comprehensive:

• Educate senior management as to the potential benefits obtainable through the application of RASSP technology thereby stimulating the use of RASSP technology and the demand for RASSP trained professionals;
• Work with universities to effect a paradigm shift in the graduate, undergraduate, and continuing professional digital system design curricula of small- and medium-sized universities to ensure that graduating students can meet industry’s need for RASSP trained engineers, scientists, and managers.

2. Module Concept in Education

The RASSP E&F team has developed a novel module-based framework that can be used to efficiently insert the technology being generated on the RASSP program into university curricula. Similar to the knowledge unit concept proposed by the Joint Curriculum Task force [2], modules are developed on specific topics and used to develop courses. The attractiveness of this approach is that it is easy to insert new material (through the use of a module) into an existing course. This technique is extremely important because of the inertia of curricula development.

Each module consists of a comprehensive discussion of one technical sub-area, (e.g., virtual prototyping) and presents the technical details, examples, and case studies needed to obtain a thorough understanding of the topic. The specific material found in a module includes such items as presentation materials, notes on presentation materials, predefined laboratories, and homework problems with solutions.

A typical module, illustrated in Figure 1, consists of three components. The first component is the fundamental core of design principles (e.g., in a high speed IIR digital filter design module, it could outline the use on the basic operations such as retiming, pipelining, and unfolding of the flow graph). The second component consists of examples, metrics, case studies and problems. This component provides simple examples that illustrate the theory covered in the fundamental core and provides problems that can be used for homework exercises. The third component of a module is a hands-on laboratory exercise. The laboratory exercise is intended to rigorously demonstrate the concepts taught in the other sections of the module by providing an opportunity to apply those theories on significant problems in a “learn by doing” fashion.

Each module represents a unit of a course that is independent of other modules in the course (aside from prerequisite requirements). A typical module is designed to provide three hours of lecture time. The laboratory portion of a module may actually not exist for all modules or may span multiple modules. In the ideal situation, the lab components represent a continuous, semester long design project broken into smaller pieces.

There are many advantages to encapsulating a focused amount of material in a modular fashion. These include:

• Modules can be used in a “mix and match” scenario, depending upon the particular area of digital system design as well as the target audience needs;
• As technology advances in an area, only modifications to applicable modules are necessary. This approach reduces the cost of upkeep and makes it easier to keep pace with the rapid pace of technological change;
• Modules can be easily incorporated into existing graduate or advanced undergraduate courses within a university.

• VHDL Basics: an introduction to the VHSIC Hardware Description Language (VHDL), IEEE Std 1076-1993, and its fundamental concepts.
• Structural VHDL: a description of the use of VHDL in describing models in terms of component instantiations and interconnections.
• Behavioral VHDL: a description of VHDL features that can be used to describe the outputs of a component in response to changes in its inputs.
• Advanced Constructs in VHDL: a description of the constructs in VHDL that are more reminiscent of high-level programming languages such as file I/O, abstract data types, shared variables, etc.
• System Level Modeling: an introduction to techniques used for modeling systems at a high level (CPU, Memories, Interconnect, etc.) in a top-down design process.
• Hardware/Software Codesign: an introduction to the concepts of codesign (concurrent design) of hardware and software, from specifications, for embedded systems.
• Hardware/Software Partitioning: an introduction to the techniques used, in the design of embedded systems, to determine which functions are to be implemented in software on COTS processors and which are to be implemented in hardware (ASICs) and the trade-offs associated with such a partitioning.
• DSP Architectures: a description of various computation, communication, I/O, software, test, and maintenance architectures for embedded digital signal processors.
• Scheduling & Assignment for DSP: methods for allocation, scheduling and assignment of a set of software tasks in a DSP application to a selected hardware architecture.
• DSP Algorithm Design: a description, including examples, of a number of simulation-based functional and timing design and verification environments for design of digital signal processing algorithms.
• Communication Protocols: a presentation of selected communications protocols for DSP architectures geared towards understanding the relationship between them and overall system performance.
• RASSP Methodology Overview: an introduction to the RASSP program including a comparison of pre-RASSP and current RASSP design methodologies.
• Virtual Prototyping for DSP Architectures: a description of virtual prototyping (simulation based design) as applied to the design of DSP systems. Included are executable specifications, algorithm development, architecture selection, detailed design and implementation and test.
• Virtual Prototyping using VHDL: A discussion on how a virtual prototyping based top-down design flow is realized in VHDL. A complex design example is presented showing detailed integration and test.
• Hardware Synthesis Overview: an introduction on the concepts of hardware synthesis including definitions, how synthesis tools function, and general coding styles for successful hardware synthesis.
• Libraries: Generation, Maintenance, and Reuse Overview: an overview of problems that inhibit hardware/software reuse practice and current solutions for them. A survey of reuse metrics and a tool that tracks them is also presented.
• Test Technology Overview: a presentation of the fundamentals of digital systems testing including fault modeling, test generation and fault simulation algorithms, and design for testability and built-in self test techniques.
• Requirements and Specifications Modeling: a description of how executable specifications are derived from customer requirements, and a description of how they drive the top-down design process through regression testing.
• Performance Modeling using VHDL: a presentation of the environments that exist for doing simulation based performance modeling using VHDL. A discussion of hybrid modeling – the simulation of mixed performance and behavioral models – is included.
• Enterprise Integration: a presentation on the supporting EDA infrastructure, tool/configuration management rationale, workflow methodologies, and distributed collaboration and design environments, utilized in a top-down system-level design process.
• Cost Analysis for Design: a discussion of how quantitative and empirical cost models for design, implementation, test maintenance, and production can be utilized in the front-end design of embedded digital systems, in a concurrent engineering approach.
• Robust Design for Quality: a presentation on how products can be designed for 6-sigma quality. Included are state-of-art discussions on Taguchi methods, Monte Carlo methods, surface response, and fuzzy set methods for improving quality of products by improving their tolerance to process parameter variations with case studies.
• Project Management: this presentation covers the scheduling, administrative, workflow, financial, and customer-support related issues in managing large electronics system design projects.
• Design for Manufacturing: a description of how products and processes are designed for ease of manufacture.
• Implementation Technologies: a description of the various technologies available for implementation of digital systems including trade-offs and changes in the design process for them. Included are FPGAs, ASICs, Custom ICs, and MCMs.

The presentation material is being developed using Microsoft PowerPoint(TM), version 4.0. The slides use bulletized text, illustrations, etc. to communicate the subject matter. Associated with each slide is a “notes page.” These notes provide the instructor with in-depth information including background, context, and references for further topic exploration. If desired, copies of the slides may be provided to the students. Although the hard copies tend to be in black and white, the presentations are in full color, when shown with a projection system.

3. University Education

To create the technology push for RASSP, an innovative program targeted primarily at small- and medium-sized universities has been established. As is illustrated in Figure 2, the education and research programs within universities are ultimately driven by the application needs of industry and government. These application areas determine the types of resources (e.g., qualified personnel) and technologies (e.g., research) that industry and government need from the university community. To ensure the successful transfer of RASSP technologies over the long-term, these technologies must be reflected in the curricula of the academic institutions. This approach will assure that industry’s need for “resources” who understand the RASSP technology and for improvements to that technology will be met by the university community. This approach will also provide the RASSP technology push that will complement the technology pull being created through Executive Seminars. Furthermore, given the increasing rate of technological change in the area of embedded digital systems, it is important that mechanisms be established that will help assure that the academic community can meet the changing needs of industry and government.

The need to update the existing curricula is evidenced by a recent survey sponsored by Texas Instruments and Toshiba. The results of this survey, designed to assess the status of hardware description language (HDL) education in engineering schools within universities in the United States and Japan [5], indicated an alarmingly low percentage of graduating seniors possessing a working knowledge of either VHDL or Verilog. Given the importance of top-down, language-based design techniques to meet the design challenges brought about by the rapid change in manufacturing capabilities, the results of this survey are significant. Indeed, this survey stimulated Robert Rozeboom, VP of Texas Instruments, to say, “It's clear there is a significant need, and therefore, opportunity to increase the amount of training among undergraduate electrical engineering students at major universities worldwide [4].”

Through the RASSP E&F program, DARPA and the Tri-Services are working to help universities adapt their curricula to incorporate RASSP technology so that tomorrow’s graduates (BS, MS, Ph.D.) will be able to better meet the needs of industry and government. The approach being taken is to not only help the university community incorporate RASSP technology today, but also to establish a framework that will help the university community to effectively and efficiently respond to the ever changing needs of industry and government brought on by the dramatic rate of technological change.

One of the key challenges in the development of module-based RASSP curricula is determining what modules should be developed. The relationship between the module definition process and a module-based RASSP curriculum is presented in Figure 3. Using this technique, an example concentration area within a masters degree program is illustrated by the three courses shown in Table 1. These courses, RASSP 100, RASSP 101 and RASSP 102 have been piloted at the University of Virginia, the University of Cincinnati and the Georgia Institute of Technology. Currently more than 80 universities around the United States have obtained modules developed by the RASSP E&F team for use in their curricula.

The proposed university course sequence begins with RASSP 100, which focuses on rapid prototyping using VHDL, and explores the different levels of modeling, the relatively new practice of hardware/software codesign, and library reuse. It is followed by RASSP 101 and RASSP 102. RASSP 101 explores DSP algorithms and architectures in detail. RASSP 102 then examines some of the enterprise level issues associated with embedded digital system design. Not shown in Table 1, RASSP 103, is a project-based course designed to apply the principles learned from the earlier RASSP courses and to expose the student to a “near” industry scale problem. Table 1 also illustrates the flexibility of the modular approach.

By defining a module-based framework, proposing an example curriculum, and developing specific course material, the RASSP E&F program is creating an infrastructure that can help to ease transition from today’s circuit design dominated curricula, to one that incorporates the spectrum of top-down design capabilities needed to design sophisticated, embedded digital systems. The most significant attribute of the module based approach is its ability to outlive the RASSP program and be ultimately “managed” by the education community itself. It is also generic in such a way that it can help universities more easily adapt to the rapidly changing state-of-the-art in embedded system design technology.

3.1 Transferring the E&F Education Framework

In addition to developing an infrastructure to assist in the transfer of the RASSP technology, the RASSP E&F team is leading a series of “teach the teacher” educator workshops. These workshops are designed to provide instructors with the understanding and material they need to include the latest technology in the classes they teach. The RASSP E&F team is working with other organizations, for example, the National Science Foundation and VHDL International (VI), to ensure that the widest possible benefits are derived from these workshops.

Working together with VI, several workshops have been held and others are scheduled. The focus of these workshops is on VHDL and its use in top-down design. (For more information see pages 6 & 9). VI is working with its members to ensure low or no cost access to VHDL software for universities. Together, the VI and RASSP E&F efforts are providing the impetus for addressing the need so clearly stated by Robert Rozeboom, VP of Texas Instruments. In addition, a Top-Down Design Workshop for Educators has been developed and is scheduled for mid-August at the University of Virginia.

In order to transfer RASSP technology to engineers, educators, and managers, the E&F Education team has devised a format in which the education modules can be delivered in three to five day short courses available to working professionals. Initially, a series of short courses modeled after the university courses RASSP100, 101, and 102 which included largely the same modules was developed. It is important to emphasize that the modules used in these short courses are exactly the same as those in university courses. Any required laboratory and other exercises accompanying the modules, however, required modifications to accommodate the more limited time constraints imposed by the short courses over the university courses.

More recently, however, the short course mechanism has been modified to address different audience’s needs. The team has de-emphasized the predefined short course sequence and allowed industrial audiences to design their own short courses by selecting from the list of available modules in an almost a la carte fashion. The education team must, of course, ensure that any prerequisites are satisfied.

5. Executive Education

To help create a pull for the RASSP technology and professionals versed in that technology, a series of Executive Seminars have been developed and delivered. Targeting senior executives in industry and government, these seminars are designed to generate understanding and the desire to incorporate RASSP technology into their business by focusing on the business implications underlying the RASSP technology and presenting the business case behind this technology. To date, seminars have been given to senior managers in such places as Rockwell, Alliant Defense Electronics Systems, the National Security Agency (NSA), Texas Instruments, Allied Signal Corporation, NASA, and so on.

The seminars draw much of their material from the E&F educational modules. Unlike the university and short courses, however, seminars will only rarely include complete modules. Rather, they present the high-level concepts contained in the modules in order to communicate the advances of RASSP and encourage further inspection via additional courses or other RASSP transfer activities. The article by Jim Scharf, Sr., Mitchell Heller, and Larry Karns titled "Executive Education: Key to Implementing RASSP" explains executive education activities in more detail.

6. Conclusions

The RASSP Education and Facilitation team has been tasked with leading the RASSP technology transfer efforts. Very early in the process, the E&F team realized one of the key elements to a successful transfer of RASSP technology was the incorporation of the technology into academic programs. Realizing how hard it is to insert new technologies into a curriculum, the E&F team developed a novel approach to accomplish this task. This new approach, based on the development of technology modules, is currently being tested at the various universities of the team members. At the same time, the E&F team is initiating programs to see that this approach and the RASSP technology is adopted by the academic community. It is anticipated that the approach and the specific modules will be of significant benefit to the educational community, given the enormous task of keeping curricula current with the advances in microelectronics. An additional benefit of the module concept is the ability to reuse material for presentation in university courses, short courses, and executive seminars.

References

[1] A.B. Tucker and B. H. Barnes, “Flexible Design: A Summary of Computing Curricula 1991”, IEEE Computer, Vol. 24, No. 11, Nov. 1991, pp.56-66.

[2] ACM/IEEE-CS Joint Curriculum Task Force, Computing Curricula 1991, ACM Baltimore, MD., Order No. 201880, 1991.

[3] S.W. Director and R. A. Rohrer, “Reengineering the Curriculum: Design and Analysis of a New Undergraduate Electrical and Computer Engineering Degree at Carnegie Mellon University”, Proceedings of the IEEE, Vol. 83, No. 9, Sept. 1995, pp. 1246-1269.

[4] M. Jain, “Executive Director’s Message”, VHDL Times, Vol. 4, No. 3, page 2, Third Quarter 1995.

[5] VHDL University Education Report, from VHDL International, Santa Clara, CA.