The RASSP Digest - Vol. 3, September 1996
Design Tools and Architectures for Dedicated DSP Processors
by Keshab K. Parhi and Ching-Yi Wang
Abstract
Current demands on prototyping complex DSP applications has placed more emphasis on developing efficient methods and CAD tools. In our research, we have developed the Minnesota ARchitecture Synthesis (MARS) system that is capable of converting high-level behavioral descriptions into hardware architectures in very short run times. MARS utilizes the Mentor Graphics toolset as a GUI, simulator base, and layout editor. MARS also provides a structural VHDL output of the final design. Other efforts have developed novel and efficient architectures for difficult DSP applications such as: discrete wavelet transforms, novel topologies for ADSL/HDSL applications, and Reed-Solomon encoders.
1. Introduction
Our primary goals for the RASSP project is to develop CAD tools that efficiently explore various design decisions and their impact on the final implementation. We are also investigating efficient and novel architectures for difficult signal processing applications. The motivation behind developing these new architectures is to gain a better understanding of efficient translations from algorithm to hardware and this will lead to better CAD tools. We have been developing the Minnesota ARchitecture Synthesis (MARS) system which will automatically generate high-performance, dedicated architectures within a heterogeneous design environment. We are also investigating the design of high-performance and low-power architectures for the following DSP applications: discrete wavelet transforms, novel topologies for ADSL/HDSL applications, finite field arithmetic architectures, and Reed-Solomon encoders.
2. Design Tools
In the process of rapidly designing prototypes of real-time DSP systems, the use of high-level synthesis has become a more common and crucial step in the design flow because many real-time applications require high sample rates or low power consumption that can only be implemented by dedicated architectures. We have developed two approaches to this problem, a heuristic technique and an optimal integer linear programming (ILP) model based technique. Heuristic methods are attractive because they can generate good results in short CPU times; however they cannot guarantee optimal solutions. The more formalized approaches that utilize ILP models are attractive because they are capable of generating optimal solutions and are more flexible; however they suffer in exponential increases in run times as the design constraints become less restrictive. Most of the previously developed synthesis systems assume that all same type operations will be assigned to one type of hardware functional unit (e.g., all addition operations will be processed by full adders). A few systems allow for different types of processors for the same type operations; however, they only utilize homogeneous architectures where all of the processors are implemented using a single implementation style such as bit-parallel or bit-serial. Our work considers synthesis using a heterogeneous architecture environment where different types of functional units (including implementation styles) can be used to process same type operations. By allowing heterogeneous processors in the final architecture, the data format of one processor may not necessarily be the same as another processor [1][2][3]. For example, the final design may contain an adder which computes one word in one clock cycle and a second adder which processes a half-word in one clock cycle. This leads to the need for data-format converters which accept input data in a certain format and generate output data in a different format where the data format may be bit-serial or digit-serial or bit-parallel.
3. Architectures
We are also investigating the design of efficient and novel architectures for three different and unrelated DSP applications. Through this work, we have developed new architectures and systematic techniques that have lead to more robust CAD tools. The three different DSP applications that we are pursing include high-performance architectures for the discrete wavelet transform, new designs for ADSL/HDSL applications, more efficient architectures for finite field arithmetic, and low-power Reed-Solomon encoders. We developed new systematic techniques for designing efficient lattice structure discrete wavelet transform architectures. From this work, we described a general approach to design efficient architectures for multirate applications [4][5]. We have also developed novel topologies for ADSL/HDSL applications [6]. In this work we compared the efficiency of the various architectures and analyzed the tradeoffs during the design process. We developed and implemented new low-latency arithmetic processors for finite field applications and designed efficient Reed-Solomon encoders [7].
4. Deliverables
Our deliverables include the MARS synthesis toolset, a small test library of functional units and converters, and all publications on all aspects of our research supported by the RASSP contract.
5. Conclusion
We developed two techniques that efficiently performs high-level synthesis within a heterogeneous design environment. We developed a heuristic that is fast and efficient and a set of ILP models that are more flexible and can guarantee optimal solutions. Both techniques generate a low-cost solution (including data-format converters) in terms of total area consumed. This heuristic algorithm has been incorporated into the MARS-II synthesis system and is integrated within the Mentor Graphics toolset. Although the heuristic approach cannot guarantee optimal results, our experiments have shown that MARS-II is able to produce optimal and near optimal solutions in one to two orders of magnitude less time than our more robust ILP models. We have developed new systematic techniques for designing efficient discrete wavelet transform architectures. We have also developed new architectures for ADSL/HDSL applications and new low-latency arithmetic processors for finite field applications and low-power Reed-Solomon encoders.
References
[1] K. Ito, L. E. Lucke, and K.K. Parhi, “Module Selection and Data Format Conversion for Cost-Optimal DSP Synthesis,” in International Conference on Computer Aided Design, (San Jose, CA), pp. 322-327, November 1994.
[2] C.-Y. Wang, and K.K. Parhi, “High-Level DSP Synthesis using Concurrent Transformations, Scheduling, and Allocation,” IEEE Transactions on Computer Aided Design, Vol. 14, No. 3, pp. 274-295, March 1995.
[3] Y.-N. Chang, C.-Y. Wang, and K.K. Parhi, “Loop-List Scheduling with Heterogeneous Functional Units,” in Great Lakes Symposium on VLSI, (Ames, IA), pp. 2-7, March 1996.
[4] T. C. Denk and K. K. Parhi, “Systematic Design of Architectures for M-ary Tree-Structured Filter Banks,” in VLSI Signal Processing VIII (T.Nishitani and K. K. Parhi, eds.), pp. 157-166, IEEE Press, 1995. (Proc. of the 1995 IEEE Workshop on VLSI Signal Processing, Osaka, Japan).
[5] T. C. Denk, M. Majumdar, and K. K. Parhi, “Two-Dimensional Retiming with Low Memory Requirements,” in International Conference on Acoustics, Speech, and Signal Processing, (Atlanta, GA), pp. 3330-3333, May 1996.
[6] A. Shalash and K. K. Parhi, “Discrete Mutlitone Versus Carrierless AM/PM Architecture Comparison,” in International Symposium on Circuits and Systems, (Atlanta, GA), pp. II:560-564, May 1996.
[7] S. K. Jain and K. K. Parhi, “Efficient Standard Basis Reed-Solomon Encoder,” in International Conference on Acoustics, Speech and Signal Processing, (Atlanta, GA), pp. 3287-3290, May 1996.
Keshab K. Parhi and Ching-Yi Wang
Department of Electrical Engineering
University of Minnesota
200 Union Street SE
Minneapolis, MN 55455
parhi@ee.umn.edu
Newsletter Index
The RASSP Digest - Vol. 3, September 1996
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