The RASSP Digest - Vol. 3, September 1996
Performance Modeling Workbench -
A VHDL-Based Hardware/Software Codesign Tool
by Charles W. Buenzli, Jr. and Jay Runkel
Abstract
Omniview, Inc., in conjunction with the Honeywell Technology Center, is developing a VHDL based Hardware/Software Codesign tool, code named Performance Modeling Workbench (PMW), as part of the RASSP Technology Base program. PMW allows a designer to rapidly create alternative hardware/software architectures and simulate them to validate system performance, find bottlenecks, and identify overdesigns. PMW facilitates the RASSP 4X goal by reducing performance model development time by an order of magnitude and by surfacing problems early in the design cycle.
1. Introduction
Incremental refinement and validation of each design phase through VHDL modeling is one of the cornerstones of the RASSP design methodology. VHDL performance models, because of their high level of abstraction, play a key role in this process during the early system design phases (see Figure 1). They also bridge the communication gap between system design and the detailed design of the hardware and software.
Performance models describe a system’s time-related aspects: throughput, response time, latency, and utilization. They generally do not model the applications data or its transforms except for some high level control related behavior. As a result, performance models simulate much faster than behavioral models. In one example [1], a 24 processor system modeled in VHDL at the performance-level simulated the equivalent of 2,857,000 instructions per second, versus 5 instructions per second for a single I860 processor modeled at the Instruction Set Architecture (ISA)-level model.
The major impediments to the widespread adoption of VHDL performance modeling bus been the lack of commercially available performance models in VHDL and a user-friendly environment that allows the designer to model systems in familiar terms and isolates him from the underlying implementation details. The Honeywell Technology Center has partially solved the model availability problem with their development of a generic, parameterized library of VHDL-based performance models. How ever, most users found them too complex to understand and use [2-5]. It is Omniview’s vision and goal for PMW to provide an integrated, user-friendly environment for VHDL-based performance modeling that will remove these impediments and efficiently analyze the volume of performance data from systems having hundreds or thousands of processors.
2. PMW Overview
The PMW enables designers to rapidly construct performance models by providing a library of reusable performance-modeling elements. This library is based upon the Honeywell Performance-Modeling Library and leverages off the performance-modeling techniques developed at the University of Virginia [6]. The PMW library, which is implemented in VHDL, contains detailed performance models of processors, memories, communication devices, input and output devices, operating systems, and application software (Figure 2). These models define the speed at which processors execute various classes of instructions, characterize the sequence of instructions representing software applications, and the speed at which memories, input and output devices, and communication elements process data. In addition, these models may be simulated with fully-functional models supporting an all-VHDL, design process where the functional blocks of a performance model can be incrementally refined to functional models as necessary.
The PMW provides a suite of design editors for configuring performance models that combine elements from the PMW performance-modeling library (Figure 3). A graphical-capture tool is used to successively decompose a system into functional blocks defining the system’s hardware architecture. Performance models for the leaf-level hardware blocks are defined by selecting an element from the PMW library, specifying the connections among its ports and the other elements in the system, and customizing the clement’s parameters so that it exhibits the desired behavior. The software architecture of a system is defined by decomposing the software into tasks and specifying the messages communicated among each task. The behavior of each individual task is defined by creating a flow chart. The computational requirements of each flow chart block are specified by selecting predefined software elements from PMW library or by characterizing the instructions and memory operations executed by the block.
The PMW provides analysis and visualization support to enable a designer to verify the behavior of performance models, to identify bottlenecks and over-designs, and to compare design performance. Visualization support is necessary because of the vast amount of data communicated among the components of a complex system. This information overwhelms the displays provided by most VHDL simulators, especially when there is a large number of processors in a system.
The PMW analysis support includes standard analysis tools, such as activity timeliness bar graphs, and histograms, which display the latency, throughput, and utilization of system components (Figure 4). In addition, the PMW provides analysis tools that animate the architecture diagrams created in the hardware and software editors to display The system’s simulation behavior. These animation tools color code the system components according to their latency, throughput, and utilization to help a designer quickly identify bottlenecks and overdesigns. The PMW can also export simulation results and performance metrics so that they can be loaded into spreadsheets or other analysis tools.
3. Conclusion
Prototypes of PMW are being used by RASSP participants, other DoD agencies and commercial companies. The feedback from these evaluation sites has been very positive and has been used by the development team to implement a continuous quality improvement process that will insure the commercial product resulting from the Technology Base research will meet their needs. A commercial product release is scheduled for the fourth quarter of 1996.
4. References
[1] Carpenter, T. & Hein, C., “VHDL-Based Top-Down Virtual Prototyping for Large DSP Systems, “Lockheed Martin Technical Presentation,” Camden, NJ, November 2. 1996.
12] Rose, F., Steeves, T. & Carpenter, T., “ VHDL Performance Models,” Proceedings 1st Annual RASSP Conference, Arlington, VA, August 1994, pp 60-70.
[3] Steeves, T., et al, “Evaluating Distributed Muliprocessor Designs,” Proceedings 2nd Annual RASSP Conference, Arlington, VA, July 1995, pp 95-102.
[4] Shackleton, J., & Steeves, T., “Advanced Multiprocessor Systems Modeling,” Proceedings Fall 1996 VIUF, Boston, MA, October 1995, pp 8.21-8.28.
[5] Carpenter, T., Rose, F., & Steeves, T., “VHDL-Architectural Assessment Environment.”
[6] Aylor, J.H., Waxman, R., Johnson, B.W., & Williams, R.D., “The Integration of Performance and Functional Modeling in VHDL,” Chapter 2 in Performance and Fault Modeling with VHDL, edited bv Joel M. Schoen, Prentice Hall, Inc., Englewood Cliffs, NJ,1992, pp 22-145.
Charles W. Buenzli, Jr.
Omniview, Inc.
100 High Tower Blvd., Suite 201
Pittsburgh, PA 15205
charles@omnivw.com
Jay T. Runkel
Omniview, Inc.
100 High Tower Blvd., Suite 201
Pittsburgh, PA 15205
runkel@omnivw.com
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The RASSP Digest - Vol. 3, September 1996
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