LV Software, Inc. (doing business as LogicVision) has been contracted as part of RASSP Technology Base to develop a hierarchical and integrated Built-In Self-Test (BIST) methodology and its associated tools. The concept of BIST offers a paradigm shift over the conventional (i.e. external) form of manufacture testing, which scales extremely well with RASSP objectives. This article briefly describes why BIST is more useful than external testing, followed by a description of how BIST is being developed to meet the objectives of the RASSP contract.
The objective of RASSP is to dramatically improve the process by which complex digital systems, particularly embedded signal processors, are specified, designed, documented, manufactured, and supported. A critical component of this methodology has to do with the manufacturing test and its implications on the design and support process. For complex systems, the total cost of manufacturing and support is overwhelmingly dominated by the conventional external test process. In fact, it has been observed that this cost can be as much as 30% of the total manufacturing cost, and the ratio is expected to continue to grow with the increasing complexity. A paradigm shift based on the concepts of Built-In Self-Test (BIST) and Design For Testability (DFT) has already started to take root, with significant resulting improvements. LogicVision was awarded a tech-base contract for hierarchical and integrated BIST (HIBIST) test methodology and tool set starting October 1, 1994.
The technical scope of the contract is to develop a pragmatic scheme and associated Computer-Aided Design (CAD) tools to make Built-In Self-Test (BIST) an autonomous, integrated and hierarchical feature for electronic systems, particularly Digital Signal Processors (DSP). The contractor shall develop the tools and methodology to
This article briefly describes the comparison of external testing to Built-In Self-Test, and how HIBIST methodology is being developed.
In the context of the RASSP program, testing often refers to the testing of functional description, as in “a test-bench for a VHDL entity.” While this form of test sequences or test patterns is useful for design validation, it is often not sufficient for manufacture test. In general, a functional test is carried out to validate or verify that a design meets certain specifications, whereas a manufacture test is used to validate that an already known-to-be correct design was manufactured correctly. At the manufacture test, the concern is with ensuring that the actual physical structure of the design agrees with the logical or functional description. Any defects or failures in the manufacturing process may impact the physical structure and therefore testing at the manufacture level is also referred to as structural testing. Unless otherwise specified, all references to testing in this article are to structural testing.
The conventional form of testing requires access to a multi-million dollar Automatic Test Equipment (ATE) set-up which must be extensively programmed to perform testing on the specific device under consideration. This external form of testing, useful and well grounded as it may be, starts breaking down with the increasing complexity of electronic systems being designed and manufactured with the emerging sub-micron and deep sub-micron technologies:
In very simple terms, external testing does not scale well with the continuing miniaturization in the microelectronics industry. There is clearly a need for a paradigm shift that would scale well with the emerging technologies and will help meet the 4X objectives of RASSP.
The Built-In Self-Test (BIST) form of testing allows the creation of such a paradigm. BIST offers an at-speed test capability for a circuit and the capability is built inside the circuit being tested. When the circuit is simple, such as an embedded memory in a chip, it will have its own BIST tester, complete with the test generation, test application and response analysis capabilities to declare the device good or bad as shown in figure 1. Seen from outside, such a circuit would be an autonomously BISTed (ABISTed) device.
There are several deliverables related to the ABIST capability being developed under this RASSP contract. First, major building blocks used in the design of RASSP systems must be identified in collaboration with RASSP prime contractors (Lockheed Martin). Those blocks can be embedded in ASICs or off-the-shelf components like RAMs, ROMs, FIFOs, FPGAs, PALs, etc. For each of those blocks, specific BIST algorithms will be developed in accordance with appropriate fault models. Standard protocols and diagnosis procedures will also be developed to simplify manufacturing. Working prototypes of each BIST solution will be developed to validate the approach.
A complex circuit such as a large ASIC may however have several BIST testers: one for all its embedded memories, one for its logic, and one for its embedded core. All these BIST testers would be networked together to provide a complete BIST capability for the entire ASIC. Again, seen from outside, such an ASIC would be an autonomously BISTed device.
When this ABIST process is carried top-down in a hierarchical and integrated manner for the system, board, and multichip modules (MCM) levels, it provides a glimpse of how BIST can be used to perform most of the testing without any ATE. The ATE is being replaced by an intelligent network of small, designed-in, special-purpose testers. This hierarchical and integrated BIST (HIBIST) is a distributed form of testing versus external tests which is a centralized form of testing.
The access and control of the ABIST blocks will be done by exploiting the capabilities of the various test buses described by the IEEE 1149 standard, in particular 1149.1 (Boundary Scan for board/ASIC level) and 1149.5 (System/module/Board test access) as shown in figure 2.
In order to fully achieve all the benefits of BIST (see section 7), a lot more automation is required at various levels of the design capture process and physical packaging hierarchy. This automation aspect is an integral aspect of ABIST and HIBIST related deliverables.
One of the main productivity factor that RASSP will provide to designers is the ability to capture the system specification at a high level [register transfer level (RTL) or higher] and to turn this description into a structural representation suitable for manufacturing. It is an objective of this contract to achieve the same level of productivity for the insertion of BIST by providing front-end design capabilities as shown in figure 3. For example, a BIST circuit can be automatically synthesized for an off-the-shelf memory that can be tested by an adjacent ASIC or FPGA or by a board level test controller.
Another important objective is the ability to specify test features in a top-down fashion as well as being able to reuse test information at various manufacturing steps (ASIC, board, module, system) in a bottom-up way.
The deliverables for the contract related to automation cover the development of the ABIST point tools, and the HIBIST tool set. Cadence Design Systems is a member of the team for this contract and is helping in integrating ABIST and HIBIST to their framework and other design tools.
The three key advantages of HIBIST are time to market, reusability and quality.
Time to Market. The biggest advantage of distributed testing is the phenomenal improvement it provides in productivity during the development cycle. An ideal scenario is when the design of an ASIC and of the associated BIST capability is complete at the same time and at the same level, say in VHDL or Verilog at the register-transfer level, ready together for automatic logic synthesis. Moreover, the test plan, the test program, and the test coverage are available as soon as the device design is complete. This, in the case of submicron ASICs, saves several weeks to months of development time. Even if BIST is used on only a part of the ASIC, the resulting savings in the time to market and in reduced acquisition costs for ATE can be quite significant. This concept can be extended to work at board and system level with the same level of effectiveness.
Reusability. A BISTed device can be tested over and over again whenever and wherever the need be. A BISTed ASIC for instance can be tested right after manufacturing, at the PCB level, at the system level, or in the field, with the same degree of ease. Moreover, the BISTed ASIC can simplify the testing of the board, or the system it is on. In fact, if a BISTed system was designed in an integrated and hierarchical manner with BISTed components at each level, such a system would be easily diagnosable, repairable, maintainable, and would cost far less than a corresponding ATE based version.
Quality. As pointed out earlier, the at-speed testing of sub-micron and deep sub-micron devices by external testers is not a trivial task. In general, the ATE themselves always have to be able to work at speeds higher than that of the device being tested. This issue becomes much simpler when the BIST tester is built with the same technology as the device being tested and with no corresponding pin-electronics or interface problems. The BIST testers not only perform at-speed testing, but they can be used to apply significantly more test vectors than external testers, resulting in better quality.
In brief, HIBIST provides a structured and manageable solution for manufacture testing of large systems. This distributed form of testing also provides portability, modularity, reusability, and seamless integration within the top-down design flow. Also simplified with HIBIST are several tasks from design debugging to field diagnosis. LogicVision already offers a complete BIST capability at the ASIC level in the form of an EDA product called ICBIST. Similar capabilities at the board and system levels will be offered in the near future with the help of the RASSP contract. The challenges will be (i) to accommodate COTS parts that are not designed with any DFT or BIST, and (ii) to provide solutions that are generic but useful to a large class of applications. Nonetheless, the emergence of IEEE standard testability buses (1149.1 and 1149.5) and a strong support of BIST by Lockheed Martin and other commercial companies will certainly make HIBIST happen.
Benoit Nadeau-Dostie
LV Software, Inc.
1735 N. First Street, Suite 306
San Jose, CA 95112
benoit@lvision.com