The expanded exhibition was a highlight for this year's conference as over 300 attendees saw demonstrated the latest advances in tools for designing large DSP systems and the results of applying the tools to some real-world design problems. A theme throughout many of the booths was the results of the first benchmark -- the architecture design and virtual prototype of the SAR image formation processor. From the executable specification to the detailed virtual prototypes, people were able to follow the design process of a high performance, parallel DSP implementation. Also highlighted were the many booths from the RASSP technology base development and the corollary, non-funded, commercial market for DSP systems. Overall, the exchange was very beneficial for the RASSP and DSP system community. The technical program concurrent with the exhibition was focused around ten major themes. These themes were the introduction to RASSP and its second year accomplishment, demonstrations of the RASSP process, projecting RASSP benefits, systems performance modeling, HW/SW development processes, VHDL prototyping, benchmark results, model year architectures, design process management and novel design approaches. Each provided in depth coverage of development details of the front to back end design tools and processes.
In addition to the technical program, a tutorial day focused on providing in depth information about specific, important topics. The topics were Ptolemy, RASSP Design for test (DFT) methodology, and VHDL-based, top-down virtual prototyping for large DSP systems. Ptolemy is a significant new develop-ent in the RASSP program under the guidance of Dr. Edward Lee of the University of California, Berkeley. The results to date of this co-funded effort (the industry funds the other half) have already had a wide ranging impact with major EDA vendors, commercial mixed-signal developers, and the research community. The tutorials and the conference as a whole represent a significant effort within the RASSP program to focus on adoption and proliferation during the program development.
The first day of the general sessions and exhibits was also focused into an overview day which was separately promoted and drew an extra 75 attendees. It started with a keynote address by Dr. Robert Kahn, President, CNRI, and one of the founding developers (both in industry and at ARPA) of the ARPAnet and related technologies. His informative talk on the infrastructure needs of the National Information Infrastructure provided some insight into the methods being taken to re-build the base of the quickly expanding Internet so that virtual enterprises, large scale design, and commerce can occur over this shared and open resource. Following was an overview of the RASSP program which highlighted the early insertions and success of applying the RASSP technology to real system design problems.
Specifically, RASSP over the past year has been successful in the design of a back-end IRST companion to the ARPA sponsored Airborne InfraRed Measurement System (AIRMS) -- a high resolution IR detector and test station. By simply applying VHDL-based virtual prototyping to this project they realized a 2.2x overall savings in design time -- mostly coming from a very short HW/SW integration and test activity. This demonstration (a model year 0 excercise in IRST development of which you will see more in the coming years) was conducted over a virtual enterprise consisting of Hughes Aircraft (CA), Motorola (AZ) and Sanders, a Lockheed Martin Company (NH).
Additionally, a prevalent highlight was the UAV SAR image formation benchmark in which MIT Lincoln Labs developed an executable specification (in VHDL) and a real-time data source/sink. Two contractors then went off to design and build solutions -- first virtually and then in real hardware and software. The virtual prototype was used to assess performance, verify design criteria and validate critical software pieces before actually committing to hardware or full software development. A third contractor (Mitre) simply took the software specification and ported it to an Intel Paragon multi-processor computer to assess the viability of using general purpose, high performance computing architectures for this type of DSP algorithm. You are encouraged to get a copy of the proceedings and learn more about this exciting project.
The RASSP program, for the first time, is putting VHDL to use at all layers of abstraction in the design process. The significance is that this is the first, real documented case of using VHDL from executable specifications through performance analysis, system level modeling and down to RTL/Gate level synthesis -- a feature that has been touted as a capability for many years. A significant result of the RASSP program is the putting into practice the process and tools to support using a single language for [digital] functional specification from the requirements down to the final gates of the hardware. It is requiring real issues to be addressed such as how to deal with algorithm and software development in a language based specification refinement environment and how to define layers or stages in the design process at which models or detail should be defined.
Much is going on in the RASSP program and will continue to become apparent over the coming year. New, linked architecture analysis and design tool suites, taxonomies for modeling in VHDL at many abstraction levels, process modeling/ tracking/metric tools and support, model year architectures for simpler upgrades, design for test, links to manufacturing, more professional development and university courses, and many others. Please make sure to attend our third conference next July to see the developments and provide additional insight to the team to assist them in solving your problems.