The RASSP Digest - Vol. 2, No. 1, 1st. Qtr. 1995

Technology Base

VHDL Component Modeling: Impact on the RASSP Program

by J. Scott Calhoun and Dr. Bob Reese

Abstract

Mississippi State University's Microsystems Prototyping Laboratory (MPL) has been contracted as part of the RASSP Technology Base to develop VHDL models of selected Cypress Semiconductor standard integrated circuits. Mississippi State and Cypress have entered an agreement whereby Cypress will provide timing information necessary to create VHDL models of high quality and accuracy to be released as part of the RASSP program. MPL is also under contract to delivery VHDL-based tools which will assist the model developer in testing created VHDL models. Finally, MPL will be participating in the RASSP E&F through the development and release of a HTML-based VHDL course (this effort is currently non-funded).

1. Component VHDL Models and the RASSP Design Process

The Rapid Prototyping of Application Specific Signal Processors (RASSP) initiative is intended to dramatically improve the process by which complex digital systems, particularly embedded digital signal processors, are designed, manufactured, upgraded, and supported. RASSP seeks an improvement of at least a factor of four in the time required to take a design from concept to fielded prototype or to upgrade an existing design, with similar improvements in design quality and life cycle cost. The motivation for RASSP is the need to provide affordable embedded signal processors for a wide range of DoD systems that are state-of-the-art when they are fielded, rather than when they are first defined.

To accomplish these goals, improvements are being sought at all levels of today's system design methodology. In addition, RASSP is pushing the envelope upward in the electronics design process to develop tools and capability which will integrate system requirements and specification development; along with top-level hardware and software design development into the overall RASSP design flow seamlessly. The primary tangible output from a successful iteration of the RASSP design process will be the ability to produce virtual or model-year prototypes of complex digital electronic systems. These virtual prototypes will contain all the information necessary to quickly and successfully manufacture physical prototypes which will meet the documented system requirements. Simulation of the model-year prototypes utilizing VHDL (or some derivative there of) is the main verification mechanism by which the system is shown to meet the requirements levied against it.

At the design data level where individual system printed circuit boards are to be produced, simulations exist where there is a one-to-one correspondence between inner connected simulation models and the physical representation of the integrated circuits. From a system perspective this is the last and lowest level of simulation performed to verify the design correctness prior to fabrication. Many of the integrated circuits used in a PCB design may be ASICs. Those that are not fall into a broad category of circuits which are referred to as standard off-the-shelf components. This class of components include microprocessors (general purpose, signal, FPU, etc.), bus interface components (VME, MIL-STD-1553, etc), memory (RAM, PROM, FIFO, etc.), programmable logic devices (EPLD, PAL, FPGA, etc.), and specialized bus drivers (buffers, latches, transceivers). These components represent the bulk of the digital standard components sold by semiconductor companies in the world today for use in complex digital system designs. The RASSP Technology Base program has funded several VHDL modeling efforts to assist the RASSP program in obtaining VHDL models necessary to develop and demonstrate the overall RASSP design process. Mississippi State University has been funded to develop VHDL models of memory and programmable logic device standard components offered by Cypress Semiconductor, Inc. When completed, these models (along with others developed by the RASSP program) will be used to create the board level simulations necessary to verify correctness of RASSP designs prior to fabrication. This verification allows for virtual board designs to be debugged in simulation avoiding costly fabrication rework cycles.

2. VHDL Modeling at MSU

MSU has been tasked to provide VHDL models for standard Off-The-Shelf (OTS) logic devices provided by Cypress Semiconductor, Inc. Cypress has a design division located in Starkville where many of the components targeted for modeling ware designed. This affords ready access to internal data which may be needed to insure the accuracy and performance of developed models. Cypress has entered an agreement to work with MSU to provide all component information necessary to deliver to the RASSP program the highest quality of models possible.

The program calls for MSU to address the following part types: 
      1.  Flash PLD
      2.  FPGA
      3.  Erasable PLD
      4.  Dual Port SRAM
      5.  Single Port SRAM
      6.  PROM
      7.  FIFO
The modeling strategy developed at MSU will be to develop baseline methodologies for each part type listed above. In addition, as part type methodologies are developed, part models for multiple components in a part type will be developed as quickly as possible to deliver the maximum number of models possible. The following subsections describe the development strategy for each of the part types which are currently under development.

2.1 Single Port SRAM and PROM

Two general VHDL packages have been developed for generic memory device modeling. Both packages are memory-organization independent.

The packages are as follows:

1. A general memory package which statically allocates all model storage. This is suitable for ROM models and small RAM models.

2. A general memory package which dynamically allocates model storage and has a user-controlled option for swapping memory pages to disk. This is suitable for large and small RAM models. The models developed to date are: 32K x 8 EPROM (CY7C256), 32K x 8 SRAM (CY7C199- CMOS, CY7B199 - BiCMOS), 64 x 4 SRAM (CY7C195 - CMOS, CY7B195 - BiCMOS). The EPROM model uses the static memory model while the SRAM models use the dynamic model. The SRAM models utilize approximately 98% common code with timing packages accounting for most of the non-shared code.

2.2 Flash and Erasable PLD

A 22V10 PLD model (PALC22V10d) has been developed; the model makes extensive use of GENERATE statements based upon the JEDEC map to create the internal simulation structure. The GENERATE methodology gives good runtime performance in that only the programmed portions of the device contribute to the simulation overhead. We plan on following this methodology in modeling the more complex Cypress PLDs represented by the CY7C37X family.

2.3 Dual Port SRAM

We are currently studying the issue of dual port SRAM modeling. Dual port SRAMs such as the CY7B138 with on-board arbitration offer significant modeling challenge.

2.4 FPGA

Our FPGA modeling plans center around the Cypress pASIC380 family. At this time we have held only preliminary discussions with Cypress concerning possible modeling approaches.

3. VHDL Component Modeling Issues

The amount of VHDL component models available today is still relatively small. Therefore, there are and will be a number of modeling issues with regard to VHDL component models as models become available to the RASSP community as part of this program. These issues are briefly discussed.

3.1 EIA-567A

EIA-567A defines three packages and a recommended methodology for representing timing, electrical and physical view information in VHDL. At this time the EIA-567A specification has been followed in those areas in which it was felt that EIA-567A added value. To date, the timing view package has been utilized to a limited extent. Examples of 567A timing view compliance include adding generics for input wire delay and output load delay and generics for controlling 'X'-value and message generation on timing violations. MSU did not follow the recommended methodology for encoding timing parameters; a specialized timing package for representing databook timing values was developed. One reason for not using the 567A methodology is that it requires renaming the databook timing parameters to follow a generic template. This puts the burden on the model writer to deal with timing parameter name translation which can be error-prone. This also makes the model source code more obtuse to external readers who know the databook timing parameters and are not familiar with the 567A specification. Finally, there is no provision in the EIA-567A timing view for having different speed grades (e.g. -10, -15, -20), short of writing a different package for each grade which makes model code maintenance and test bench configuration awkward.

3.2 Model Portability and Interoperability

MSU has tested the models in both Vantage and Model Tech environments in order to ensure portability of the models. As per EIA-567A, the models utilize the IEEE-1164 standard logic package for the state/strength value system of the models. MSU is in the process of obtaining a set of models which will act as an interoperability test set. These models include a processor and several component models. MSU plans to create testbenches where MSU developed models and the obtained models will simulate in the same environment to ensure interoperability of MSU models with other industry developed models. In addition, MSU plans to work with other RASSP Technology Base contractors to create VHDL simulations which demonstrate the viability of VHDL as a simulation media throughout the RASSP design process.

4. Model Documentation and Release

VHDL component models developed by MSU are being documented and released via the World Wide Web (WWW). MSU has obtained permission from Cypress to post Web versions of the three component datasheets representing part of the initial model release. The model release mechanism will be built into the electronic datasheet for each part. Because of export restrictions on RASSP deliverable, VHDL model release will be limited to RASSP program participants.

4.1 WWW Component Datasheets

The WWW component datasheets are viewable from the MSU RASSP homepage (http://www.erc.msstate.edu/mpl/rassp/html/overview.html) by clicking on the VHDL Model Library icon. This presents the overall Cypress BiCMOS/CMOS Databook from which the datasheets for the parts to be modeled are contained. Traversal of the databook homepage reveals sections for part types (STATIC RAMS, PROMS, EPLDS). Each listing in these part types document represents a part that is either modeled or is projected to be modeled. Those which are complete are hyperlinked to the homepage for the individual circuit. A portion of the homepage for the 27C256 is shown on Figure 1.

4.2 WWW Component Model Release

RASSP VHDL models are export restricted. For initial releases from the RASSP Technology Base programs, the models are being released via the WWW utilizing restricted access and data encryption. There will be a single point of contact for model release per RASSP contractor or government organization. The procedure for release RASSP VHDL models is as follows:

An example model release is shown below:


Figure 1. 27C256 WWW Component Datasheet


Figure 2. 27C256 VHDL Model Release Form

The RASSP Digest - Vol. 2, No. 1, 1st. Qtr. 1995

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