The RASSP Digest - Vol. 2, No. 1, 1st. Qtr. 1995
Prime Development
Object-Oriented VHDL Provides New Modeling and Reuse Techniques for RASSP
by Dr. Sowmitri Swamy, Vista RASSP Program Manager
SCHAUMBURG, IL - Vista Technologies, Inc. and Martin Marietta identified new object-oriented constructs that can be implemented as an extension language to VHDL. This approach will improve system modeling and simulation, and increase the potential for component reuse.
The extension language, OO-VHDL, is a super-set of VHDL. It enables designers to mix OO-VHDL objects and traditional VHDL components as part of the same system description. It is important to note that this work is not defining a new language based on VHDL. It is identifying new constructs that can be implemented on top of VHDL.
A pre-processor implementation will generate simulatable VHDL code, which enables designers to leverage existing VHDL tools, such as analyzers and simulators. This approach provides users with the benefits of the language extension quickly and at modest cost, because no changes are needed in existing VHDL simulation tools.
An object-oriented approach is already well established as the preferred method to designing complex systems, particularly software systems. Its benefits, based on several years of experience, have been widely documented. Until now, it has not been used to design complex systems that also involve hardware design, such as signal processing systems.
1. Improved System Modeling and Simulation
Extensive simulation is a key ingredient in the RASSP methodology to develop new signal processing architectures or to make model year upgrades to architectures. Simulations are performed at several levels - system, architecture, register-transfer - using models written in VHDL.
For commercial, off-the-shelf components, application-specific integrated circuits, and programmable logic, designers get simulation models from commercial model libraries or generate them from automated modeling tools. But at the higher levels of the design hierarchy, designers develop (abstract) models individually and manually during the design process. The burden of generating these models, and ensuring that they are fit for reuse in subsequent model years, means that the RASSP environment must provide support for quick model development with the capability for reuse.
System-level models contain abstract components that are eventually implemented as a hardware component, a software component, or a mixture of the two. The cornerstone of OO-VHDL is the Entity Object, which enables the object-oriented specification of an abstract component - whether it is a hardware design unit or a software object. Using the object-oriented concept of “inheritance,” designers can reuse an EntityObject by making incremental changes in its behavior or interface.
The interaction between EntityObjects involves passing messages between them. These messages are commands to the recipient of the message to execute a specific operation. During system-level simulation, designers track the behavior of the system by examining the sequence of operations performed by various EntityObjects.
2. Elements of the OO-VHDL Approach
OO-VHDL provides new capabilities for encapsulation, reusability, inheritance, and message passing. Objects are typically described in two parts: an interface part and an implementation part, roughly corresponding to a VHDL entity declaration and architecture body. The object interfaces, known as class description, document the operations performed by an object. By reading a class description, it is easy for designers to determine the functionality of a component implementation part.
An object-oriented approach increases the potential for component reuse. For example, suppose a simple behavioral description of a highway/farm road traffic light controller exists, and you have to add left turn signals. The traditional approach would be to copy the old behavioral description and modify it. An object-oriented design reuse process factors out the common functionality of similar components in an inheritance hierarchy. Without inheritance, reuse can only occur at the component level; that is, either you must use the component as is, or you must design a new one.
Operations define an abstract procedural interface to an EntityObject. Messages invoke the operations. When an OO-VHDL message is sent, the invoker suspends operation until the corresponding action (the operation) is complete. From the sender's point of view, sending a message has the semantics of calling a procedure. This differs from the hardware model of communication through signals, which requires specialized protocols to synchronize behaviors and to exchange data between components.
However, unlike procedure calls, a message only requests that a particular operation be performed -- it does not cause the operation to execute immediately. An EntityObject services messages sequentially. To enforce sequentially, OO-VHDL queues all message requests sent if an EntityObject is actively servicing another operation request. When the current operation is completed, the next request is removed from the queue and serviced.
Concurrence control is an important aspect of system-level design. However, signal-based concurrence control, such as bus-resolution, is at too low a level. Of the existing concurrence control approaches, the distributed processing model (similar to the remote procedure call model) and the Ada rendezvous are the most desirable for high-level behavioral modeling because of their ease of use and generality. OO-VHDL combines the distributed processing and Ada approach; this combination is referred to as DP/A in OO-VHDL.
3. Modeling Examples Prove Effectiveness of Object-Oriented Approach
To explore and test new OO-VHDL language constructs, Vista developed example system-level models written in tandem with the development of the language extensions. OO-VHDL models for the IEEE 802.4 Token Passing Bus Access Method for standard LANs, and ESPS, an example signal processing system, proved the power of object-oriented language constructs. These models demonstrated the effectiveness of OO-VHDL for rapid prototyping of system behavior that involves hardware/software interactions, and complex synchronization of concurrent hardware or software entities.
4. Language Standardization Effort
Standardization efforts are underway to add object-oriented features to VHDL in 1997 or sooner, if possible. An IEEE Design Automation Standards Committee group was formed for this purpose. The language and supporting tools will be made available free to users to generate valuable comments and suggestions.
5. The O-O VHDL Modeling Process
The pre-processor approach translates OO-VHDL models into VHDL 1076. It allows simulation tools used in the RASSP environment to be used for OO-VHDL simulation. This approach allows EntityObjects and VHDL components, including commercial, off-the-shelf components, to be freely mixed in any modeling situation. The OO-VHDL modeling process starts by generating the OO-VHDL models using a design entry tool. The modeler is provided with an extensive collection of OO-VHDL objects in an OO-VHDL design library that can be reused or extended in the object sense. The model is then converted into standard VHDL by the pre-processor and simulated. During simulation, the traceability tool allows users to track the simulation in terms of the original OO-VHDL model developed by the user.
The RASSP Digest - Vol. 2, No. 1, 1st. Qtr. 1995
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