The RASSP Digest - Vol. 2, No. 1, 1st. Qtr. 1995

Prime Development

Honeywell Develops VHDL Performance Model Library

by Fred Rose, Honeywell RASSP Technical Director


1. Introduction

The design and development of high performance computing systems is becoming increasingly complex. A primary ingredient of a sound design methodology is a detailed performance model of the system. A performance model expressed in VHDL serves as a simulatable specification, aids the identification of bottlenecks, and supports performance validation. It also allows trade-off studies for what-if analysis and documentation of design decisions. Honeywell Technology Center (HTC) has developed a library and a corresponding methodology for developing VHDL performance models. These models can be used for capturing and documenting architectural level designs, and for doing performance analysis studies of the architecture. HTC is significantly enhancing this library for the Martin Marietta RASSP team.

Performance modeling is applied during the early stages of system development. It provides another tool to the system designer but is not intended to be stand-alone nor discarded at the end of the system development stage. Performance modeling can aid evaluation of design alternatives, capture design decisions and assumptions, examine system behavior at boundary conditions, and help determine bottlenecks and overdesign. The system designer can also utilize performance modeling for examining system sizing, topology, partitioning and capability issues. An important benefit of performance modeling is that it provides early interaction of system, hardware, and software designers.

HTC has developed a generic, parameterizable library of VHDL performance models. This library consists of input/output devices, memories, bus communication elements, and a processor model. The processor model is the key element to the performance modeling methodology as it facilitates hardware/software codesign and coanalysis. The processor model has the capability of modeling software tasks and scheduling.

This VHDL performance environment allows the systems architect to capture the system under study in a consistent, verifiable form. The VHDL simulation produces metrics which can be used by any commercial analysis package, spreadsheet, or other appropriate format to aid the design decision process. The results can be directly compared with the system specification to verify that the architecture meets the performance requirements. Once the architecture is verified (the latency, utilization, and throughput meet requirements, the system is self consistent, and size, weight, and power limits are met), the system is ready to proceed to detailed design. The performance model can also produce the architecture's characterization for its use in a higher level model, where this design would just be another building block.

The primary focus of HTC's RASSP tasks for Martin Marietta are to help facilitate interoperability at the system design level by developing a VHDL performance model interoperability guideline, and to provide a robust library to achieve the system VHDL performance modeling.

2. Performance Model Interoperability

For the RASSP program to truly realize the full benefits of performance modeling, a common modeling approach is required. VHDL is the Lingua Franca, that is the language for doing business, of the EDA world. As the EDA industry increasingly moves to a “plug and play'' business model, a common language becomes essential. However in addition to a common language, common usage or style is required. This has been recognized from the beginning in the VHDL community and a variety of style related standardization activities have occurred. However, to date, these efforts have focused on lower levels of design abstraction. The performance model interoperability guideline will raise that level of abstraction.

It is critical that the performance models interoperate with the tools used to specify and capture the RASSP requirements and system design information. The interoperability guideline defines how Honeywell's performance model library will function with other elements of the RASSP environment. Honeywell will work with the primary architecture-level tool vendors, including JRS, Vista, and Omniview, on the Martin Marietta team, and additionally Lockheed-Sanders and the University of Virginia to establish interoperability with their tools and VHDL performance models. This interoperability guideline is meant to be a consensus opinion on VHDL performance modeling interoperability. Because Honeywell has a role on the Martin team to develop and support VHDL performance models, this document is initially heavily weighted towards that role. Hopefully as this technology becomes more widespread throughout the RASSP community, the interoperability guideline will become more generic.

The interoperability guideline consists of the following sections:

3. Model Development

The VHDL performance modeling methodology is targeted towards high level description, specification and performance analysis of computing systems. The tools and techniques themselves are not targeted towards any particular application. The level at which is appropriate to apply these tools is at the architectural level. Architectural level includes the actual device or entity under study such as a signal processor, and its environment, such as sensors and actuators. In the case of an electronics system, an architectural level description would include information about both the hardware and software. Note that the definition of "system" is loose here. While the application of performance models is constrained to electronic systems, the library should be fully capable of representing systems consisting of ASICs, boards, and subsystem cabinets, and sensor networks.

Regarding model capability, the two modeling/simulation areas which the existing HTC current performance models did not address well were large multiprocessor systems and signal and image processing application specific models. Since the application specific models are best addressed on a case by case basis, HTC is directing our activity to the multiprocessor modeling area.

The prior HTC modeling capability concentrated on small scale multiprocessing systems. As a result, the processor model developed into a powerful, highly flexible generic model. Communication models on the other hand have been limited to processor-memory bus models with rudimentary arbitration schemes.

The proposed modeling capability will include an efficient "light weight" processor models as well as a generic interprocessor communication models. Multiprocessor systems will require more elaborate communication models capable of more advanced protocols and arbitration mechanisms. Scalable point to point communication models capable of supporting several different protocols are needed to model large multiprocessor designs.

4. Related Contracts

Under a separate RASSP technology base contract, Omniview, in conjunction with HTC, will develop commercial quality product called the Performance Modeling Workbench (PMW). The PMW will provide an extensive graphical user interface for performance models. The performance models, based on the HTC VHDL performance model library, will adhere to the requirements specified in the interoperability guideline. The PMW will also include multi-processor modeling tools such as output analysis, capture, route/message cost, and architecture visualization.

Lastly, the performance models will be constructed in a manner to support hybrid modeling. Hybrid modeling supports performance analysis with interfaces to functional models of communication and other device models. Functional modeling of selected system components will be necessary. A good example of this is the detailed functional modeling of the underlying communication mechanisms. Under a RASSP technology base contract, Honeywell, along with the University of Virginia, will develop models and utilities to support hybrid modeling.
The RASSP Digest - Vol. 2, No. 1, 1st. Qtr. 1995

newsletter/html/95q1/news_5.html