The RASSP Digest - Vol. 2, No. 1, 1st. Qtr. 1995
Editor's Corner
Editorial Viewpoint
by Anthony J. Gadient
One of the most important factors contributing to the dramatic reduction in development time provided by the RASSP program is the effective use of the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). For this reason, we have chosen to focus on the RASSP VHDL activities in this edition of the RASSP Newsletter.
One of the activities being undertaken by RASSP which will contribute significantly to the effective use of VHDL in top-down system-level design is the development of a "taxonomy" of VHDL models. Many of you might wonder what the benefit of this activity will be and why it is being undertaken. This editorial is aimed at addressing this question by explaining the benefits a formal taxonomy of VHDL models will provide to the RASSP and VHDL user communities.
The RASSP design methodology and a VHDL taxonomy are like the ‘yin’ and the ‘yang,’ highly interrelated concepts, each inseparable from the other. To understand the importance of one, it is necessary to understand the other. Therefore, to explain the utility of a VHDL taxonomy it is first necessary to examine what a design methodology is.
A design methodology may be characterized as a directed, cyclic graph where cycles represent the iterative define-analyze-refine process that distinguishes design from other activities. For this reason, many work flow management systems use directed graphs as a way to present work flows (or design methodologies) to the end-user. Given this characterization of a design methodology, one can think of the nodes of the graph as representing design activities which often involve the invocation of design tools. Edges may be thought of as representing the flow of information and control from one design activity to the next. It is here that the idea of a VHDL taxonomy and that of a design methodology merge.
The purpose of a VHDL taxonomy is to provide a way of characterizing VHDL models in terms of a set of attributes and attribute values so that one can relate edges (information flow) to VHDL models that may either be produced by a design activity or obtained from a design reuse library. For this reason, the successful development of a VHDL taxonomy requires many things to be understood, for example:
a) Where does a particular type of model fit in the design process?
b) What design risks are reduced through a particular type of model's use?
c) What are the benefits /costs associated with the use of a particular type of model, for example, what errors will it detect, how much development and execution time are required, and so forth?
Many schemes have been developed to help us organize and think about the design process; most recognized amongst these is the Gajski-Kuhn Y-chart. In the VHDL community the Ecker-cube has obtained considerable attention. The VHDL taxonomy activity being undertaken by the RASSP program is building upon these earlier efforts. The attributes and attribute values that are used to characterize a VHDL model lie at the heart of this activity. Ideally, this set of attributes would possess two properties:
Property 1: It would be desirable if two VHDL models that differ in at least one attribute value would be used by different activities in the design process or be used by one design activity for distinctly different reasons.
Property 2: It would be desirable if a model could be automatically categorized by automatically determining its attribute-values.
The first property would support RASSP's drive to reduce development time by a factor of four by facilitating VHDL model reuse and model interoperability. Theoretically, the first property ensures that an isomorphism exists between the design methodology and the VHDL taxonomy. This fact ensures that a VHDL reuse library can be organized so that designers working on a particular activity can easily obtain VHDL models that are potentially relevant to what they are working on by requesting models with certain attribute values. For instance, a designer that is developing the architecture for an embedded system is interested in quickly and easily identifying where bottlenecks for a particular architecture exist and performing "what-if" analysis until a well-balanced system architecture that meets the cost and form-fit-function constraints of the system is identified. In this process, access to VHDL models that possess certain qualities that can be used to help evaluate evaluate the system’s performance is required. Today, such models are often referred to as "Performance Models."
So, you might ask, why bother with a taxonomy (determining a set of attributes and attribute values for characterizing different types of models). Why not, for instance, just call performance models, "performance models," and when a designer needs performance models he requests "Performance Models" from the reuse library. Unfortunately, the simple solution implied by this question may not be appropriate. Given the term "Performance Model," different individuals are likely to have different understandings of what a performance model is. As Fred Rose from Honeywell Technology Center writes, "As the EDA industry increasingly moves to a ‘plug and play’ business model, a common language or ‘lingua franca’ is essential. But more than a common language is required; common usage or style is also required." In essence, the intent of this common style is to ensure that models of a certain type possess certain characteristics or attributes. By developing a taxonomy that identifies the appropriate set of attributes for characterizing VHDL models and identifies the attribute values a particular model type should possess, the taxonomy provides a more rigorous definition for a model type than a simple name. This rigor also enhances the interoperability between two different models of the same type by ensuring that each model of a certain type exhibit a shared set of characteristics. Model interoperability and therefore “plug and play” can be further enhanced by adherence to Property 2.
By satisfying Property 2, the taxonomy can provide the basis for automating the process of determining whether a given model adheres to some modeling style or not. Because the development of modeling guidelines is the approach being taken within the VHDL community to address the model interoperability or "plug and play” issue, automatically determining whether a given model satisfies a style's requirements can provide significant benefit to the RASSP community.
However, defining a taxonomy for VHDL models that satisfies this second property is a significant undertaking because it requires the taxonomy to be formally specified, for it is only through a formal machine processable definition that Property 2 can be realized.
The RASSP Program's efforts to develop a taxonomy for VHDL models is one of the critical elements being addressed by RASSP that will enable effective top-down system level design with VHDL. The development of a VHDL model taxonomy will contribute to the widespread usability of system level VHDL models and provide the basis for sharing hardware design knowledge in the form of reusable VHDL libraries. A great deal of excellent work has already been done in this area by Dr. Harr of ARPA, Prof. Madisetti of Georgia Tech, Carl Hein of Martin Marietta, Paul (Kassey) Kalutkiewicz of Lockheed Sanders and a score of others too numerous to name. However, a great deal remains undone. As Winston Churchill once said, "...this is not the end. It is not even the beginning of the end. But it is, perhaps, the end of the beginning." So it is with RASSP's efforts to define the conceptual structure for organizing VHDL models by defining a VHDL taxonomy.
The RASSP Digest - Vol. 2, No. 1, 1st. Qtr. 1995
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