The RASSP Digest
The Lockheed Sanders Demonstration Program
LeRoy Fisher
Hughes
The goal of the RASSP Demonstration effort is to provide validation of the RASSP Process and RASSP Design Environment in the context of real-world signal processor design. Over the course of the RASSP Program, three full releases of the RASSP Design Environment (RDE) will be used, along with corresponding releases of the RASSP Process. Each release of the RDE will be utilized in the development of model year upgrades to the demonstration vehicle. Model Year 0 work has been performed largely with tools from the RDE tool set. New RDE integration and infrastructure capabilities are being used as they become available. Figure 2 illustrates the close relationship between the three primary RASSP efforts - Process Development, Design Environment Development and Demonstration.
The objectives of the RASSP demonstrations are to:
- 1) Use an embedded signal processing system as a test case, spanning the development cycle from concept to specification, architecture analysis, design, manufacture and support, so that the entire RASSP process can be evaluated as it evolves during the contract.
- 2) Design the system using the RASSP model year concept - the ability to upgrade system design rapidly and often, incorporating the latest technology and incrementally upgrading the system throughout its life cycle.
- 3) Provide process metrics and lessons-learned for methodology and process refinement. Measure the progress toward reducing product development time by a factor of four.
- 4) Provide feedback on the usefulness of specific tools and the design environment.
- 5) Provide clear, convincing data that the RASSP methodology is practical and effective for complex design tasks.
By demonstrating the process and tools as they are being defined, the program becomes much more than an esoteric study. The demonstration helps focus and prioritize development. It also checks the usefulness of the tools early in the development cycle. Adequate design complexity ensures that the process and tools are viable in real-world examples. Because requirement definition is real, there is no opportunity to gloss over details, as might be possible for a simple laboratory demonstration. A tangible demonstration also provides an understandable scope of work for which metrics can be collected and improvements in the RASSP process explained. Metrics gathered across multiple years clearly show that the design process has improved.
Demonstration Vehicle
The demonstration vehicle for RASSP is an airborne infrared search and track (IRST) processing system using programmable processors. It employs a heterogeneous Multiple Instruction Multiple Data (MIMD) architecture using commercial off the shelf (COTS) processor chips, operating systems, and system software tools. The IRST processor was chosen as the preferred demonstration for several reasons:
- 1) Scalability. The IRST algorithms were available in a scalable manner for a coarse grain MIMD parallel processor. Coarse grain in this sense is a non-shared memory, message passing architecture. The available software design and initial partitioning provided a starting point for showing model year improvement and demonstrating reuse. By starting from this well-thought-out design, a more complex system demonstration can be achieved.
- 2) Modularity. The IRST algorithms and software are modular to allow RASSP process exploration to be performed at different levels of rigor for different functions. This modularity allows the scope of the demonstration to be adjusted to meet RASSP needs and schedule.
- 3) Tools. Some of the algorithms are described at the math level in Matlab, one of the RASSP analysis tools, thus allowing a top-down exploration of hardware/software partitioning and design.
- 4) Ease of implementation. Some of the existing algorithms easily lend themselves to hardware implementation (e.g., convolution and registration). Also, test imagery is available.
- 5) Applicability. IRST processing has received much recent interest as a means to meet airborne and ship defense requirements. Thus its demonstration should be of interest to multiple potential Government organizations. Ideally, these organizations can start with the RASSP demonstration databases, apply the RASSP process, and create their own IRST solution tailored to specific application requirements.
Demonstration Model Year 0 concludes with the construction of a complete IRST processing system. Algorithms and some C software were available at the beginning of the Model Year 0 effort. The architecture, interface cards, processor, and Ada software are the design elements for this first model year. The design uses standard buses and interfaces, such as VME, RS-170, and RS-422. The system will have about 20,000 lines of application code and about 24,000 lines of VHDL code.

The RASSP Digest - Vol. 1, No. 1, 4th Qtr. 1994
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