The RASSP Digest

Martin Marietta RASSP Design Center Enables Design Environment Implementation

Martin Marietta's RASSP design center provides a facility for the team to implement the integrated RASSP design environment. The RASSP design environment is important because it enables a significant portion of the 4X improvement in development schedule and 4X reduction in life-cycle cost.

The RASSP design center at Martin Marietta Laboratories in Moorestown has a 30-Gigabyte data server and 10 Sun Microsystems' Sparc 10 workstations dedicated to RASSP. The team plans annual hardware enhancements using Martin Marietta capital. These workstations are networked into the Moorestown Laboratories' resources. Martin Marietta plans to connect to the outside world in early 1995 using EINet from MCC to provide flexible and secure on-demand connectivity.

Martin Marietta's design environment implementation team leveraged the heritage of its Engineering Process Improvement (EPI) program to combine an already integrated set of CAD tools with additional DSP analysis tools to implement its Baseline 0 design environment. Martin Marietta has now defined a set of 46 tools from 26 vendors. Intergraph will provide a framework to integrate all tools and automate process and workflow control. These tools are fully described in Martin Marietta's "CAD System Description" document. The tools are organized according to their use within the RASSP design methodology.

The tools for the systems, architecture, and detailed design (hardware and software) areas are summarized in the following paragraphs.

System Design tools support early development of system partitioning, test, reliability, and maintenance concepts.

RTM by Marconi System Technology enables life-cycle requirement traceability

PRICE S/M/H/HL by Martin Marietta for computer-aided parametric cost estimating enables life-cycle cost analysis throughout the design process

RAM/ILS by Management Sciences Inc. enables feedback on reliability, availability, maintainability, and integrated logistics support during early trade-off analyses

RDD-100 by Ascent Logic enables system definition, functional analysis, function allocation, interface design, scenario development, and thread analysis

TPS by Interleaf provides a complete document publishing tool

RRDM by Aspect will provide access to reuse data and libraries

Architecture Design tools help analyze architecture and hardware/software codesign in a variety of ways: functional analysis, trade-off studies for architecture selection, partitioning/mapping, and architecture verification.

NetSyn by JRS Research Laboratories enables multiprocessor design analysis and synthesis to support architectural trade-offs

SPW by Alta Group of Cadence enables interactive design, simulation, and implementation of digital signal processing and communication systems

BONeS by Alta Group of Cadence performs detailed, discrete architectural simulation and is used to obtain high-fidelity performance metrics early in the system design

MatLab by Mathworks provides advanced image processing functionality and numeric computation

Ptolemy by BDTI/UC Berkeley supports multi-domain analysis of complex systems

GEDAE by Martin Marietta provides a software front-end for hardware testbeds that enables graph-based programming and front-end analysis of multiprocessor trade-offs

ADEPT by University of Virginia provides a unified VHDL environment to support hardware/software codesign and trade-offs

Hardware Design tools support seamless coupling from the higher level architectural requirements, hardware/software codesign, and behavioral tools down to the functional and detailed-level hardware design processes.

Design Architect by Mentor Graphics captures designs at the architectural, logic, and circuit levels for top-down design

QuickVHDL by Mentor Graphics creates, debugs, and simulates VHDL models

QuickPath by Mentor Graphics provides static path analysis

QuickFault by Mentor Graphics provides deterministic fault-simulation

MCM Station by Mentor Graphics provides layout, thermal analysis, and signal integrity analysis of MCMs or PWBs

DesignVision by Vista graphically represents behavior for modeling VHDL, viewing simulation results, and documentation

SimMatrix by Precedence provides a simulation backplane to support interactive co-simulation

FIDELITY by Omniview allows designers to rapidly synthesize and evaluate alternative hardware architectures

VPS by Quickturn Design Systems enables hardware emulations

SmartModels by LMG group of Synopsys provides full and bus functional simulation libraries for a large number of COTS parts

Design Compiler by Synopsys enables high-level design synthesis of ASICS

C-MDE from LSILogic enables ASIC development

FPGA Foundary from Neocad supports FPGA development

Lasar by Teradyne provides dynamic min/max timing path analysis

Victory by Teradyne provides test analysis

Software Design tools support library development, detailed design, and source code development. Martin Marietta will be adding more software tools soon.

Teamwork by Cadre Technologies provides structured design analysis and documentation in support of software development

Sun ADA by Sun Microsystems supports HOL source code development in the workstation environment; target-specific HOL compilers are being installed to support emerging DSP chips

CDEM will be provided by AT&T to support distributed software debugging capabilities for multiprocessor systems

PIE and TIBBIT by University of Oregon will provide a performance analysis and a binary-to-binary software translation capabilities

GrTT and mPIDgen by Management Communications and Control Inc. will provide autocode generation and run-time system for graph execution control