The Rapid Prototyping of Application Specific Signal Processors (RASSP) program is a major ARPA/TriService initiative to reinvent the design process for embedded digital signal processors. Our goal is to improve the time it takes to go from concept to fielded prototype on both new designs and upgrades by a factor of four, with similar improvements in life cycle cost and supportability.
RASSP is aimed at the whole system design process, from specification to manufacture. The program emphasizes complex digital systems at the board and multiboard levels. Consequently, it spans heterogeneous systems involving mixes of standard and custom hardware, field programmable devices, and software on programmable processors.
At this writing, the RASSP program is one year into the four year span of the primary development programs which are the core of the program. What has been accomplished in the first year?
Programmatically, the ARPA/TriService team has finished the major undertaking of building the RASSP team and ramping the program up to full speed. RASSP now involves some twentyfive contracts in four general areas. Lockheed Sanders (Nashua, NH) and the Martin Marietta Advanced Technology Laboratory (Moorestown, NJ) each are developing and demonstrating complete RASSP design systems. They are supported by a technology base development effort involving a large number of universities, notforprofit, and commercial firms performing research and development in digital signal processing and electronic design automation. RASSP also includes innovative Education and Facilitation (E&F) and benchmarking efforts, both new experiments in ARPA programs. Current design metrics emphasize evaluation of point tools. The RASSP benchmarking effort will develop systemlevel benchmark design problems and process metrics, and share RASSP design experience with the larger community. The E&F will ensure that RASSP design concepts and experience are widely disseminated to the larger end user, commercial EDA, and educational communities.
Technically, RASSP efforts are focused in three general areas: design process methodology, digital signal processor architecture, and electronic design infrastructure which includes EDA tools, libraries, and enterprise integration capabilities. While progress has been made in all three, I would like to concentrate on the first and third areas.
A good design system should be driven by methodology, tempered by available tools and other infrastructure. The RASSP program is emphasizing development of a concurrent systems engineering methodology. Both Lockheed and Martin have defined first versions of a RASSP design process that includes a highly integrated functional design process (meaning the process of translating requirements into functional specifications and constraints, and then mapping those specifications into a hardware/software architecture optimized under the constraints), augmented with concurrent engineering capabilities such as early cost estimation, producibility assessment and so forth. A number of successes have been achieved in linking tools for DSP algorithm development to tools for system simulation and hardware/software codesign. The RASSP Program is also exploring the limits of VHDL as a language for system representation across many levels of abstraction, from executable specifications to behavioral and RTLlevel designs suitable for synthesis, to gate level design documentation. This effort has made substantial progress and is also illuminating many practical problems, from simulation speed to library population. The latter point brings us to the area of design infrastructure.
The RASSP program has invested in its first year in a number of efforts to help populate VHDL part libraries, ranging from direct development of models to efforts to commercialize model generation tools. One of the most visible signs of our early progress will be the announcement in 1995 of a number of new or accelerated EDA products and enhancements directly attributable to these RASSP efforts.
RASSP faces a number of near term challenges. Before a second year elapses, the developers must integrate the first version of a comprehensive design system. The first benchmarking results will become available, and are certain to include many lessons about what is and isn't working in the RASSP methodology. Virtual prototypes of each developer's demonstration projects will be completed, providing another test of the early methodology and tools. Finally, we must also begin to make progress in our efforts to explore DSP architectural structures which inherently support rapid design.
While the RASSP program is now up to full speed, opportunities still exist to work with us to meet the goal of dramatically improving embedded DSP design. The ARPA/Tri-Service team remains interested in partnering with end users on additional demonstration projects. And of course, we are always interested in hearing of good new technical ideas applicable to the RASSP program.
The RASSP Education and Facilitation team is there to help you learn more about RASSP. This newsletter contains a great deal of information about all aspects of the program. To learn still more, I encourage you to log into the RASSP World Wide Web server at http://rassp.scra.org/, or contact the RASSP E&F team directly. And be sure to join us for the Second Annual RASSP Conference next Summer!
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