The RASSP Program: Overview and Accomplishments
M. A. Richards, ARPA
RASSP: Viewpoint from a Prime Developer
W. R. Hood, C. Myers, Lockheed Sanders, Inc.
Martin Marieta RASSP Program Overview
J. Saultz, Martin Marietta Laboratories
RASSP Benchmark Program Overview
G. A. Shaw, M.I.T. Lincoln Laboratory
RASSP Education and Facilitation
J. Corley et al, SCRA
RASSP Technology Base R&D Overview
J. Hines, D. Barker, Wright Laboratory
VHDL Performance Modeling
F. Rose, T. Steeves, T. Carpenter, Honeywell Technology Center
RASSP Methodology Overview
J. Pridmore, W. Schaming, Martin Marietta Laboratories
Processes and Experiences in VHDL Top-Down Design
R. Dreiling, Lockheed Sanders
VHDL Executable Requirements
A. H. Anderson, G. A. Shaw, C. T. Sung, M.I.T. Lincoln Laboratory
Test Bench Development for RASSP DSP Models
J. Armstrong, Virginia Tech; G. Franck, Research Triangle Institute
Design and Simulation of Heterogenous Systems using Ptolemy
B. Evans, A. Kamas, E. Lee, University of California at Berkeley
CAD Tool Interoperability Through Standards
D. Cottrell, J. Teets, CAD Framework Initiative
ADEPT: A Unified System Level Modeling Design Environment
S. Kumar et al, University of Virginia
Board and MCM Level Synthesis for Embedded Systems: The COMET Co-synthesis Environment
R. Vermuri, H. Carter, P. Alexander, University of Cincinnati
Applications of a Formal Model of VHDL
D. Benz, X. Fan, P. Wilsey, University of Cincinnati
Algorithms for Signal Processing
A. V. Oppenheim et al, Massachusetts Institute of Technology
VLSI Discrete Wavelet Transform Architectures
K.K. Parhi and T. C. Denk, University of Minnesota
Adapting Algorithms to Architectures Through Transformations
G. Frank, B. Clark, W. Ransdell, Research Triangle Institute
Overview of the RACE Hardware and Software Architecture
B. Isenstein, Mercury Computer Systems Inc., B. Kuszmaul, Massachusetts Institute of Technology
Estimating the Requirements of Signal Processing Algorithms
B. Friedlander, University of California at Davis