The RASSP Digest

VHDL Models

In this month's Tech Base column we will present the efforts taking place to create VHDL models for RASSP. Future columns will present Tech Base efforts in other areas such as simulation, synthesis, and translation tools; analysis algorithms and tools; and enterprise integration.

The information below generally describes the nature of the models being created and how they fit into the RASSP program. A later issue of The RASSP Digest will provide more detailed information about each model and how they can be obtained from the RASSP repository.

VHDL Hybrid Models

Hybrid models will allow the RASSP designer to seamlessly use multiple abstraction levels within the same simulation. This program will develop models and utilities to support hybrid modeling. VHDL is being used to model designs from early algorithmic and performance levels to behavior to detailed gate design. The primary advantage for using VHDL throughout the design cycle is keeping the design in the same representation throughout. The expressive power of VHDL is well suited to this task. However, unless techniques which allow seamless integration of these multiple levels are developed, this great advantage of VHDL will be lost. Individual tools and design representations will continue to be used, maintaining the current disarray and confusion in the industry for system level design. While the tailored RASSP VHDL DID calls out multiple VHDL levels, no technique exists to integrate these multiple models. In many cases, unrelated tools will be used and VHDL will merely be an output format ,almost an afterthought. Unless a clean, straightforward technique is developed, this will be true on the RASSP program.

The complexity of model integration comes from different information content and format for the different model levels. Performance models use a token (VHDL record structure) as a signal which contains no detailed data information. Behavioral models use integer and real signal structures which contain detailed data information. Register transfer level models use bit level signal structures, such as the IEEE 1164 9state logic system, which also contain detailed data information. Each of these levels also handle timing differently.

There are multiple reasons to mix levels. One may not have detailed design information for a particular block and may be forced to abstract the behavior. One may want to develop a detailed design for another block. Simulation performance may not be satisfactory with detailed models at all levels. Detailed models are used to verify timing assumptions made earlier. Software analysis may be desired but a detailed hardware processor model may not be available or may be too slow. These are all commonplace design occurrences.

Performance Modeling Workbench

The Performance Modeling Workbench (PMW) will be a fully integrated VHDL environment for systemlevel hardware/software codesign and performance analysis. PMW will minimize the "upfront" model generation penalty through a comprehensive library of parameterized VHDL hardware and software models that allow the system designer to quickly generate and evaluate alternate architectures early in the system design process. A powerful, comprehensive results analysis package will allow the designer to compare and verify performance at each stage with previous results and the system requirements. Since all models are in VHDL, each stage of the design process is documented in a standardized, consistent, and verifiable form. The PMW will be based on the existing Honeywell performance modeling library.

VHDL Modeling of Architectural Building Blocks

The objective of this effort is the creation of a library of synthesizable (and simulatable, of course) common building block components that can be used to quickly design and implement a DSP or an SIC for use with a DSP. The library and associated documentation will provide a "data book" of reusable components with information on the use of the model for simulation and synthesis. Models with appropriate variations will be generated under the effort for fixed point integer units including adders, multipliers, linear shifters, and barrel shift/rotate units; and floating point units including single, double, and extended precision floating point adders, floating point multipliers, and transcendental function units.

VHDL Modeling of Cypress Semiconductor Standard Parts

The objective of this effort is to develop VHDL models of selected Cypress Semiconductor standard integrated circuits. Mississippi State and Cypress have entered an agreement where by Cypress will provide timing information necessary to create VHDL models of high quality and accuracy to be released as part of the RASSP program.

Several critical part types will be modeled to develop a baseline VHDL model library of standard parts. Advanced PLDs, FPGA, FIFO, and Dual Port memories are the part types under investigation. A meeting is scheduled between Cypress and MSU for later in the Fall to determine the first part to be modeled and the modeling support information which will be provided to MSU by Cypress.

MSU will also be releasing two VHDL modeling support tools as part of the RASSP contract. The first is TestView which is an automatic VHDL testbench synthesizer. TestView allows users to develop custom VHDL testbenches for the model under test (MUT) which are portable to any IEEE-1076 simulator. ConfigView provides a graphical user interface to VHDL configurations. ConfigView allows large configurations to be easily edited to customize simulation executions. Each of these programs will be released as MOTIF and Sun Microsystems COSI applications. Beta release for TestView is scheduled for 2nd quarter 1995. ConfigView Beta release will follow in 3rd quarter 1995.

CAD Tools for the Development and Reuse of Models of Signal Processing Software and Hardware

Besides developing software partitioning and VHDL test bench generator tools, RTI and VPI will be developing a signal processing algorithm library and a VHDL module library. The capabilities of these algorithms and modules will be analyzed, refined, and demonstrated. Furthermore, these algorithms and VHDL models will be interfaced to the tools in the RASSP design environment.

Populating VHDL Libraries for RASSP

This project will develop libraries of VHDL models for digital electronic macrocells, components, sub-systems and systems. The end product will be an extensive library that includes commercial-off-the-shelf (COTS) parts, digital signal processors (DSP) , a VHDL math library, and tools to aid in the generation, maintenance and standardization of VHDL libraries for RASSP. Our VHDL models for i860 and VME are being used extensively by the RASSP primes in their virtual prototyping demonstrations (which were also presented at the RASSP workshop in 1994), and models for the ADSP 21060 (SHARC,) PowerPC, TMS320C30, and other COTS and DSP chips are currently in development. All models are being collected into a respository for rapid dissemination, once they are validated and released. Technical point of contact: Dr. Vijay K. Madisetti, (404) 853-9830, email: vkm@ee.gatech.edu.