Lockheed Martin Advanced Technology Laboratories'
RASSP Documents
Application of DFT to RASSP Benchmark 3R. J. TarzaiskiAbstractDetailed application of the RASSP Methodology to the Benchmark 3 systems as part of a non-interfering shadow program. Develops TSDs, a singular test philosophy, and describes a test means evalustion. Also describes the role of dependency modeling in high level system analysis. Application of Ontology-Based Knowledge Representation to Design ReuseElisa Finnie, Eric Lai, Robert Engelmore, Adam Farquhar and Richard FikesAbstractOntolingua, a language for ontology-based knowledge representation, provides the capability to construct comprehensive characterizations of knowledge bases. While the ability to characterize the content of a knowledge base is not new, Ontolingua includes a number of features that greatly enhance conventional data representation and modeling technologies through the incorporation of semantic context. In addition to supporting object-oriented modeling techniques, Ontolingua enables representation of constraints, definitions, and relationships among terms within ontologies. This facility provides a framework that supports automated translation among knowledge bases with differing data models and physical implementations. The ability to formally describe and unambiguously distinguish between diverse data sources is essential to enabling reuse of intellectual property. This paper presents a high-level view of ontology-based knowledge representation and an approach to solving the intellectual property reuse problem through the application of this technology. CAD System DescriptionLockheed Martin Advanced Technology LaboratoriesAbstractLockheed Martin ATL's design environment implementation team has leveraged the heritage of its Engineering Process Improvement (EPI) program to combine a proven set of tools with extended capabilities for Baseline 0. Enhancements have been made in tool integration, functionality, and performance in the CAD system for Baseline 1. Intergraph will provide a framework to integrate all tools and automate process and workflow control. An updated description of the Baseline 1 tools is the focus of this document and is referred to as Baseline 2. The tools are organized according to their use within the RASSP design methodology. Common Models for Configuration Management and Authorization Management in Systems Engineering EnvironmentsBiju Kalathil and John WelshAbstractIn an integrated product development environment that includes several vendor tools, diverse and incompatible configuration management mechanisms and authorization management mechanisms across tools can lead to inefficiencies in the design process. We describe in this document a common model of configuration management and authorization that may be adopted for an integrated product development environment. We specified a common minimal set of configuration management mechanisms and authorization management mechanisms that must be provided by the tools to support the proposed configuration and authorization models. We implemented a pilot program of the configuration management and authorization management models using Intergraph Corporation's Document Manager 2.0 (DM2) software system. This pilot implementation proves the plausibility and usability of the model. Component, Duplicate Components, Cost, and RMA Attributes ReportAbstractThis document reports the attributes of Component, Duplicate Components, Cost, and RMA. The Configuration Management Model for the RASSP System - Version 2Biju KalathilAbstractThis document describes a common model of configuration management that may be adopted by the RASSP enterprise framework tools and the CAD tools. This model provides for the management of the various versions of the design objects that are created and manipulated during the process of the design of a product. The model does not cater to the version management of reusable library components that are created outside of the design process. The Configuration Management Model for the RASSP System - Version 3Biju Kalathil and D. BlanchardAbstractThis document describes a common model of configuration management that may be adopted by the RASSP enterprise framework tools and the CAD tools. This model provides for the management of the various versions of the design objects that are created and manipulated during the process of the design of a product. The model does not cater to the version management of reusable library components that are created outside of the design process. Design For Test Methodology Applied Across Design and Support CyclesR. J. Tarzaiski and S. SharmaAbstractA complete description of the results of the LM DFT methodology presented at the Program Review of November, 1996. The presentation was repeatedly given during operation of a display booth where all RASSP achievements were highlighted. Design For Test Methodology Applied Across Design and Support Cycles TutorialR. J. Tarzaiski and S. SharmaAbstractTutorial steps for application of DFT Methodology, including test strategy diagrams (TSDs). Part of a training session for prospective users of the Methodology. Domain Independent Reuse MethodologyLockheed MartinAbstractThe purpose of this document is to provide a record of the RASSP Domain Independent Methodology Development Activity. The purpose of this activity is to provide an overall reuse methodology that is independent of the domain that it is resident. EVALUATION: BEACON Product Family for Signal Processing Command Program GenerationC. FickleAbstractThe Beacon Product Family is a reasonably mature tool set that can successfully be used to graphically model and autocode generate Ada-83 source code for signal processing command programs whose primary function is to control graph execution and configuration variables. The tool should be thought of as a detailed design/code tool that allows software programmers to program graphically. The code generated is extraordinarily clear and is comparable to hand written code in terms of clarity and efficiency. The graphics are similar too traditional flowcharts and thus closely reflect the generated source code. The tool does not support Ada packages (generated procedures are treated as separates) nor does it support the broad Ada typing, strings, tasking, or exceptions. The product includes the ability to generate procedure level test cases, which has not been evaluated here, and the potential for integration with signal processing graph tools to facilitate the rapid development of command programs. Evaluation: MATRIX X Product Family for Signal Processing Command Program GenerationC. FickleAbstractThe MATRIX X Product Family is a mature tool set that can successfully be used to graphically model and autocode generate Ada source code for signal processing command programs whose primary function is to control graph execution and configuration variables. The code generated is not comparable to hand written code in terms of clarity or efficiency, but is adequate for real-time applications that are not severely CPU or Memory constrained. Conversion between the limited set of model data types and the extensive set of Ada data types provides a source of potential errors during both program creation and program maintenance. The product has the potential to be tailored into a stand alone command program simulation environment and the potential for integration with signal processing graph tools to facilitate the rapid development of command programs. Hardware Synthesis Study of WSSPT SVI Interface Encapsulations Application NotesGreg BuchananAbstractThe purpose of the initial SVI synthesis study was twofold: first, to gain experience in writing synthesizable VHDL code for SVI encapsulations, and second, to gain a better understanding of the hardware overhead introduced by a typical interconnect fabric encapsulation. The lessons learned from the experience of creating optimized synthesizable VHDL code have been documented as coding guidelines in Standard Virtual Interface Specification, Version 0.5. The results pertaining to the hardware overhead introduced by SVI encapsulation are the subject of this memo. A Hierarchical, Design-for-Testability Methodology for the Rapid Prototyping of Application Specific Signal ProcessorsJohn Evans and Richard SedmakAbstractThis paper describes a design for testability process, which is highly automated, hierarchical, and spans the entire life cycle. The process was developed for the DoD's RASSP Program and contributes significantly to the RASSP goals of 4x improvement in cycle time, design quality, and life cycle costs. Information Brokers: Gathering Information from Heterogeneous Information SourcesRichard Fikes, Adam Farquhar, Wanda PrattAbstractThe Internet provides dramatic new opportunities for gathering information from multiple, distributed, heterogeneous in-formation sources. However, this distributed environment poses difficult technical problems for the information-seeking client, including finding the information sources relevant to an interest, formulating questions in the terms that the sources understand, interpreting the retrieved information, and assembling the information retrieved from several sources into a coherent answer. In this paper, we describe techniques that will enable vendors and buyers to build and maintain network-based information brokers capable of retrieving information about services and products via the Internet from multiple vendor catalogs and data bases for both human and computer-based clients. Interface Definition Specification for the Benchmark 1 SARRASSP Project USAAbstractThis document applies to the firmware and hardware interfaces for the Benchmark 1 SAR Signal Processor. Intermediate Solution to the Mentor Graphics - Metaphase InterfaceAbstractUntil the RASSP Enterprise Framework (EF) can be upgraded to the Metaphase 2.2, which will incorporate the use of the Mentor Graphics Interface, an intermediate solution has been implemented which will allow users of the EF to create, register, and check in/out large Mentor Graphics Datasets. This solution will automate the required actions which are necessary for moving MGC Datasets on a UNIX file system. The information below outlines those steps. Library RequirementsAbstractThis document represents the composite of the Library Management Model for RASSP -Version 2.0 [LM-ATL, 1995a], the RASSP Reuse Data Manager (RRDM) and Reuse Strategy Requirements Specification (Draft) [Aspect, 1995a], the RASSP Reuse Library Integration Strategy [Aspect, 1995b], the RASSP Reuse Data Manager (RRDM) and Reuse Strategy Implementation Plan (Draft) [Aspect, 1995c], the reuse section of the RASSP Interim Report [LM-ATL, 1995b], and subsequent research in design reuse. Unlike the documents that preceded it, this methodology is intended to be library management tool-independent. Although the requirements documented herein are focused on the RASSP digital signal processor domain, it is hoped that the overall approach applies to library management for a much broader spectrum of engineering design and test environments. Metadata Interchange Specification (MDIS) Version 1.1Abstract
To enable full-scale enterprise data management, different IT tools must be able to freely
and easily access, update, and share metadata. The only viable mechanism to enable
disparate tools from different vendors to exchange metadata is a common metadata
interchange specification with guidelines to which the different vendors tools can comply.
Misc Enterprise Software Documentation (11/95)John J. WelshAbstractThis text describes custom developments / commands developed for the enterprise framework. A Model Driven Methodology for Business Process EngineeringASME Computers in Engineering Conf. Engineering Database Program, 95Bipin ChadhaAbstractHaving competitive processes has become as important (if not more) as having competitive products. Simply designing good products is not enough to gain competitive edge. Business processes have grown complex and fragmented in an ad-hoc manner. They span several departments and are very inefficient. Often the work being performed conflicts with the organizations' goals and strategic objectives. Traditional practices and policies tend to encourage this, resulting in being part of the problem instead of being part of the solution. This paper presents a model driven methodology for Business Process Engineering (BPE) to support an organization's migration to effective, agile and efficient processes. The essential elements of the methodology are process modeling, process analysis, and process execution by utilizing an array of information technologies. The methodology steps depend on process models for understanding, analyzing, simulating, improving, innovating, and implementing the business processes. The methodology starts by defining the goals and objectives of the BPE project. Candidate business processes are identified. The selected strategic "As-Is" business processes are analyzed to find where problems exist. Several techniques are employed to engineer the "To-Be" process. The new process may be a radical departure from the old process. The alternatives are evaluated using cost/benefit analysis. The selected processes are then implemented using a phased approach that relies on information technology solutions along with the implementation of recommended organizational and cultural changes. A continuous improvement program is put into place to ensure long term success. A Model-Year Architecture Approach to Hardware Reuse in Digital Signal Processor System DesignJanet Wedgwood and Greg BuchananAbstractThe Rapid Prototyping of Application-Specific Signal Processors (RASSP) program is changing the way engineers design embedded signal processors. The objective of the program is to reduce time-to-market and cost by at least a factor of four, and improve design quality by at least a factor of four. We are achieving these improvements using a methodology and framework that stresses hardware and software reuse, and model-year architectures that help engineers reuse elements and upgrade through open interface standards. This paper describes our team's hardware model-year architecture approach to develop cost-effective signal processors that can be applied to a wide range of military and commercial applications. We will present an overview of the MYA approach and describe the framework. We will introduce two key hardware architectural interfaces: the Standard Virtual Interface (SVI) and the Reconfigurable Network Interface (RNI) [LM ATL 1996b]. Next we will describe several implementations of the SVI and RNI to illustrate how they would be used and some of the issues involved in implementing this approach. We will discuss how the MYA relates to other efforts in the area of standard interfaces such as PCI (Peripheral Component Interconnect) [PCI 1993], PacketWay [Cohen et. al. 1997], the Virtual Microarchitecture Interface (VMI) [LM ATL1997a] and the Virtual Socket Interface Alliance (VSIA) [VSIA1997]. Finally, we will present our conclusions. Myrinet to SVI External Network Interface Application NotesGreg BuchananAbstractThe Myrinet to SVI External Network Interface (ENI) is designed to serve as the network interface component for a RASSP MYA Reconfigurable Network Interface (RNI). The ENI acts as a fully compliant full-duplex, 1-meter Myrinet port on one side, and a fully compliant SVI port on the op-posing side. The ENI fully translates and converts messages bidirectionally from one port to the other. When connected to an RNI bridge element, incoming messages from the Myrinet port will be translated and formatted as required for the opposing or "bridged" ENI; the bridge element will likewise translate messages from the bridged ENI, which are destined to become outgoing messages on the Myrinet. The Ontolingua Server: A Tool for Collaborative Ontology ConstructionAdam Farquhar, Richard Fikes and James RiceAbstractReusable ontologies are becoming increasingly important for tasks such as information integration, knowledge-level interoperation, and knowledge-base development. We have developed a set of tools and services to sup-port the process of achieving consensus on common shared ontologies by geographically distributed groups. These tools make use of the world-wide web to enable wide access and provide users with the ability to publish, browse, create, and edit ontologies stored on an ontology server. Users can quickly assemble a new ontology from a library of modules. We discuss how our system was constructed, how it exploits existing protocols and browsing tools, and our experience supporting hundreds of users. We describe applications using our tools to achieve consensus on ontologies and to integrate information. Preliminary Module Development Specification for the Data I/O ModuleMartin Marietta Advanced Technology LaboratoriesAbstractThis specification establishes the performance, design, development, and test requirements for the Data I/O Module for use in the Synthetic Aperture Radar Signal Processor (SAR-SP) hardware configuration item for use aboard the ADTS aircraft. Preliminary Module Development Specification for the Host Interface ModuleMartin Marietta Advanced Technology LaboratoriesAbstractThis specification establishes the performance, design, development, and test requirements for the Host Interface Module for use in the Synthetic Aperture Radar Signal Processor (SAR-SP) hardware configuration item for use aboard the ADTS aircraft. Preliminary Module Development Specification for the Processing Element ModuleMartin Marietta Advanced Technology LaboratoriesAbstractThis specification establishes the performance, design, development, and test requirements for the Processor Element Module of the SAR Signal Processor Configuration Item. Preliminary Software Requirements Specification for the Control Program FirmwareMartin Marietta Advanced Technology LaboratoriesAbstractThis specification establishes the performance, design, development, and test requirements for the Control Program Firmware for use in the Synthetic Aperture Radar Signal Processor (SAR-SP) hardware configuration item for use aboard the ADTS aircraft. Preliminary Software Requirements Specification for the Data Processing FirmwareMartin Marietta Advanced Technology LaboratoriesAbstractThis specification establishes the performance, design, development, and test requirements for the Data Processing Firmware for use in the Synthetic Aperture Radar Signal Processor (SAR-SP) hardware configuration item for use aboard the ADTS aircraft. Process Modeling Language SpecificationDavid E. GrubelAbstractTo promote transferability of workflows, a tool independent language is needed for process flow definition. The Process Modeling Language (PML) defined in this specification describes models built using an extended version of the Integrated Computer-Aided Manufacturing DEFinition Number 3 language (IDEF-3x). This specification provides a "template" for importing and exporting process models (workflows) to and from model repositories. The Process Modeling Language (PML) grammar will be expressed in the Backus Naur Form (BNF). A Proposed Implementation of the RASSP Authorization Model Using Intergraph DM2Intergraph CorporationAbstractThe RASSP Authorization Model can be implemented using DM2. An authorization in DM2 performs the same function as the triplet, {o I ,r j , t k } where o I is an authorization object in an authorization object hierarchy, r j is an authorization role in an authorization role hierarchy, and t k is an authorization type in an authorization type hierarchy. DM2 extends the definition of the triplet by adding a condition which defines the circumstances that allow the authorization role to perform the authorization type on the authorization object. An authorization in DM2.0 can then be described as a quadruplet {o I ,r j , t k ,c n }, where c n is the authorization condition. A Proposed Implementation of the RASSP Configuration Management Model Using Intergraph DM2Intergraph CorporationAbstractThis document proposes a DM2 implementation of the RASSP Enterprise Framework's workspace hierarchy, scheme for version control, and configuration management. Proposed Message Structure for RACEway / Myrinet RNI Demonstration Application NotesGreg BuchananAbstractThis document proposes a set of assumptions and message structures for building a RACEway to Myrinet RNI. To some degree, the message structures are dictated by the way the RACEway and Myrinet SVI encapsulations were built. For example, the Myrinet SVI encapsulation assumes that a 4-byte packet type word will follow the route words, so this proposal makes use of that feature of the encapsulation operation. The message structure proposed here for the RNI should also be suitable for use in the VMI virtual prototype model. RACEway to SVI External Network InterfaceGreg BuchananAbstractThe RACEway to SVI External Network Interface (ENI) is designed to serve as the network fabric interface component for a RASSP MYA Reconfigurable Network Interface (RNI). The ENI acts as a fully compliant half-duplex, RACEway port on one side, and a fully compliant SVI port on the opposing side. The ENI fully translates and converts messages bidirectionally from one port to the other. When connected to an RNI bridge element, incoming messages from the RACEway port will be translated and formatted as required for the opposing or "bridged" ENI; the bridge element will likewise translate messages from the bridged ENI, which are destined to become outgoing messages on the RACEway. RASSP: The Authorization Model for the RASSP System Version 2Martin Marietta LaboratoriesAbstractThe various enterprise-level tools and CAD tools use diverse and incompatible models and mechanisms for authorization. Thus currently the authorization information cannot be shared among the various tools used in the RASSP enterprise framework. Authorizations have to be specified separately in the various tools and the management of the consistency of the authorization information among the tools in an enterprise is a management nightmare and a significant cost overhead. In this report we propose a common generic model of authorization that may be adopted by the RASSP enterprise framework tools and the CAD tools. We have specified a common minimal set of authorization management mechanisms that need to be provided by the tools to support the proposed model. To facilitate the exchange of authorization data between tools the authorization data generated by each tool will be modeled using the Configuration Management conformance class 1 of the STEP 2 (Standard for the Exchange of Product Model Data) standard AP203 [ISO, 1993]. Our model of authorization is based on the authorization model proposed for object data management systems by [Rabitti, 1991]. An important criterion we have followed in the development of the model and the mechanisms is that they should be generic enough to allow an organization to adopt any authorization policy it chooses to. RASSP Build 1A System Design Document Version 1ALockheed Martin Corporation Advanced Technology LaboratoriesAbstractThe intent of this document is to define the enterprise system as configured to support the benchmark 3 / UYS2 upgrade program. RASSP Build 1 Configuration Management - RASSP Enterprise Data ModelLockheed Martin Corporation Advanced Technology LaboratoriesAbstractThis document is an IDEF diagram for Build 1 of the Configuration Management - RASSP Enterprise Data Model. RASSP Build 2 System Description Version 1.0Lockheed Martin Corporation Advanced Technology LaboratoriesAbstractThe purpose of this document is to describe the Build 2 version of the RASSP Enterprise Framework. The design tool encapsulation and working environments guides are included as appendices to this document. RASSP: The Configuration Management Model for the RASSP System Version 3D. Blanchard and B. KalathilAbstractWe propose in this document a common model of configuration management that may be adopted by the RASSP enterprise framework tools and the CAD tools. This model provides for the management of the various versions of the design objects that are created and manipulated during the process of the design of a product. The model does not cater to the version management of reusable library components that are created outside of the design process. The release management of reusable library components is described in [Martin Marietta, 1994]. We have specified a common minimal set of configuration management mechanisms that need to be provided by the tools to support the proposed CM model. To facilitate the exchange of CM data between tools the CM data generated by each tool will be modeled using the CM conformance class of the STEP (Standard for the Exchange of Product Model Data) standard AP203 [ISO, 1993]. An important criterion we have followed in the development of the model and the mechanisms is that they should be generic enough to allow an organization to adopt any CM process it chooses to. RASSP Design For Test TrainingJohn S. Evans, Shanti Sharma, R. J. Tarzaiski and Richard M. SedmakzAbstractTutorial describing the RASSP overall test architecture with components testbench architecture, testability architecture, and tester architecture. The relationship of these components to the test strategy diagram is examined. The complete spectrum of testing from requirements specification to development of test plans and procedures is presented. RASSP Design Tool Encapsulation Document Version 2.0Lockheed Martin Advanced Laboratories TeamAbstractThe purpose of this document is to describe the procedure for encapsulating design tools into the Build 2 version of the RASSP Enterprise Framework. It does not address the installation of the individual design tools. RASSP Design-For-Testability MethodologyLockheed Martin Advanced Laboratories TeamAbstractThe RASSP Design-For-Testability (DFT) Methodology enables designers to create systems that can be cost-effectively tested throughout their life cycles. Designs that adhere to this methodology are made testable on the basis of various design for testability (DFT) and built-in-self- test (BIST) techniques. The methodology covers various aspects of test and diagnosis at the chip, MCM, board and system levels, including test requirements capture; test strategy development; DFT and BIST architecture development; DFT and BIST design and insertion; test pattern generation; test pattern evaluation; and test application and control. This methodology provides the designer with a process for introducing testability requirements and constraints early in the design cycle and for addressing DFT and BIST issues hierarchically at the chip, multichip module (MCM), board, and system levels. The payback for early testability emphasis includes lower test cost throughout the life cycle of the product, reduced design cycle time, improved system quality, and enhanced system availability and maintainability. RASSP In-Progress ReportLockheed Martin Advanced Laboratories TeamAbstractThe goal of the DARPA/Tri-Service-sponsored Rapid Prototyping of Application-Specific Signal Processors (RASSP) program is to reduce the cost and time to develop and manufacture signal processors by at least a factor of four. Lockheed Martin Advanced Technology Laboratories' (ATL) approach to reaching this goal is based on three thrusts: methodology, model-year architecture, and infrastructure (enterprise). The Advanced Technology Laboratories' RASSP team -- composed of an alliance of companies -- implemented the first baseline RASSP system, which advances today's state-of-the-art by a factor of >2X. The Advanced Technology Laboratories' RASSP used the methodology and tools to demonstrate cost and design-cycle improvements on the benchmark virtual prototype, and developed a hardware/ software system that demonstrated first-pass success. Additional developments underway will provide further benefits and will demonstrate 4X improvements in cost and time to market. This paper updates the team's progress halfway through the program, and highlights the impact of using the RASSP concepts on the design of a SAR processor, a Navy standard processor upgrade, and a CNI application. RASSP Enterprise Framework Approach for Model Repository DevelopmentMartin Marietta CorporationAbstractThis report describes the approach to be taken in development of the Rapid prototyping of Application-Specific Signal Processors (RASSP) model repository. RASSP Enterprise Framework Approach for Workflow DevelopmentMartin Marietta CorporationAbstractThis report describes the approach to be taken in development of the Rapid prototyping of Application-Specific Signal Processors (RASSP) workflows. RASSP Enterprise Model Repository User GuideJeffrey StavashAbstractThese are memo notes that include a copy of the RASSP Enterprise Model Repository User Guide. RASSP Enterprise Technologies for Signal Processor Life-Cycle SupportJohn Welsh, Bipin Chadha, Biju Kalathil, Peter Holmes, Mary Catherine Tuck, William Selvidge, Elisa Finnie and Lynwood HinesAbstractEnterprise integration technologies are a key contributor to improving time-to-market, cost, and design quality by a factor, which is the goal of the DARPA Rapid Prototyping of Application-Specific Signal Processors (RASSP) program [1]. The Lockheed Martin Advanced Technology Laboratories (ATL) RASSP team developed a productivity improvement model, shown in Figure 1, that indicates the relative contributions of various RASSP technologies to the overall improvement. Enterprise technologies address the entire 17% enterprise partition, and more than half of the 30% reuse and model-year architecture partition, thus accounting for at least 35% of the overall RASSP productivity improvement. The RASSP Integrated Systems Tool Set Provides a Concurrent Engineering Environment for Design Trade-OffsGregory Barnett and Charles Fry, PEAbstractThe goal of the DARPA/Tri-Service-sponsored Rapid Prototyping of Application Specific Signal Processors (RASSP) program is to reduce development and manufacturing time and cost of signal processors by a factor of four. Lockheed Martin's Advanced Technology Laboratories (ATL) RASSP team has developed an integrated systems engineering tool set which forms the basis for a concurrent engineering design environment. This design environment, which consists of Ascent Logic's RDD-100, PRICE Systems parametric cost estimation models, and Management Sciences RAM-ILS tools, provides the integrated product development team with cost and reliability estimation data within a systems engineering tool. The concurrent engineering design environment is described and an example is provided which demonstrates the value of the tool integration within the design environment. This design environment enables the integrated product development team to estimate the life-cycle costs and reliability early in the design process. RASSP: The Library Management Model for the RASSP System Version 2Lockheed Martin Advanced Laboratories TeamAbstractIn today's design environments, the ability of the design engineer to maximize reuse is impaired by the fact that there is no efficient way of searching for reusable design objects across multiple sources; and the various sources of reusable data are uncoupled to the design environment. We describe in this paper the approach we have developed for managing reusable design objects in a system for Rapid Prototyping of Application-Specific Signal Processors (RASSP). Our approach consists of (1) developing a design object class hierarchy that classifies the various types of design objects in the RASSP domain, and models the descriptive data associated with the design objects, and (2) developing a commercial library management system which will implement the design object class hierarchy; and provide mechanisms for searching for design objects across multiple libraries, and across a virtual enterprise. RASSP Methodology Version 2.0Lockheed Martin Advanced Laboratories TeamAbstractThe RASSP Methodology is organized into five basic sections. This section summarizes the overall methodology from a perspective that spans individual processes. The individual process areas on RASSP are program planning, the design process, manufacturing and test, and specialty engineering. Section 2 describes the project planning phase of the program. Section 3 is the focal point of the document; it describes the overall design process for RASSP. Sections 4 and 5 describe the subsequent manufacture and test, and specialty engineering ('ilities, etc.) disciplines, respectively, and how they interface to the design process. RASSP MYA Specification Volume I: Introduction to Model Year Architecture Version 1.0AbstractThe purpose of the RASSP Model Year Architecture Specification is to consolidate and communicate the latest developments in the Lockheed Martin RASSP Model Year Architecture definition. This document, RASSP Model Year Architecture Specification - Version 1.0, represents the first formal release of the MYA specification and coincides with the completion of the primary phase of the RASSP program. This specification supercedes information contained in preceding versions of the RASSP Model Year Architecture Working Document, and has been refined through three previous iterations during the course of the RASSP program. This version of the MYA Specification differs from previous versions of the MYA Working Document in that the specifications for the four key components of the Model Year Architecture -- hardware architecture elements, the Standard Virtual Interface, software architecture elements, and reuse library elements -- have been broken out as separate volumes of the MYA Specification. Except for the Standard Virtual Interface specification, the information covered in these volumes was previously included in the MYA Working Document. This volume of the MYA Specification presents an overview of the Model Year Architecture approach and introduces its constituent components. RASSP MYA Specification Volume II: Hardware Architecture Element Specification Version 1.0AbstractThe purpose of this document is to convey a formal specification for hardware architecture elements which comprise the RASSP Model Year Architecture (MYA) Functional Architecture. The Functional Architecture defines the necessary components at the architectural level and the manner in which their interfaces must be defined to ensure that the resulting architecture design is upgradable and facilitates technology insertion. As such, the Functional Architecture is a starting point for developing an architecture for an application-specific problem, not a detailed instantiation of an architecture. Adherence to this specification will ensure the creation of architectural elements, and the design of specific architectures which include them, which will provide the RASSP MYA features of architectural element reuse, interoperability, and facilitated upgradability. RASSP MYA Specification Volume III: Standard Virtual Interface Specification Version 1.0AbstractThe purpose of this document is to convey a formal specification for the Standard Virtual Interface (SVI), a technology-independent functional interface which facilitates hardware up-grades and technology insertion at the architectural level. This specification should be used when designing and modeling architectural reuse library elements to ensure interoperability among those various library elements. The use of the SVI is not applicable to board or module level COTS products. Such products are expected to be based on an industry-accepted non-proprietary open interface standard which allows upgrades and technology insertion with respect to that standard. The SVI provides an additional level of interoperability and flexibility for upgrades and technology insertion in cases where designs, while making use of COTS components at the chip level, are under control of the RASSP user community. Refer to the RASSP Model Year Architecture Specification, Vols. I & II for more information about Model Year Architecture concepts and applications of the SVI. The definition of the SVI presented in this specification supercedes that which was presented in the RASSP Model Year Architecture Working Document. RASSP MYA Specification Volume IV: Standard Virtual Interface Specification Appendices Version 1.0AbstractThis text includes all Appendices for "RASSP MYA Specification". RASSP Virtual Prototyping for DSP Systems34th Design Automation Conference, Anaheim, Ca., June, 1997C. Hein, J. Pridgen and W. KlineAbstractThis paper describes a top-down hierarchical simulation process that dramatically accelerates the design-evolution of DSP systems when compared with traditional physical prototyping methods. A summary of the model abstraction hierarchy and purposes for the various types of models provides critical guidance in selecting appropriate abstractions to achieve accurate yet efficient simulations. The simulations enable rapid exploration of many more alternative software and hardware solutions than would be practical using conventional gate-level simulation technologies. The result is improved design adaptations and quality. Reconfigurable Network Interface (RNI) Guideline Myrinet to PCI RNIAbstractThis document contains a description of a particular Reconfigurable Network Interface (RNI) which was developed as part of the hardware verification study under the Model Year Architecture task of the DARPA-sponsored Rapid Prototyping of Application Specific Signal Processors (RASSP) program. The purpose of this document is to aid designers in the understanding and use of the RNI and describe the considerations which drive the design structure. Subsytems Architecture and Allocations Document for the Benchmark 1 SARRASSP Project USAAbstractThe Benchmark 1 SAR is an imaging signal processor to be attached to a synthetic aperture radar. The current concept for the SAR signal processor has several different potential architectures. This document covers all the potential components to be used in those architectures. SVI Verification Study: Encapsulations of the Benchmark II - Data I/O Board and the Mercury Rino-RIC ChipsetAmit ChhabraAbstractThis document provides a description of the Data I/O board and Rino chipset encapsulations using the SVI methodology in accordance with the goals of the Model Year Architecture Task of the RASSP Program. SVI Verification Task (Case 2) - RNI Encapsulation Study: VHDL Model Description Application NotesGreg BuchananAbstractThe objective of this verification task is to create and demonstrate a VHDL example of a simple Remote Network Interface (RNI) Element. In this case the RNI concept is demonstrated in a sensor interface application which links the Cypress HOTLink high-speed serial link to a PCI interconnect fabric. The RNI model is demonstrated by instantiating the RNI model into the WSSPT SEM-E model, and then exercising the RNI in conjunction with multiple WSSPT PE's. The HOTlink model is available for reuse. Due to its proprietary nature, the WSSPT and PCI models are not available for reuse. Systems Requirements Specification (SRS) for the Enterprise Integration Framework (EIF) of RASSPMartin Marietta CorporationAbstractThis Systems Requirements Specification (SRS) details the requirements for the Rapid Prototyping of Application-Specific Signal Processors (RASSP) Enterprise Integration Framework (EIF). Test Strategy Diagram Example (Subsystem Level)AbstractAn EXCEL implementation of the subsystem level test strategy diagram for the Benchmark 3 Functional Element consisting of one FPCTL board and two FPCAP boards. Requirements, predictions, and differences between these quantities are entered into cells for later distribution to lower level TSDs. Test Strategy Diagram Example (Board Level)AbstractAn EXCEL implementation of the board level test strategy diagram for the benchmark 3 boards. Requirements, predictions, and differences are described. The TSD automates the interrelationships among the established sequence derived from the singular test philosophy. Test means for the boards and their capabilities of error detection, isolation, and correction are described as cell entries, and summaries for higher level application of these results are automatically coupled to the next higher level TSD. Tutorial on RASSP Design-For-TestabilityJohn S. Evans, Shanti Sharma, R. J. Tarzaiski and Richard M. SedmakAbstractIntroduction to the problem of testing across design, manufacturing, and field deployment. Describes DFT solution, RASSP DFT goals, and the integration of DFT into RASSP. Using Shared Work Locations With the RASSP Enterprise SystemAbstractThe Build 2 production version of the RASSP Enterprise System has been upgraded to support multiple engineers working concurrently in the same DMM workflow task. This is accomplished through the use of a shared work location. The intent of this short document is to describe the functionality of a shared work location. Using WorkXpert to Implement RASSP Electronic Design WorkflowsJeffery StavashAbstractThe goal of the ARPA/Tri-Service sponsored Rapid Prototyping of Application-Specific Signal Processors (RASSP) program is to improve, by at least a factor of four, the time-to-market, life-cycle cost, and design quality of Digital Signal Processor (DSP) systems. One way this goal is being achieved is through the use of enterprise system technology. Lockheed Martin Advanced Technology Laboratories (ATL) is developing an enterprise system which integrates a workflow manager, product data manager, reuse data manager, Computer-Aided Design (CAD) tools, and network services into a single cohesive framework. The workflow manager guides the user through the design process with graphical workflows. The product data manager configuration manages the design data that's being produced. The reuse data manager supports the cataloging and searching for reusable design objects. Network services addresses the design-to-manufacturing interface via a secure network protocol. By integrating work -flows, product data, CAD tools, and network services together, an enterprise system enables a concurrent/collaborative approach to DSP design that embraces the entire life cycle from requirements to manufacture. This paper describes how workflows for electronic design were developed on the RASSP program by ATL, and how those workflows were implemented using the Mentor Graphics WorkXpert product. |