|**************************************************************************** [RAIL Ver] 1.2 [File Name] test.ral [File Rev] 0.1 [Date] 5/20/98 [Source] John Keifer from Intel [Notes] Generic Example of a RAIL file [Disclaimer] [Copyright] Copyright |**************************************************************************** [RAIL Title] Test_PC_System [Unit Length] inch |**************************************************************************** [Stackup] |layer height W/ER DIEL: 5m ER=4.8 SIG: 1.4m W=6.25m DIEL: 5m ER=4.8 PLANE: 1.4m DIEL: 40m ER=4.8 PLANE: 1.4m DIEL: 5m ER=4.8 SIG: 1.4m W=6.25m DIEL: 5m ER=4.8 |**************************************************************************** [Map Table] |refes generic model part | name name name U1 CST cs.ibs NA U2 CLOCK clock.ibs NA U3 SB sb.ibs SouthBridge U4 CPU_conn cpuconn.mmf NA U11 DIMM_conn0 dimmconn.mmf NA U12 DIMM_conn1 dimmconn.mmf NA U13 DIMM_conn2 dimmconn.mmf NA J1 PCICARD pcicard.ibs NA J2 ISACARD isacard.ibs NA |**************************************************************************** [Multiboard] |outgoing ingoing assembly |refdes refdes name U4 J1 cpucard.ral U11 J1 dimm.ral U12 J1 dimm.ral U13 J1 dimm.ral |**************************************************************************** [Group Nets] AGP_Bus AGP_data AGP_strobe AGP_ctrlpu AGP_ctrl [Group Nets] AGP_data GAD(31:0) GC_BE(3:0)# SBA(7:0) [Group Nets] AGP_strobe AD_STB(1:0) SB_STB [Group Nets] AGP_ctrlpu GFRAME# GTRDY# GIRDY# GDEVSEL# GSTOP# GSERR# GPERR# GREQ# GGNT# PIPE# GPAR RBF# [Group Nets] AGP_ctrl ST(2:0) [Group Nets] Host_Bus HA(31:3) HD(63:0) [Group Nets] DRAM CS(7:0)# MAx(13:0) SRAS(3:0)# SCAS(3:0)# WE(3:0)# CKE DQM(7:0)# MD [Group Nets] CS(7:0)# RCSA(7:0)# RCSB(7:0)# [Group Nets] MAx(13:0) MAA(13:0) MAB(1:0) [Group Nets] DQM(7:0)# CDQA(7:0)# CDQB(5,1)# [Group Nets] MD MD(63:0) MECC(7:0) [Group Nets] HCLKs HCLKPC HCLKAGP HCLKDIMM(11:0) [Group Nets] Host_Ctrl ADS# BNR# DBSY# DRDY# HIT# HITM# BREQ0# HLOCK# HTRDY# HREQ(4:0)# RS(2:0)# DEFER# BPRI# FERR# IGNNE# INTR NMI SMI# STPCLK# CPURST# INIT# RSTIN# [Group Nets] PCICLKs PCLKSB PCLK(3:0) PCLKCS [Group Nets] PCI_Bus AD(31:0) C_BE(3:0)# FRAME# IRDY# TRDY# STOP# PLOCK# DEVSEL# SERR# [Group Nets] PCI_ptpt REQ#(4:0) GNT#(4:0) PAR PERR# PHLD# PHLDA# WSC# [Group Nets] PCI_NETS PCI_Bus PCI_ptpt [Group Parts] PCI CS SB PCICARD |**************************************************************************** [DC Nets] |net_name DC Voltage GND 0.0V VCC 5.0V -5V -5.0V -12V -12.0V VCC2.5 2.5V VCC3 3.3V VTT 1.5V GTL_VREF 1.5V | |**************************************************************************** [Trace Char] |net/group_name Zo_typ Zo_min Zo_max Td_typ Td_min Td_max Default 65 50 80 175p 150p 200p | |**************************************************************************** [Budgets] Host_Bus | high low intra inter |drvr - rcvr {sig} sigs edge duration min max overshoot overshoot xtalk xtalk CPU - CST {sig} HA(31:3) B 15.0n 0.5n 5.0n 2.45 -0.80 500m 300m CST - CPU {sig} HA(31:3) B 15.0n 0.5n 5.0n 2.45 -0.80 500m 300m CPU - CST {sig} HD(63:0) B 15.0n 0.5n 5.0n 2.45 -0.80 500m 300m CST - CPU {sig} HD(63:0) B 15.0n 0.5n 5.0n 2.45 -0.80 500m 300m | [Budgets] Host_Ctrl | high low intra inter |drvr - rcvr {sig} sigs edge duration min max overshoot overshoot xtalk xtalk CPU - CST {sig} CPURST# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CPU - CST {sig} ADS# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CST - CPU {sig} ADS# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CPU - CST {sig} BNR# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CST - CPU {sig} BNR# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CPU - CST {sig} INIT# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CPU - CST {sig} DBSY# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CST - CPU {sig} DBSY# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CPU - CST {sig} DRDY# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CST - CPU {sig} DRDY# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CPU - CST {sig} HLOCK# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CPU - CST {sig} HIT# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CST - CPU {sig} HIT# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CPU - CST {sig} HITM# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CST - CPU {sig} HITM# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CST - CPU {sig} HTRDY# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CPU - CST {sig} HREQ(4:0)# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CST - CPU {sig} HREQ(4:0)# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CST - CPU {sig} RS(2:0)# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m SB - CST {sig} PCIRST# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CST - CPU {sig} DEFER# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CST - CPU {sig} BPRI# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m CPU - SB {sig} FERR# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m SB - CPU {sig} IGNNE# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m SB - CPU {sig} INTR B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m SB - CPU {sig} NMI B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m SB - CPU {sig} SMI# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m SB - CPU {sig} STPCLK# B 15.0n 0.2n 4.0n 2.45 -0.80 500m 300m | [Budgets] PCI_NETS | high low intra inter |drvr - rcvr {sig} sigs edge duration min max overshoot overshoot xtalk xtalk PCI - PCI {sig} PCI_Bus B 30.0n 0.0n 9.0n 11.00 -5.50 500m 300m PCI - PCI {sig} PCI_ptpt B 30.0n 0.0n 4.0n 11.00 -5.50 500m 300m | [Budgets] AGP_Bus | high low intra inter |drvr - rcvr {sig} sigs edge duration min max overshoot overshoot xtalk xtalk AGP - AGP {sig} AGP_Bus B 15.0n 0.0n 2.7n 4.40 -0.80 500m 300m | [Budgets] SDRAM_1DIMM | high low intra inter |drvr - rcvr {sig} sigs edge duration min max overshoot overshoot xtalk xtalk CST - SDRAM {sig} CS(7:0)# B 15.0n 0.5n 4.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} MAx(13:0) B 30.0n 0.5n 7.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} SRAS(3:0)# B 30.0n 0.5n 5.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} SCAS(3:0)# B 30.0n 0.5n 5.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} WE(2:0)# B 30.0n 0.5n 5.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} CKE B 30.0n 0.5n 15.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} DQM(7:0)# B 15.0n 0.5n 3.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} MD(63:0) B 15.0n 0.5n 3.0n 4.97 -1.50 500m 300m SDRAM - CST {sig} MD(63:0) B 15.0n 0.0n 2.0n 4.97 -1.50 500m 300m | [Budgets] SDRAM_2DIMM | CST - SDRAM {sig} MAx(13:0) B 30.0n 0.5n 10.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} SRAS(3:0)# B 30.0n 0.5n 5.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} SCAS(3:0)# B 30.0n 0.5n 5.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} WE(2:0)# B 30.0n 0.5n 5.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} CKE B 30.0n 0.5n 15.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} DQM(7:0)# B 15.0n 0.5n 4.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} MD(63:0) B 15.0n 0.5n 3.0n 4.97 -1.50 500m 300m SDRAM - CST {sig} MD(63:0) B 15.0n 0.0n 2.0n 4.97 -1.50 500m 300m | [Budgets] SDRAM_3DIMM | CST - SDRAM {sig} MAx(13:0) B 30.0n 0.5n 15.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} SRAS(3:0)# B 30.0n 0.5n 9.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} SCAS(3:0)# B 30.0n 0.5n 9.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} WE(2:0)# B 30.0n 0.5n 9.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} CKE B 30.0n 0.5n 15.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} DQM(7:0)# B 15.0n 0.5n 4.0n 4.97 -1.50 500m 300m CST - SDRAM {sig} MD(63:0) B 15.0n 0.5n 4.0n 4.97 -1.50 500m 300m SDRAM - CST {sig} MD(63:0) B 15.0n 0.0n 2.0n 4.97 -1.50 500m 300m | |**************************************************************************** | typ min max [Topology] Host_Bus TpKc CST CPU_conn NA 1.0 8.00 [Topology] CDQA(7:0)# Tt CST Tee A 1.00 5.00 Ttd2 Tee DRAM2 0.25 NA NA Ttd1 Tee DRAM1 0.25 NA NA Td2d0 DRAM1 DRAM0 0.75 NA NA [Topology] CDQB(5,1)# Td1 CST DRAM2 A 1.0 5.00 [Topology] RCSA0# Tpt CST Tee NA NA 4.00 Ttd0 Tee DRAM0!30 1 NA NA Ttd0 Tee DRAM0!45 1 NA NA [Topology] RCSA1# Tpt CST Tee NA NA 4.00 Ttd0 Tee DRAM0!114 1 NA NA Ttd0 Tee DRAM0!129 1 NA NA [Topology] RCSA2# Tpt CST Tee NA NA 4.00 Ttd1 Tee DRAM1!30 1 NA NA Ttd1 Tee DRAM1!45 1 NA NA [Topology] RCSA3# Tpt CST Tee NA NA 4.00 Ttd1 Tee DRAM1!114 1 NA NA Ttd1 Tee DRAM1!129 1 NA NA [Topology] RCSA4# Tpt CST Tee NA NA 4.00 Ttd2 Tee DRAM2!30 1 NA NA Ttd2 Tee DRAM2!45 1 NA NA [Topology] RCSA5# Tpt CST Tee NA NA 4.00 Ttd2 Tee DRAM2!114 1 NA NA Ttd2 Tee DRAM2!129 1 NA NA [Topology] MAB(13:0) Tpd2 CST DRAM2 NA 1.0 5.00 [Topology] MAA(13:0) Tpd1 CST DRAM1 NA 1.0 5.00 Td1d0 DRAM1 DRAM0 0.5 NA NA [Topology] MD(63:0) Tpd2 CST DRAM2 NA 1.0 5.00 Td2d1 DRAM2 DRAM1 0.5 NA NA Td1d0 DRAM1 DRAM0 0.5 NA NA [Topology] HCLKPC Tct CLOCK Tee NA NA 1.00 Ttr1 Tee R1 NA NA 1.00 R33 R1 R2 33 TrK R2 CPU_conn A+3.0 NA 15.00 Ttr3 Tee R3 NA NA 1.00 R33 R3 R4 33 Trp R4 CST A+8.0 NA 15.00 [Topology] HCLKAGP Tcr7 CLOCK Tee NA NA 1.00 Ttr7 Tee R7 NA NA 1.00 R33 R7 R8 33 Trc R8 AGP_conn A+5.0 NA 15.00 TcA AGP_conn AGP 3.3 NA NA [Topology] HCLKDIMM0 Tcr9 CLOCK R9 NA NA 1.00 R10 R9 R10 22 Trdc0 R10 DIMM_conn0!42 A NA 8.00 [Topology] HCLKDIMM1 Tcr11 CLOCK R11 NA NA 1.00 R10 R11 R12 22 Trdc0 R12 DIMM_conn0!125 A NA 8.00 [Topology] HCLKDIMM2 Tcr13 CLOCK R13 NA NA 1.00 R10 R13 R14 22 Trdc0 R14 DIMM_conn0!79 A NA 8.00 [Topology] HCLKDIMM3 Tcr15 CLOCK R15 NA NA 1.00 R10 R15 R16 22 Trdc0 R16 DIMM_conn0!163 A NA 8.00 [Topology] HCLKDIMM4 Tcr17 CLOCK R17 NA NA 1.00 R10 R17 R18 22 Trdc1 R18 DIMM_conn1!42 A NA 8.00 [Topology] HCLKDIMM5 Tcr19 CLOCK R19 NA NA 1.00 R10 R19 R20 22 Trdc1 R20 DIMM_conn1!125 A NA 8.00 [Topology] HCLKDIMM6 Tcr21 CLOCK R21 NA NA 1.00 R10 R21 R22 22 Trdc1 R22 DIMM_conn1!79 A NA 8.00 [Topology] HCLKDIMM7 Tcr23 CLOCK R23 NA NA 1.00 R10 R23 R24 22 Trdc1 R24 DIMM_conn1!163 A NA 8.00 [Topology] HCLKDIMM8 Tcr25 CLOCK R25 NA NA 1.00 R10 R25 R26 22 Trdc2 R26 DIMM_conn2!42 A NA 8.00 [Topology] HCLKDIMM9 Tcr27 CLOCK R27 NA NA 1.00 R10 R27 R28 22 Trdc2 R28 DIMM_conn2!125 A NA 8.00 [Topology] HCLKDIMM10 Tcr29 CLOCK R29 NA NA 1.00 R10 R29 R30 22 Trdc2 R30 DIMM_conn2!79 A NA 8.00 [Topology] PCLK1 Tcr41 CLOCK R41 NA NA 1.00 R10 R41 R42 33 Trpc1 R42 PCICONN1 A+10.0 NA 15.00 [Topology] PCLK2 Tcr43 CLOCK R43 NA NA 1.00 R10 R43 R44 33 Trpc2 R44 PCICONN2 A+10.0 NA 15.00 [Topology] PCLK3 Tcr45 CLOCK R45 NA NA 1.00 R10 R45 R46 33 Trpc3 R46 PCICONN3 A+10.0 NA 15.00 [Topology] PCLK4 Tcr47 CLOCK R47 NA NA 1.00 R10 R47 R48 33 Trpc4 R48 PCICONN4 A+10.0 NA 15.00 [Topology] PCLKCS Tcr49 CLOCK R49 NA NA 1.00 R10 R49 R50 33 Trp R50 CST A+10.0 NA 15.00 [Topology] PCLKSB Tcr51 CLOCK R51 NA NA 1.00 R10 R51 R52 33 TrpX R52 SB A+10.0 NA 15.00 [Topology] HPICCLK Tcr53 CLOCK R53 D NA 1.00 R33 R53 R54 33 TrKc R54 CPU_conn NA NA 10.00 TcA CPU_conn APIC NA NA 4.00 [Topology] AGP_data Tpc CS AGP_conn NA 1.00 10.00 TcA AGP_conn AGP NA 0.5 3.0 [Topology] AGP_strobe Tps CST stub 0.1 NA NA R55 stub VCC3 8.0k Tpc stub AGP_conn NA 1.00 10.00 TcA AGP_conn AGP NA 0.5 3.0 [Topology] AGP_ctrlpu Tps CST stub 0.5 NA NA R56 stub VCC3 8.0k Tpc stub AGP_conn NA 1.00 10.00 TcA AGP_conn AGP NA 0.5 3.0 [Topology] AGP_ctrl Tps CST AGP_conn NA 1.00 10.00 TcA AGP_conn AGP NA 0.5 3.0 | |**************************************************************************** [Priority] AGP_Bus Host_Bus DRAM HCLKs Host_Ctrl PCICLKs PCI_Bus PCI_ptpt | |**************************************************************************** [Clocks] HCLKs Frequency = 66MHz Duty_cycle = 0.60 Jitter = 300ps High_time = 4.0ns Low_time = 4.0ns Rise_time = 1.5ns Fall_time = 1.5ns Overshoot_high = 6.05V Overshoot_low = -0.8V Crosstalk = 100mV [Clocks] PCICLKs Frequency = 33MHz Duty_cycle = 0.60 Jitter = 300ps High_time = 11.0ns Low_time = 11.0ns Rise_time = 1.2ns Fall_time = 1.2ns Overshoot_high = 6.05V Overshoot_low = -0.8V Crosstalk = 100mV [Clocks] PICCLK Frequency = 14.31818 Duty_cycle = 0.60 Jitter = 300ps High_time = 11.0ns Low_time = 11.0ns Rise_time = 1.2ns Fall_time = 1.2ns Overshoot_high = 6.05V Overshoot_low = -0.8V Crosstalk = 100mV | |**************************************************************************** [Clock Skew] |group/net_name {part} generic_name - group/net_name {part} generic_name |rcvr1 - rcvr2 edge min max HCLKPC {part} CPU - HCLKPC {part} CST R 0.00ns 0.5ns HCLKPC {part} CST - HCLKAGP R -0.5ns 0.5ns HCLKDIMM(10:0) - HCLKPC {part} CST R -0.5ns 1.0ns HCLKPC {part} CST - PCLKCS R 0.5ns 5.0ns HCLKPC {part} CST - PICCLK R 0.5ns 5.0ns PCICLKs - PCICLKs R -2.0ns 2.0ns | |**************************************************************************** [Edge Sens] | intra inter |net_name mono_rise mono_fall xtalk xtalk SMI# Y Y NA NA NMI Y Y NA NA INTR Y Y NA NA IOR# Y Y NA NA IOW# Y Y NA NA MEMR# Y Y NA NA MEMW# Y Y NA NA BALE Y Y NA NA OSC Y Y NA NA | |**************************************************************************** [End]