Index of /pub/ibis/macromodel_wip/archive/20060117/arpadmuranyiintel/Sample Verilog-A prede-emphasis buffer data

[ICO]NameLast modifiedSizeDescription
[DIR]Parent Directory  -
[ ]IV_data_ODT_GND.dat17-Jan-2006 08:40 416
[ ]IV_data_ODT_Vcc.dat17-Jan-2006 08:40 416
[ ]IV_data_ODT_Vcc_GND.dat17-Jan-2006 08:40 416
[ ]IV_data_no_ODT.dat17-Jan-2006 08:40 416
[TXT]Sample_Verilog-A_prede-emphasis_buffer_data_ziplist.txt22-Jul-2009 16:28 0
[ ]VT_data_ODT_GND.dat17-Jan-2006 08:40 540
[ ]VT_data_ODT_Vcc.dat17-Jan-2006 08:40 540
[ ]VT_data_ODT_Vcc_GND.dat17-Jan-2006 08:40 620
[ ]VT_data_no_ODT.dat17-Jan-2006 08:40 460
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