From owner-ibis Tue Jul  3 15:51:55 2001
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From: "Mohan, Prabhu" <Prabhu.Mohan@actel.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Cc: "'arpad.muranyi@intel.com'" <arpad.muranyi@intel.com>
Subject: Introduction to IBIS Models
Date: Tue, 3 Jul 2001 15:54:35 -0700 
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Hi all,

Is this document (Introduction to IBIS Models) still available from IBIS
website or elsewhere?  Is there any other document that deals with "How to
obtain c_comp?"

Thanks
Prabhu

-----Original Message-----
From: Betty Luk [mailto:Betty@genesis-microchip.com]
Sent: Wednesday, November 29, 2000 11:33 AM
To: 'ibis-users@eda.org'
Cc: 'arpad.muranyi@intel.com'
Subject: measuring c_comp using simulation


Hi,
 
In Arpad Muranyi's "Introduction to IBIS Models" (available from IBIS
website), there was a sample Spice netlist for a simulation to obtain the
value of c_comp.  When I used this simulation for my buffer, the capacitance
ranged from 2pF to 8pF, with a mean of 5pF.  In the example, the range was
only between 2 to 3pF.  Should the mean value for the simulated capacitance
be used?    What about obtaining min and max values for c_comp?
 
I would really appreciate any feedback.  I have attached the sample Spice
file for reference.
 
Thanks very much,
Betty
 
 


------_=_NextPart_000_01C10413.21924B90
Content-Type: application/octet-stream;
	name="c_meter.sp"
Content-Transfer-Encoding: quoted-printable
Content-Disposition: attachment;
	filename="c_meter.sp"

Capacitance meter circuit=0A=
************************************************************************=
***=0A=
.OPTIONS POST=3D1 POST_VERSION=3D9007 ACCURATE NUMDGT=3D8=0A=
.TRAN  0.01ns  '2*dt'  SWEEP  CapV  LIN  'Points+1'  CapV1  CapV2=0A=
************************************************************************=
***=0A=
.PARAM  CapV1   =3D   0.0V=0A=
.PARAM  CapV2   =3D   5.0V=0A=
.PARAM  Points  =3D  20=0A=
.PARAM  dt      =3D  10.0ns=0A=
************************************************************************=
***=0A=
.PARAM  dV      =3D   'CapV2-CapV1'=0A=
.PARAM  Ovh     =3D   0.1=0A=
.PARAM  CapV    =3D   0.0V=0A=
************************************************************************=
***=0A=
.MEAS  TRAN  Sw_I1  FIND  PAR('I(Vsw)')  WHEN  V(Sweep)=3DCapV  =
Rise=3D1=0A=
.MEAS  TRAN  Sw_I2  FIND  PAR('I(Vsw)')  WHEN  V(Sweep)=3DCapV  =
Fall=3D1=0A=
.MEAS  TRAN  CAP    =
PARAM=3D'abs((Sw_I1-Sw_I2)/2*(dt/(dV+2*dV*Ovh)))'=0A=
************************************************************************=
***=0A=
Vvcc  Vcc    0  DC=3D 5.0=0A=
Vsw   Sweep  0  PWL=0A=
+  0ns        'CapV1-dV*Ovh'=0A=
+  dt         'CapV2+dV*Ovh'=0A=
+ '2*dt'      'CapV1-dV*Ovh'=0A=
************************************************************************=
***=0A=
X1 in Sweep Vcc 0 0 IO_buf=0A=
.include "IO_buf.inc"=0A=
Rdum in 0 1e+3=0A=
*=0A=
C1     Sweep   0    C=3D10.0pF               $ Test capacitor =
(constant)=0A=
*C1     Sweep   0    C=3D'10.0e-12*V(sweep)'  $ Test capacitor =
(variable)=0A=
************************************************************************=
***=0A=
.END=0A=

------_=_NextPart_000_01C10413.21924B90--
 
From owner-ibis Tue Jul  3 16:28:19 2001
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Date: Tue, 03 Jul 2001 16:26:51 -0700
To: Kim Helliwell <kimgh@apple.com>
From: Lynne Green <lgreen@cadence.com>
Subject: Re: Combining IBIS models of the same part from different
  vendors
Cc: "ibis-Users@Eda.Org'" <ibis-users@eda.org>
In-Reply-To: <200107032215.f63MFPw19937@scv2.apple.com>
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Kim,

You should be very careful.  Two parts may have the same data sheets, but 
the edge
rates may differ by a factor of 3 or more (and signal integrity will be 
correspondingly
different!).

If possible, SI should be checked using the IBIS model from each vendor 
that you
use as a source for the part.  At the least, check the fastest and slowest 
IBIS
drivers you can encounter on each net.

It is probably safest (from a design data management perspective) to keep 
the IBIS
files separate, and "sweep" the model files in the simulation tool.

-Lynne


At 03:14 PM 7/3/2001 -0700, you wrote:
>One of the difficulties in the IBIS world is: if you are using a part that 
>you buy from several
>vendors, and they each give you an IBIS model for the part, how do you 
>combine these
>files into some sort of composite models (assuming that is desirable at all).
>
>Now, it's easy to look at typ, min, max values for caps and voltages, and 
>figure out
>what to do.  Harder is combining typ, min, and max pullup and pulldowns, 
>or VT curves.
>
>What I'm looking for is a "best practice" for this situation: if you've 
>faced this situation, how have
>you dealt with it?
>
>Of course, maybe nobody has faced this yet, because the other difficulty, 
>of course, is
>finding a part, any part, that has multiple suppliers that all provide 
>IBIS models for them :-)
>But we won't go there this time!
>
>
>Kim Helliwell
>Apple Computer
>kimgh@apple.com
>408 974 9936

--=====================_112265929==_
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Content-Disposition: attachment; filename="BizCard.txt"

Dr. Lynne Green
Senior Member of Consulting Staff
PCB Systems Division
Cadence Design Systems, Inc.
320 120th Ave NE, Suite B-103
Bellevue, WA 98005
Phone: 425-990-1288
FAX: 425-451-1871
lgreen@cadence.com
http://www.cadence.com
--=====================_112265929==_--

 
From owner-ibis Tue Jul  3 17:15:15 2001
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From: Abdulrahman Rafiq <arafiq@cisco.com>
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CC: "'ibis-users@eda.org'" <ibis-users@eda.org>,
   "'arpad.muranyi@intel.com'" <arpad.muranyi@intel.com>
Subject: Re: Introduction to IBIS Models
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Prabhu,

You can find a number of ducments here :

http://www.eia.org/eig/ibis.htm

"Mohan, Prabhu" wrote:

> Hi all,
>
> Is this document (Introduction to IBIS Models) still available from IBIS
> website or elsewhere?  Is there any other document that deals with "How to
> obtain c_comp?"
>
> Thanks
> Prabhu
>
> -----Original Message-----
> From: Betty Luk [mailto:Betty@genesis-microchip.com]
> Sent: Wednesday, November 29, 2000 11:33 AM
> To: 'ibis-users@eda.org'
> Cc: 'arpad.muranyi@intel.com'
> Subject: measuring c_comp using simulation
>
> Hi,
>
> In Arpad Muranyi's "Introduction to IBIS Models" (available from IBIS
> website), there was a sample Spice netlist for a simulation to obtain the
> value of c_comp.  When I used this simulation for my buffer, the capacitance
> ranged from 2pF to 8pF, with a mean of 5pF.  In the example, the range was
> only between 2 to 3pF.  Should the mean value for the simulated capacitance
> be used?    What about obtaining min and max values for c_comp?
>
> I would really appreciate any feedback.  I have attached the sample Spice
> file for reference.
>
> Thanks very much,
> Betty
>
>
>
>   ------------------------------------------------------------------------
>                  Name: c_meter.sp
>    c_meter.sp    Type: unspecified type (application/octet-stream)
>              Encoding: quoted-printable

--
-------------------------------------------------------------------------
--------------------------------------          -             -          |
| Abdulrahman A. Rafiq (AKA Abbey)   |         ---           ---         |
| Hardware Engineer                  |       -------        ------       |
| ISBU, Cisco Systems, Inc.          |     -----------    ----------     |
--------------------------------------   ------------------------------  |
-------------------------------------------------------------------------



--------------77685F77138ED38680D30BFE
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Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Prabhu,
<p>You can find a number of ducments here :
<p><A HREF="http://www.eia.org/eig/ibis.htm">http://www.eia.org/eig/ibis.htm</A>
<p>"Mohan, Prabhu" wrote:
<blockquote TYPE=CITE>Hi all,
<p>Is this document (Introduction to IBIS Models) still available from
IBIS
<br>website or elsewhere?&nbsp; Is there any other document that deals
with "How to
<br>obtain c_comp?"
<p>Thanks
<br>Prabhu
<p>-----Original Message-----
<br>From: Betty Luk [<a href="mailto:Betty@genesis-microchip.com">mailto:Betty@genesis-microchip.com</a>]
<br>Sent: Wednesday, November 29, 2000 11:33 AM
<br>To: 'ibis-users@eda.org'
<br>Cc: 'arpad.muranyi@intel.com'
<br>Subject: measuring c_comp using simulation
<p>Hi,
<p>In Arpad Muranyi's "Introduction to IBIS Models" (available from IBIS
<br>website), there was a sample Spice netlist for a simulation to obtain
the
<br>value of c_comp.&nbsp; When I used this simulation for my buffer, the
capacitance
<br>ranged from 2pF to 8pF, with a mean of 5pF.&nbsp; In the example, the
range was
<br>only between 2 to 3pF.&nbsp; Should the mean value for the simulated
capacitance
<br>be used?&nbsp;&nbsp;&nbsp; What about obtaining min and max values
for c_comp?
<p>I would really appreciate any feedback.&nbsp; I have attached the sample
Spice
<br>file for reference.
<p>Thanks very much,
<br>Betty
<br>&nbsp;
<br>&nbsp;
<p>&nbsp; ------------------------------------------------------------------------
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Name: c_meter.sp
<br>&nbsp;&nbsp; c_meter.sp&nbsp;&nbsp;&nbsp; Type: unspecified type (application/octet-stream)
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Encoding: quoted-printable</blockquote>

<pre>--&nbsp;
-------------------------------------------------------------------------
--------------------------------------&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |
| Abdulrahman A. Rafiq (AKA Abbey)&nbsp;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ---&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ---&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;
| Hardware Engineer&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; -------&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ------&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |
| ISBU, Cisco Systems, Inc.&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; |&nbsp;&nbsp;&nbsp;&nbsp; -----------&nbsp;&nbsp;&nbsp; ----------&nbsp;&nbsp;&nbsp;&nbsp; |
--------------------------------------&nbsp;&nbsp; ------------------------------&nbsp; |&nbsp;
-------------------------------------------------------------------------</pre>
&nbsp;</html>

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From owner-ibis Tue Jul  3 17:20:19 2001
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Date: Tue, 3 Jul 2001 17:19:35 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: Re: Introduction to IBIS Models
To: ibis-users@eda.org, Prabhu.Mohan@actel.com
Cc: arpad.muranyi@intel.com
MIME-Version: 1.0
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It is available under:

http://www.eda.org/pub/ibis/training/

Look at the 00readme.txt file for details.

Syed

> From: "Mohan, Prabhu" <Prabhu.Mohan@actel.com>
> To: "'ibis-users@eda.org'" <ibis-users@eda.org>
> Cc: "'arpad.muranyi@intel.com'" <arpad.muranyi@intel.com>
> Subject: Introduction to IBIS Models
> Date: Tue, 3 Jul 2001 15:54:35 -0700 
> MIME-Version: 1.0
> 
> Hi all,
> 
> Is this document (Introduction to IBIS Models) still available from IBIS
> website or elsewhere?  Is there any other document that deals with "How to
> obtain c_comp?"
> 
> Thanks
> Prabhu
> 
> -----Original Message-----
> From: Betty Luk [mailto:Betty@genesis-microchip.com]
> Sent: Wednesday, November 29, 2000 11:33 AM
> To: 'ibis-users@eda.org'
> Cc: 'arpad.muranyi@intel.com'
> Subject: measuring c_comp using simulation
> 
> 
> Hi,
>  
> In Arpad Muranyi's "Introduction to IBIS Models" (available from IBIS
> website), there was a sample Spice netlist for a simulation to obtain the
> value of c_comp.  When I used this simulation for my buffer, the capacitance
> ranged from 2pF to 8pF, with a mean of 5pF.  In the example, the range was
> only between 2 to 3pF.  Should the mean value for the simulated capacitance
> be used?    What about obtaining min and max values for c_comp?
>  
> I would really appreciate any feedback.  I have attached the sample Spice
> file for reference.
>  
> Thanks very much,
> Betty
>  
>  
> 

 
From owner-ibis Thu Jul  5 05:32:34 2001
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Subject: Re: Combining IBIS models of the same part from different vendors
To: Kim Helliwell <kimgh@apple.com>
Cc: "ibis-Users@Eda.Org'" <ibis-users@eda.org>
From: Adam.Tambone@fairchildsemi.com
Date: Thu, 5 Jul 2001 08:32:22 -0400
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 07/05/2001 08:32:23 AM
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Kim,

Hmmm...  haven't heard of this before although the implementation should be
simple and just a matter of cutting and pasting them together.

Each pin has a model associated with it, so in the pin information section
be sure to correctly map the pin with the model.  If the model information
comes from different IBIS datasheets that is ok as long as you correctly
map the nomenclature such as model names.  Cut and paste the model
information (model name, model type,  DC data, V-t data, parameters, etc. )
and combine into the IBIS datasheet.

[Pin] signal_name          model_name           R_pin     L_pin     C_pin
1     a0                   data_i_vendor1              101m      3.89n     0.15p
2     b0                   data_i_vendor1               81m       3.37n     0.08p
3     a1                   data_i_vendor2               81m       2.56n     0.07p
4     b1                   data_i_vendor2               81m       2.57n     0.07p

[Model]                       data_i_vendor1
Model_type Input
Vinh=2.0
Vinl=0.8
C_comp              7.0p                NA                  NA
|
[Temperature Range] 25                  85                  -40
|
[Voltage Range]     3.30                3.15                3.45
|
[GND Clamp]
   -3.300000E+0   -1.111975E+0   -1.138288E+0   -1.086002E+0
.
.
.
etc

[Model]                       data_i_vendor2
Model_type Input
Vinh=2.0
Vinl=0.8
C_comp              6.0p                NA                  NA
|
[Temperature Range] 25                  85                  -40
|
[Voltage Range]     3.30                3.15                3.45
|
[GND Clamp]
   -3.300000E+0   -1.111975E+0   -1.138288E+0   -1.086002E+0
.
.
.
etc

Hope This Helps,
Adam Tambone






Kim Helliwell <kimgh@apple.com> on 07/03/2001 06:14:41 PM

To:   "ibis-Users@Eda.Org'" <ibis-users@eda.org>
cc:

Subject:  Combining IBIS models of the same part from different vendors


One of the difficulties in the IBIS world is: if you are using a part
that you buy from several
vendors, and they each give you an IBIS model for the part, how do you
combine these
files into some sort of composite models (assuming that is desirable at
all).

Now, it's easy to look at typ, min, max values for caps and voltages,
and figure out
what to do.  Harder is combining typ, min, and max pullup and pulldowns,
or VT curves.

What I'm looking for is a "best practice" for this situation: if you've
faced this situation, how have
you dealt with it?

Of course, maybe nobody has faced this yet, because the other
difficulty, of course, is
finding a part, any part, that has multiple suppliers that all provide
IBIS models for them :-)
But we won't go there this time!


Kim Helliwell
Apple Computer
kimgh@apple.com
408 974 9936




 
From owner-ibis Thu Jul  5 12:28:36 2001
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Date: Thu, 05 Jul 2001 12:28:29 -0700
From: Scott McMorrow <scott@vasthorizons.com>
Organization: SiQual
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To: apanella@molex.com, ibis <ibis-users@eda.org>
Subject: Re: Note on Rev
References: <OF61E59593.F8487DE9-ON86256A80.0068D160@LocalDomain> <3B44BE2A.66F8B488@vasthorizons.com>
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To further clarify:

It would be nice to be able to indent keywords within sections, as is implied
by the Keyword Tree Diagram.  This would lend these files to being more
readable and better structured.

It would also be silly to have the file fail  a golden parser for the column 1
restriction, when most commercial parsers will use the square brackets
as a delimiter for the beginning and ending of a keyword.

regards,

scott



--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com



Scott McMorrow wrote:

> All,
>
> I see no reason why on page 3 of the document the following
> is a requirement:
>
> 3) Keywords must be enclosed in square brackets, [ ] , and must start in column 1
> of the line.
>
> The column 1 requirement seems a bit antiquated to me.
>
> regards,
>
> scott
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
>
> apanella@molex.com wrote:
>
> > <<File: icm0.pdf>>Good Catch Arpad...
> >
> > All...  See attached...  with correct revision number
> >
> > I am sending the doc again... see attached...  I didn't think this correction
> > was worth a revision number.
> >
> > _gus
> >
> > -----Original Message-----
> > From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
> > Sent: Thursday, July 05, 2001 1:35 PM
> > To: apanella
> > Subject: RE: 0.969 attached...
> >
> > The title page still shows rev 0.968...
> >
> > Arpad
> > =======================================
> >
> > -----Original Message-----
> > From: apanella
> > Sent: Thursday, July 05, 2001 1:16 PM
> > To: '"Peters, Stephen" <stephen.peters@intel.com>'; '"Al Davis
> > <aldavis@ieee.org>" <aldavis@ieee.org>'; '"Bob Ross
> > <bob_ross@mentorg.com>" <bob_ross@mentorg.com>'; '"Chris Reid
> > <chris_reid@mentorg.com>" <chris_reid@mentorg.com>'; '"DC Sessions
> > <ibis@lumbercartel.com>" <ibis@lumbercartel.com>'; '"Gerald Bannert
> > <gerald.bannert@icn.siemens.de>" <gerald.bannert@icn.siemens.de>';
> > '"Greg Edlund <gedlund@us.ibm.com>" <gedlund@us.ibm.com>'; '"John Angulo
> > <angulo@hyperlynx.com>" <angulo@hyperlynx.com>'; '"Lynne Green
> > <lgreen@cadence.com>" <lgreen@cadence.com>'; '"Muranyi, Arpad"
> > <arpad.muranyi@intel.com>'; '"Scott McMorrow <scott@vasthorizons.com>"
> > <scott@vasthorizons.com>'; '"Steve Nolan <s-nolan1@ti.com>"
> > <s-nolan1@ti.com>'
> > Subject: RE: 0.969 attached...
> >
> > See attached...
> >
> > The major revision in the attached document is per the last teleconference that
> > I attended.
> >
> > Basically it revolves around making the subparameters in 968 more line an
> > assigned variable as seen in IBISX
> >
> > This was done for both the sub parameters for [Begin Cn Model] and the matrix
> > section.
> >
> > The "matrix" portion probably needs more work.
> >
> > We can use this for review on Tuesday.
> >
> > _gus
> >
> >   ------------------------------------------------------------------------------------------------------------------------------------
> >                Name: ICM0.PDF
> >    ICM0.PDF    Type: Acrobat (application/pdf)
> >            Encoding: base64

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Organization: SiQual
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All,

I see no reason why on page 3 of the document the following
is a requirement:


3) Keywords must be enclosed in square brackets, [ ] , and must start in column 1
of the line.


The column 1 requirement seems a bit antiquated to me.


regards,

scott


--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


apanella@molex.com wrote:

> <<File: icm0.pdf>>Good Catch Arpad...
>
> All...  See attached...  with correct revision number
>
> I am sending the doc again... see attached...  I didn't think this correction
> was worth a revision number.
>
> _gus
>
> -----Original Message-----
> From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
> Sent: Thursday, July 05, 2001 1:35 PM
> To: apanella
> Subject: RE: 0.969 attached...
>
> The title page still shows rev 0.968...
>
> Arpad
> =======================================
>
> -----Original Message-----
> From: apanella
> Sent: Thursday, July 05, 2001 1:16 PM
> To: '"Peters, Stephen" <stephen.peters@intel.com>'; '"Al Davis
> <aldavis@ieee.org>" <aldavis@ieee.org>'; '"Bob Ross
> <bob_ross@mentorg.com>" <bob_ross@mentorg.com>'; '"Chris Reid
> <chris_reid@mentorg.com>" <chris_reid@mentorg.com>'; '"DC Sessions
> <ibis@lumbercartel.com>" <ibis@lumbercartel.com>'; '"Gerald Bannert
> <gerald.bannert@icn.siemens.de>" <gerald.bannert@icn.siemens.de>';
> '"Greg Edlund <gedlund@us.ibm.com>" <gedlund@us.ibm.com>'; '"John Angulo
> <angulo@hyperlynx.com>" <angulo@hyperlynx.com>'; '"Lynne Green
> <lgreen@cadence.com>" <lgreen@cadence.com>'; '"Muranyi, Arpad"
> <arpad.muranyi@intel.com>'; '"Scott McMorrow <scott@vasthorizons.com>"
> <scott@vasthorizons.com>'; '"Steve Nolan <s-nolan1@ti.com>"
> <s-nolan1@ti.com>'
> Subject: RE: 0.969 attached...
>
> See attached...
>
> The major revision in the attached document is per the last teleconference that
> I attended.
>
> Basically it revolves around making the subparameters in 968 more line an
> assigned variable as seen in IBISX
>
> This was done for both the sub parameters for [Begin Cn Model] and the matrix
> section.
>
> The "matrix" portion probably needs more work.
>
> We can use this for review on Tuesday.
>
> _gus
>
>   ------------------------------------------------------------------------------------------------------------------------------------
>                Name: ICM0.PDF
>    ICM0.PDF    Type: Acrobat (application/pdf)
>            Encoding: base64



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adr:;;18735 SW Boones Ferry Road;Tualatin ;OR;97062-3090;USA
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email;internet:scott@siqual.com
title:Principal Engineer
fn:Scott McMorrow
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'Scott McMorrow'" <scott@vasthorizons.com>, apanella@molex.com,
   ibis
	 <ibis-users@eda.org>
Subject: RE: Note on Rev
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Hi Scott:

  The reason for the column 1 requirement lies in the arbitrary length of
the [Notes] field. As IBIS is defined, (implicitly by the golden parser in
Ver 3.2, explicitly in IBIS-X), the [Notes] field ends when the next keyword
is encountered.  However, a real life case arose in which a keyword was used
*within* the note.  The parser encountered it, ended the [Notes] section,
and subsequently bombed on the remaining notes text.  The fix was to
recognize [...] as keyword only when the opening bracket was in column 1.
As I mentioned, this rule was formalized in IBIS-X (which is where the
General Syntax Rules and Guidelines in the connector spec came from).

  Regards,
  Stephen Peters
  Intel Corp.
 

-----Original Message-----
From: Scott McMorrow [mailto:scott@vasthorizons.com]
Sent: Thursday, July 05, 2001 12:21 PM
To: apanella@molex.com; ibis
Subject: Re: Note on Rev


All,

I see no reason why on page 3 of the document the following
is a requirement:


3) Keywords must be enclosed in square brackets, [ ] , and must start in
column 1
of the line.


The column 1 requirement seems a bit antiquated to me.


regards,

scott


--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


apanella@molex.com wrote:

> <<File: icm0.pdf>>Good Catch Arpad...
>
> All...  See attached...  with correct revision number
>
> I am sending the doc again... see attached...  I didn't think this
correction
> was worth a revision number.
>
> _gus
>
> -----Original Message-----
> From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
> Sent: Thursday, July 05, 2001 1:35 PM
> To: apanella
> Subject: RE: 0.969 attached...
>
> The title page still shows rev 0.968...
>
> Arpad
> =======================================
>
> -----Original Message-----
> From: apanella
> Sent: Thursday, July 05, 2001 1:16 PM
> To: '"Peters, Stephen" <stephen.peters@intel.com>'; '"Al Davis
> <aldavis@ieee.org>" <aldavis@ieee.org>'; '"Bob Ross
> <bob_ross@mentorg.com>" <bob_ross@mentorg.com>'; '"Chris Reid
> <chris_reid@mentorg.com>" <chris_reid@mentorg.com>'; '"DC Sessions
> <ibis@lumbercartel.com>" <ibis@lumbercartel.com>'; '"Gerald Bannert
> <gerald.bannert@icn.siemens.de>" <gerald.bannert@icn.siemens.de>';
> '"Greg Edlund <gedlund@us.ibm.com>" <gedlund@us.ibm.com>'; '"John Angulo
> <angulo@hyperlynx.com>" <angulo@hyperlynx.com>'; '"Lynne Green
> <lgreen@cadence.com>" <lgreen@cadence.com>'; '"Muranyi, Arpad"
> <arpad.muranyi@intel.com>'; '"Scott McMorrow <scott@vasthorizons.com>"
> <scott@vasthorizons.com>'; '"Steve Nolan <s-nolan1@ti.com>"
> <s-nolan1@ti.com>'
> Subject: RE: 0.969 attached...
>
> See attached...
>
> The major revision in the attached document is per the last teleconference
that
> I attended.
>
> Basically it revolves around making the subparameters in 968 more line an
> assigned variable as seen in IBISX
>
> This was done for both the sub parameters for [Begin Cn Model] and the
matrix
> section.
>
> The "matrix" portion probably needs more work.
>
> We can use this for review on Tuesday.
>
> _gus
>
>
----------------------------------------------------------------------------
--------------------------------------------------------
>                Name: ICM0.PDF
>    ICM0.PDF    Type: Acrobat (application/pdf)
>            Encoding: base64



 
From owner-ibis Fri Jul  6 08:36:15 2001
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Subject: Re: Note on Rev
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"Peters, Stephen" wrote:
> 
> Hi Scott:
> 
>   The reason for the column 1 requirement lies in the arbitrary length of
> the [Notes] field. As IBIS is defined, (implicitly by the golden parser in
> Ver 3.2, explicitly in IBIS-X), the [Notes] field ends when the next keyword
> is encountered.  However, a real life case arose in which a keyword was used
> *within* the note.  The parser encountered it, ended the [Notes] section,
> and subsequently bombed on the remaining notes text.  The fix was to
> recognize [...] as keyword only when the opening bracket was in column 1.
> As I mentioned, this rule was formalized in IBIS-X (which is where the
> General Syntax Rules and Guidelines in the connector spec came from).

A keyword could also occur at column 1 inside a [Notes] section, so
I think good error messages are the best solution to avoiding misused
reserved words.

I agree with Scott that the column 1 rule seems antiquated (reminds
me of Fortran punch cards beginning in column 7).  A compromise might
be to require the keyword to be the first token on a line, but allow
leading white space.  This would at least allow indentation.

Greg Haynes		  haynes@utmc.aeroflex.com
Aeroflex UTMC Microelectronic Systems
4350 Centennial Blvd           phone: 719 594-8197
Colorado Springs, CO 80907       fax: 719 594-5541
 
From owner-ibis Fri Jul  6 09:45:35 2001
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All,

Gus,

Here are a few more comments:

Comment 1)

For each keyword there is a usage example.  For example, for [Date] the following
example is shown:

    [Date]            July 1, 2000            The latest file revision date


In this usage example a comment is shown, but the comment does not include the
comment character.  I would suggest revising all usage examples as follows:


    [Date]            July 1, 2000            | The latest file revision date


In this way each usage example uses the correct ICM syntax.



Comment 2)

The [Date] and [File Rev] keywords requires a Text String.  Wouldn't it be better to require
specific types of field formats, so that this information could be processed automatically?


regards,

scott


--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


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Date: Fri, 06 Jul 2001 09:44:02 -0700
From: Scott McMorrow <scott@vasthorizons.com>
Organization: SiQual
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All,

I do not like the dual purpose use of the [Source] keyword.  It is used to record the manufacturer's name, and the place and method
from whence the model was created.  This mixes two pieces of information that are both useful.  I  propose addition of another
keyword:

[Part Manufacturer] which can be used to contain the name of the manufacturer of the part.  This will make it very easy to search
for manufacturers in a database of connector models and makes the manufacturer of the part unambiguous.

[Source] then becomes the source of the information for extraction, which might also be some person or organization other than the
connector manufacturer.

regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


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Date: Fri, 06 Jul 2001 09:55:01 -0700
From: Scott McMorrow <scott@vasthorizons.com>
Organization: SiQual
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To: "Peters, Stephen" <stephen.peters@intel.com>
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Subject: Re: Note on Rev
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Stephen,

I have the following suggestions to eliminate this problem:

1) Require that keywords do not appear in any text blocks.  Where a keyword is defined to include the [keyword] syntax.  This would
be an unusual circumstance anyway.  It is highly unlikely that in production models that a [keyword] would appear in a text block
sections.  These sorts of things generally only occur in examples and can be easily removed.

2) Require an [End Block] keyword for all sections with text blocks.


The requirement that keywords begin in column 1 seems more onerous to me than either of these suggestions.  I would "really" like to
be able to use indented structure within all future models to facilitate better understandability.  Also, I would really like to not
have to deal with a stupid parser that spits out my files when somehow I managed to create a model that does not position a keyword
in column 1.


regards,


scott


--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com



"Peters, Stephen" wrote:

> Hi Scott:
>
>   The reason for the column 1 requirement lies in the arbitrary length of
> the [Notes] field. As IBIS is defined, (implicitly by the golden parser in
> Ver 3.2, explicitly in IBIS-X), the [Notes] field ends when the next keyword
> is encountered.  However, a real life case arose in which a keyword was used
> *within* the note.  The parser encountered it, ended the [Notes] section,
> and subsequently bombed on the remaining notes text.  The fix was to
> recognize [...] as keyword only when the opening bracket was in column 1.
> As I mentioned, this rule was formalized in IBIS-X (which is where the
> General Syntax Rules and Guidelines in the connector spec came from).
>
>   Regards,
>   Stephen Peters
>   Intel Corp.
>
>
> -----Original Message-----
> From: Scott McMorrow [mailto:scott@vasthorizons.com]
> Sent: Thursday, July 05, 2001 12:21 PM
> To: apanella@molex.com; ibis
> Subject: Re: Note on Rev
>
> All,
>
> I see no reason why on page 3 of the document the following
> is a requirement:
>
> 3) Keywords must be enclosed in square brackets, [ ] , and must start in
> column 1
> of the line.
>
> The column 1 requirement seems a bit antiquated to me.
>
> regards,
>
> scott
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
>
> apanella@molex.com wrote:
>
> > <<File: icm0.pdf>>Good Catch Arpad...
> >
> > All...  See attached...  with correct revision number
> >
> > I am sending the doc again... see attached...  I didn't think this
> correction
> > was worth a revision number.
> >
> > _gus
> >
> > -----Original Message-----
> > From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
> > Sent: Thursday, July 05, 2001 1:35 PM
> > To: apanella
> > Subject: RE: 0.969 attached...
> >
> > The title page still shows rev 0.968...
> >
> > Arpad
> > =======================================
> >
> > -----Original Message-----
> > From: apanella
> > Sent: Thursday, July 05, 2001 1:16 PM
> > To: '"Peters, Stephen" <stephen.peters@intel.com>'; '"Al Davis
> > <aldavis@ieee.org>" <aldavis@ieee.org>'; '"Bob Ross
> > <bob_ross@mentorg.com>" <bob_ross@mentorg.com>'; '"Chris Reid
> > <chris_reid@mentorg.com>" <chris_reid@mentorg.com>'; '"DC Sessions
> > <ibis@lumbercartel.com>" <ibis@lumbercartel.com>'; '"Gerald Bannert
> > <gerald.bannert@icn.siemens.de>" <gerald.bannert@icn.siemens.de>';
> > '"Greg Edlund <gedlund@us.ibm.com>" <gedlund@us.ibm.com>'; '"John Angulo
> > <angulo@hyperlynx.com>" <angulo@hyperlynx.com>'; '"Lynne Green
> > <lgreen@cadence.com>" <lgreen@cadence.com>'; '"Muranyi, Arpad"
> > <arpad.muranyi@intel.com>'; '"Scott McMorrow <scott@vasthorizons.com>"
> > <scott@vasthorizons.com>'; '"Steve Nolan <s-nolan1@ti.com>"
> > <s-nolan1@ti.com>'
> > Subject: RE: 0.969 attached...
> >
> > See attached...
> >
> > The major revision in the attached document is per the last teleconference
> that
> > I attended.
> >
> > Basically it revolves around making the subparameters in 968 more line an
> > assigned variable as seen in IBISX
> >
> > This was done for both the sub parameters for [Begin Cn Model] and the
> matrix
> > section.
> >
> > The "matrix" portion probably needs more work.
> >
> > We can use this for review on Tuesday.
> >
> > _gus
> >
> >
> ----------------------------------------------------------------------------
> --------------------------------------------------------
> >                Name: ICM0.PDF
> >    ICM0.PDF    Type: Acrobat (application/pdf)
> >            Encoding: base64



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--------------5FCD12DCD15BEF06853ED988--

 
From owner-ibis Fri Jul  6 10:16:33 2001
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'Scott McMorrow'" <scott@vasthorizons.com>, ibis <ibis-users@eda.org>
Subject: RE: Lack of Manufacturer keyword
Date: Fri, 6 Jul 2001 10:16:19 -0700 
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Hi Scott:

  There is a [Manufacture] keyword in the document (see the top of page 10)
and it does as you propose.  You are correct in that the [Source] keyword
should be used only to record the originating source (place and method of
extraction) of the model data.  Note that the wording describing the
[Source] keyword is different than that in the IBIS-X spec.  I'm working
with Gus to clean this up.

  Thanks,
  Stephen


-----Original Message-----
From: Scott McMorrow [mailto:scott@vasthorizons.com]
Sent: Friday, July 06, 2001 9:44 AM
To: ibis
Subject: Lack of Manufacturer keyword


All,

I do not like the dual purpose use of the [Source] keyword.  It is used to
record the manufacturer's name, and the place and method
from whence the model was created.  This mixes two pieces of information
that are both useful.  I  propose addition of another
keyword:

[Part Manufacturer] which can be used to contain the name of the
manufacturer of the part.  This will make it very easy to search
for manufacturers in a database of connector models and makes the
manufacturer of the part unambiguous.

[Source] then becomes the source of the information for extraction, which
might also be some person or organization other than the
connector manufacturer.

regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


 
From owner-ibis Fri Jul  6 10:59:57 2001
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: "'Scott McMorrow'" <scott@vasthorizons.com>,
   "Peters, Stephen"
	 <stephen.peters@intel.com>
Cc: apanella@molex.com, ibis <ibis-users@eda.org>
Subject: RE: Note on Rev
Date: Fri, 6 Jul 2001 10:58:20 -0700 
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Scott,

But what if someone wants to mention a keyword inside comments,
or the disclaimer, etc...?

Arpad
================================================================

-----Original Message-----
From: Scott McMorrow [mailto:scott@vasthorizons.com]
Sent: Friday, July 06, 2001 9:55 AM
To: Peters, Stephen
Cc: apanella@molex.com; ibis
Subject: Re: Note on Rev


Stephen,

I have the following suggestions to eliminate this problem:

1) Require that keywords do not appear in any text blocks.  Where a keyword
is defined to include the [keyword] syntax.  This would
be an unusual circumstance anyway.  It is highly unlikely that in production
models that a [keyword] would appear in a text block
sections.  These sorts of things generally only occur in examples and can be
easily removed.

2) Require an [End Block] keyword for all sections with text blocks.


The requirement that keywords begin in column 1 seems more onerous to me
than either of these suggestions.  I would "really" like to
be able to use indented structure within all future models to facilitate
better understandability.  Also, I would really like to not
have to deal with a stupid parser that spits out my files when somehow I
managed to create a model that does not position a keyword
in column 1.


regards,


scott


--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com



"Peters, Stephen" wrote:

> Hi Scott:
>
>   The reason for the column 1 requirement lies in the arbitrary length of
> the [Notes] field. As IBIS is defined, (implicitly by the golden parser in
> Ver 3.2, explicitly in IBIS-X), the [Notes] field ends when the next
keyword
> is encountered.  However, a real life case arose in which a keyword was
used
> *within* the note.  The parser encountered it, ended the [Notes] section,
> and subsequently bombed on the remaining notes text.  The fix was to
> recognize [...] as keyword only when the opening bracket was in column 1.
> As I mentioned, this rule was formalized in IBIS-X (which is where the
> General Syntax Rules and Guidelines in the connector spec came from).
>
>   Regards,
>   Stephen Peters
>   Intel Corp.
>
>
> -----Original Message-----
> From: Scott McMorrow [mailto:scott@vasthorizons.com]
> Sent: Thursday, July 05, 2001 12:21 PM
> To: apanella@molex.com; ibis
> Subject: Re: Note on Rev
>
> All,
>
> I see no reason why on page 3 of the document the following
> is a requirement:
>
> 3) Keywords must be enclosed in square brackets, [ ] , and must start in
> column 1
> of the line.
>
> The column 1 requirement seems a bit antiquated to me.
>
> regards,
>
> scott
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
>
> apanella@molex.com wrote:
>
> > <<File: icm0.pdf>>Good Catch Arpad...
> >
> > All...  See attached...  with correct revision number
> >
> > I am sending the doc again... see attached...  I didn't think this
> correction
> > was worth a revision number.
> >
> > _gus
> >
> > -----Original Message-----
> > From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
> > Sent: Thursday, July 05, 2001 1:35 PM
> > To: apanella
> > Subject: RE: 0.969 attached...
> >
> > The title page still shows rev 0.968...
> >
> > Arpad
> > =======================================
> >
> > -----Original Message-----
> > From: apanella
> > Sent: Thursday, July 05, 2001 1:16 PM
> > To: '"Peters, Stephen" <stephen.peters@intel.com>'; '"Al Davis
> > <aldavis@ieee.org>" <aldavis@ieee.org>'; '"Bob Ross
> > <bob_ross@mentorg.com>" <bob_ross@mentorg.com>'; '"Chris Reid
> > <chris_reid@mentorg.com>" <chris_reid@mentorg.com>'; '"DC Sessions
> > <ibis@lumbercartel.com>" <ibis@lumbercartel.com>'; '"Gerald Bannert
> > <gerald.bannert@icn.siemens.de>" <gerald.bannert@icn.siemens.de>';
> > '"Greg Edlund <gedlund@us.ibm.com>" <gedlund@us.ibm.com>'; '"John Angulo
> > <angulo@hyperlynx.com>" <angulo@hyperlynx.com>'; '"Lynne Green
> > <lgreen@cadence.com>" <lgreen@cadence.com>'; '"Muranyi, Arpad"
> > <arpad.muranyi@intel.com>'; '"Scott McMorrow <scott@vasthorizons.com>"
> > <scott@vasthorizons.com>'; '"Steve Nolan <s-nolan1@ti.com>"
> > <s-nolan1@ti.com>'
> > Subject: RE: 0.969 attached...
> >
> > See attached...
> >
> > The major revision in the attached document is per the last
teleconference
> that
> > I attended.
> >
> > Basically it revolves around making the subparameters in 968 more line
an
> > assigned variable as seen in IBISX
> >
> > This was done for both the sub parameters for [Begin Cn Model] and the
> matrix
> > section.
> >
> > The "matrix" portion probably needs more work.
> >
> > We can use this for review on Tuesday.
> >
> > _gus
> >
> >
>
----------------------------------------------------------------------------
> --------------------------------------------------------
> >                Name: ICM0.PDF
> >    ICM0.PDF    Type: Acrobat (application/pdf)
> >            Encoding: base64



 
From owner-ibis Fri Jul  6 10:59:28 2001
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'Scott McMorrow'" <scott@vasthorizons.com>,
   "Peters, Stephen"
	 <stephen.peters@intel.com>
Cc: apanella@molex.com, ibis <ibis-users@eda.org>
Subject: RE: Note on Rev
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Hi Scott:

  In regards to point 1) below -- the case I cited was a production file and
not an example.  I find it very reasonable to include something like "To use
this model your simulator must support the [XYZ] keyword" in the notes
section.  I don't think we can forbid someone from doing so.

  On point 2) -- The futures committee has discussed requiring [End] type
keywords for text blocks (in addition to the ones already there for major
sections).  Note that to be consistent an [End Block] keyword would have to
follow [Notes], [Source], [Disclaimer], [Copyright], [Support] and
[Redistribution Text].  I'm not mortally opposed to adding new keywords that
serve only to aid parsing or delimit text, but at some point we end up with
keyword clutter.
  Is the real issue here simply trying to find a way to make a long file
more understandable and/or easily parsable by the human eye? Is indenting
the best way, or are there other ways to get the file to read smoothly?
Understand, I think you raise a legitimate concern. I'm just wondering
what's the best way to solve it, and at what cost.

  Regards,
  Stephen


-----Original Message-----
From: Scott McMorrow [mailto:scott@vasthorizons.com]
Sent: Friday, July 06, 2001 9:55 AM
To: Peters, Stephen
Cc: apanella@molex.com; ibis
Subject: Re: Note on Rev


Stephen,

I have the following suggestions to eliminate this problem:

1) Require that keywords do not appear in any text blocks.  Where a keyword
is defined to include the [keyword] syntax.  This would
be an unusual circumstance anyway.  It is highly unlikely that in production
models that a [keyword] would appear in a text block
sections.  These sorts of things generally only occur in examples and can be
easily removed.

2) Require an [End Block] keyword for all sections with text blocks.


The requirement that keywords begin in column 1 seems more onerous to me
than either of these suggestions.  I would "really" like to
be able to use indented structure within all future models to facilitate
better understandability.  Also, I would really like to not
have to deal with a stupid parser that spits out my files when somehow I
managed to create a model that does not position a keyword
in column 1.


regards,


scott


--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com



"Peters, Stephen" wrote:

> Hi Scott:
>
>   The reason for the column 1 requirement lies in the arbitrary length of
> the [Notes] field. As IBIS is defined, (implicitly by the golden parser in
> Ver 3.2, explicitly in IBIS-X), the [Notes] field ends when the next
keyword
> is encountered.  However, a real life case arose in which a keyword was
used
> *within* the note.  The parser encountered it, ended the [Notes] section,
> and subsequently bombed on the remaining notes text.  The fix was to
> recognize [...] as keyword only when the opening bracket was in column 1.
> As I mentioned, this rule was formalized in IBIS-X (which is where the
> General Syntax Rules and Guidelines in the connector spec came from).
>
>   Regards,
>   Stephen Peters
>   Intel Corp.
>
>
> -----Original Message-----
> From: Scott McMorrow [mailto:scott@vasthorizons.com]
> Sent: Thursday, July 05, 2001 12:21 PM
> To: apanella@molex.com; ibis
> Subject: Re: Note on Rev
>
> All,
>
> I see no reason why on page 3 of the document the following
> is a requirement:
>
> 3) Keywords must be enclosed in square brackets, [ ] , and must start in
> column 1
> of the line.
>
> The column 1 requirement seems a bit antiquated to me.
>
> regards,
>
> scott
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
>
> apanella@molex.com wrote:
>
> > <<File: icm0.pdf>>Good Catch Arpad...
> >
> > All...  See attached...  with correct revision number
> >
> > I am sending the doc again... see attached...  I didn't think this
> correction
> > was worth a revision number.
> >
> > _gus
> >
> > -----Original Message-----
> > From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
> > Sent: Thursday, July 05, 2001 1:35 PM
> > To: apanella
> > Subject: RE: 0.969 attached...
> >
> > The title page still shows rev 0.968...
> >
> > Arpad
> > =======================================
> >
> > -----Original Message-----
> > From: apanella
> > Sent: Thursday, July 05, 2001 1:16 PM
> > To: '"Peters, Stephen" <stephen.peters@intel.com>'; '"Al Davis
> > <aldavis@ieee.org>" <aldavis@ieee.org>'; '"Bob Ross
> > <bob_ross@mentorg.com>" <bob_ross@mentorg.com>'; '"Chris Reid
> > <chris_reid@mentorg.com>" <chris_reid@mentorg.com>'; '"DC Sessions
> > <ibis@lumbercartel.com>" <ibis@lumbercartel.com>'; '"Gerald Bannert
> > <gerald.bannert@icn.siemens.de>" <gerald.bannert@icn.siemens.de>';
> > '"Greg Edlund <gedlund@us.ibm.com>" <gedlund@us.ibm.com>'; '"John Angulo
> > <angulo@hyperlynx.com>" <angulo@hyperlynx.com>'; '"Lynne Green
> > <lgreen@cadence.com>" <lgreen@cadence.com>'; '"Muranyi, Arpad"
> > <arpad.muranyi@intel.com>'; '"Scott McMorrow <scott@vasthorizons.com>"
> > <scott@vasthorizons.com>'; '"Steve Nolan <s-nolan1@ti.com>"
> > <s-nolan1@ti.com>'
> > Subject: RE: 0.969 attached...
> >
> > See attached...
> >
> > The major revision in the attached document is per the last
teleconference
> that
> > I attended.
> >
> > Basically it revolves around making the subparameters in 968 more line
an
> > assigned variable as seen in IBISX
> >
> > This was done for both the sub parameters for [Begin Cn Model] and the
> matrix
> > section.
> >
> > The "matrix" portion probably needs more work.
> >
> > We can use this for review on Tuesday.
> >
> > _gus
> >
> >
>
----------------------------------------------------------------------------
> --------------------------------------------------------
> >                Name: ICM0.PDF
> >    ICM0.PDF    Type: Acrobat (application/pdf)
> >            Encoding: base64



 
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From: Al Davis <aldavis@ieee.org>
To: Scott McMorrow <scott@vasthorizons.com>,
   "Peters, Stephen" <stephen.peters@intel.com>
Subject: Re: Note on Rev
Date: Fri, 6 Jul 2001 11:53:08 -0700
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On Friday 06 July 2001 09:55 am, Scott McMorrow wrote:
> Stephen,
>
> I have the following suggestions to eliminate this problem:
>
> 1) Require that keywords do not appear in any text blocks.  Where a
> keyword is defined to include the [keyword] syntax.  This would be
> an unusual circumstance anyway.  It is highly unlikely that in
> production models that a [keyword] would appear in a text block
> sections.  These sorts of things generally only occur in examples
> and can be easily removed.
>
> 2) Require an [End Block] keyword for all sections with text
> blocks.
>
>
> The requirement that keywords begin in column 1 seems more onerous
> to me than either of these suggestions.  I would "really" like to
> be able to use indented structure within all future models to
> facilitate better understandability.  Also, I would really like to
> not have to deal with a stupid parser that spits out my files when
> somehow I managed to create a model that does not position a
> keyword in column 1.

We discussed this, both in connector and IBIS-X.  The problem is 
backward compatibility.  

Under suggestion #1, this basically prohibits any use of "[" in a 
text block.  This was the original intended way of doing it.  In 
testing, I found that there were too many old files being rejected.

Suggestion #2 is the obviously superior method, except that there are 
lots of files that don't have the end marker, and we want to maintain 
100% backward compatibility.

Still, this does not require that EVERY keyword begin in column 1.  
The restriction could only apply to those terminating a text block, 
or the text block could be terminated by a line containing a "[" as 
the first non-whitespace character, following a blank line.



 
From owner-ibis Fri Jul  6 13:35:10 2001
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From: "Dagostino, Tom" <tom_dagostino@mentorg.com>
To: "'Al Davis'" <aldavis@ieee.org>, Scott McMorrow <scott@vasthorizons.com>,
   "Peters, Stephen" <stephen.peters@intel.com>
Cc: apanella@molex.com, ibis <ibis-users@eda.org>
Subject: RE: Note on Rev
Date: Fri, 6 Jul 2001 13:35:28 -0700 
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What is the backward compatibility problem.  If this applies to Ver 3.3 or later files what is the issue?

Tom Dagostino
Modeling Manager
Mentor Graphics Corp.
SAE
tom_dagostino@mentor.com
503-685-1613


-----Original Message-----
From: Al Davis [mailto:aldavis@ieee.org]
Sent: Friday, July 06, 2001 11:53 AM
To: Scott McMorrow; Peters, Stephen
Cc: apanella@molex.com; ibis
Subject: Re: Note on Rev


On Friday 06 July 2001 09:55 am, Scott McMorrow wrote:
> Stephen,
>
> I have the following suggestions to eliminate this problem:
>
> 1) Require that keywords do not appear in any text blocks.  Where a
> keyword is defined to include the [keyword] syntax.  This would be
> an unusual circumstance anyway.  It is highly unlikely that in
> production models that a [keyword] would appear in a text block
> sections.  These sorts of things generally only occur in examples
> and can be easily removed.
>
> 2) Require an [End Block] keyword for all sections with text
> blocks.
>
>
> The requirement that keywords begin in column 1 seems more onerous
> to me than either of these suggestions.  I would "really" like to
> be able to use indented structure within all future models to
> facilitate better understandability.  Also, I would really like to
> not have to deal with a stupid parser that spits out my files when
> somehow I managed to create a model that does not position a
> keyword in column 1.

We discussed this, both in connector and IBIS-X.  The problem is 
backward compatibility.  

Under suggestion #1, this basically prohibits any use of "[" in a 
text block.  This was the original intended way of doing it.  In 
testing, I found that there were too many old files being rejected.

Suggestion #2 is the obviously superior method, except that there are 
lots of files that don't have the end marker, and we want to maintain 
100% backward compatibility.

Still, this does not require that EVERY keyword begin in column 1.  
The restriction could only apply to those terminating a text block, 
or the text block could be terminated by a line containing a "[" as 
the first non-whitespace character, following a blank line.


 
From owner-ibis Fri Jul  6 14:15:28 2001
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From: Al Davis <aldavis@ieee.org>
To: "Dagostino, Tom" <tom_dagostino@mentorg.com>,
   Scott McMorrow <scott@vasthorizons.com>,
   "Peters, Stephen" <stephen.peters@intel.com>
Subject: Re: Note on Rev
Date: Fri, 6 Jul 2001 14:15:21 -0700
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On Friday 06 July 2001 01:35 pm, Dagostino, Tom wrote:
> What is the backward compatibility problem.  If this applies to Ver
> 3.3 or later files what is the issue?

Here are a few reasons:

1. Some of the old tools will be used to generate new style models, 
by first generating the old style model, then adding the one new 
feature.  They would then need to bring the whole file into 
compliance.

2. Some simulators will be using the new technology (macro language 
based) software to process even the oldest files.  Probably all tools 
newly adding IBIS support will be in this category.  Some of the old 
tools will switch to the new method even for the old files because of 
lower maintenance costs.  For this reason, the new software must 
accomodate the old files.  This is a basic principle in the design of 
the macro language.  This one is easily solved by a "compatibility 
mode" in the software, that accepts the implied block ends.

3. It is my opinion that the new work should concentrate on what does 
not work well in the old standard.  I have not heard many complaints 
about the header section.  It is also my opinion that we should not 
make gratuitous changes.



Having said that, some of the "decisions" were based on what we 
thought public opinion would be.  Now that we have some comments from 
outside the committee, it really is arbitrary and could go either way.
 
From owner-ibis Mon Jul  9 06:45:52 2001
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Date: Fri, 06 Jul 2001 11:42:58 -0700
From: Scott McMorrow <scott@vasthorizons.com>
Organization: SiQual
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To: "Muranyi, Arpad" <arpad.muranyi@intel.com>, ibis <ibis-users@eda.org>
Subject: Re: Note on Rev
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An end block statement would then solve this problem.

Or since this is not a block structured language, it is the blocks themselves
that are anomalous.  To be consistent text blocks should be treated
as comments.

I am quite opposed to simple fixes like column one allignment.  This
is a silly way to solve the real problem, which is that we are trying to
use keywords in places where they should be commented without using
comments.



"Muranyi, Arpad" wrote:

> Scott,
>
> But what if someone wants to mention a keyword inside comments,
> or the disclaimer, etc...?
>
> Arpad
> ================================================================
>
> -----Original Message-----
> From: Scott McMorrow [mailto:scott@vasthorizons.com]
> Sent: Friday, July 06, 2001 9:55 AM
> To: Peters, Stephen
> Cc: apanella@molex.com; ibis
> Subject: Re: Note on Rev
>
> Stephen,
>
> I have the following suggestions to eliminate this problem:
>
> 1) Require that keywords do not appear in any text blocks.  Where a keyword
> is defined to include the [keyword] syntax.  This would
> be an unusual circumstance anyway.  It is highly unlikely that in production
> models that a [keyword] would appear in a text block
> sections.  These sorts of things generally only occur in examples and can be
> easily removed.
>
> 2) Require an [End Block] keyword for all sections with text blocks.
>
> The requirement that keywords begin in column 1 seems more onerous to me
> than either of these suggestions.  I would "really" like to
> be able to use indented structure within all future models to facilitate
> better understandability.  Also, I would really like to not
> have to deal with a stupid parser that spits out my files when somehow I
> managed to create a model that does not position a keyword
> in column 1.
>
> regards,
>
> scott
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
>
> "Peters, Stephen" wrote:
>
> > Hi Scott:
> >
> >   The reason for the column 1 requirement lies in the arbitrary length of
> > the [Notes] field. As IBIS is defined, (implicitly by the golden parser in
> > Ver 3.2, explicitly in IBIS-X), the [Notes] field ends when the next
> keyword
> > is encountered.  However, a real life case arose in which a keyword was
> used
> > *within* the note.  The parser encountered it, ended the [Notes] section,
> > and subsequently bombed on the remaining notes text.  The fix was to
> > recognize [...] as keyword only when the opening bracket was in column 1.
> > As I mentioned, this rule was formalized in IBIS-X (which is where the
> > General Syntax Rules and Guidelines in the connector spec came from).
> >
> >   Regards,
> >   Stephen Peters
> >   Intel Corp.
> >
> >
> > -----Original Message-----
> > From: Scott McMorrow [mailto:scott@vasthorizons.com]
> > Sent: Thursday, July 05, 2001 12:21 PM
> > To: apanella@molex.com; ibis
> > Subject: Re: Note on Rev
> >
> > All,
> >
> > I see no reason why on page 3 of the document the following
> > is a requirement:
> >
> > 3) Keywords must be enclosed in square brackets, [ ] , and must start in
> > column 1
> > of the line.
> >
> > The column 1 requirement seems a bit antiquated to me.
> >
> > regards,
> >
> > scott
> >
> > --
> > Scott McMorrow
> > Principal Engineer
> > SiQual, Signal Quality Engineering
> > 18735 SW Boones Ferry Road
> > Tualatin, OR  97062-3090
> > (503) 885-1231
> > http://www.siqual.com
> >
> > apanella@molex.com wrote:
> >
> > > <<File: icm0.pdf>>Good Catch Arpad...
> > >
> > > All...  See attached...  with correct revision number
> > >
> > > I am sending the doc again... see attached...  I didn't think this
> > correction
> > > was worth a revision number.
> > >
> > > _gus
> > >
> > > -----Original Message-----
> > > From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
> > > Sent: Thursday, July 05, 2001 1:35 PM
> > > To: apanella
> > > Subject: RE: 0.969 attached...
> > >
> > > The title page still shows rev 0.968...
> > >
> > > Arpad
> > > =======================================
> > >
> > > -----Original Message-----
> > > From: apanella
> > > Sent: Thursday, July 05, 2001 1:16 PM
> > > To: '"Peters, Stephen" <stephen.peters@intel.com>'; '"Al Davis
> > > <aldavis@ieee.org>" <aldavis@ieee.org>'; '"Bob Ross
> > > <bob_ross@mentorg.com>" <bob_ross@mentorg.com>'; '"Chris Reid
> > > <chris_reid@mentorg.com>" <chris_reid@mentorg.com>'; '"DC Sessions
> > > <ibis@lumbercartel.com>" <ibis@lumbercartel.com>'; '"Gerald Bannert
> > > <gerald.bannert@icn.siemens.de>" <gerald.bannert@icn.siemens.de>';
> > > '"Greg Edlund <gedlund@us.ibm.com>" <gedlund@us.ibm.com>'; '"John Angulo
> > > <angulo@hyperlynx.com>" <angulo@hyperlynx.com>'; '"Lynne Green
> > > <lgreen@cadence.com>" <lgreen@cadence.com>'; '"Muranyi, Arpad"
> > > <arpad.muranyi@intel.com>'; '"Scott McMorrow <scott@vasthorizons.com>"
> > > <scott@vasthorizons.com>'; '"Steve Nolan <s-nolan1@ti.com>"
> > > <s-nolan1@ti.com>'
> > > Subject: RE: 0.969 attached...
> > >
> > > See attached...
> > >
> > > The major revision in the attached document is per the last
> teleconference
> > that
> > > I attended.
> > >
> > > Basically it revolves around making the subparameters in 968 more line
> an
> > > assigned variable as seen in IBISX
> > >
> > > This was done for both the sub parameters for [Begin Cn Model] and the
> > matrix
> > > section.
> > >
> > > The "matrix" portion probably needs more work.
> > >
> > > We can use this for review on Tuesday.
> > >
> > > _gus
> > >
> > >
> >
> ----------------------------------------------------------------------------
> > --------------------------------------------------------
> > >                Name: ICM0.PDF
> > >    ICM0.PDF    Type: Acrobat (application/pdf)
> > >            Encoding: base64

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


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From owner-ibis Mon Jul  9 06:54:03 2001
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From: Scott McMorrow <scott@vasthorizons.com>
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Stephen,

The issue is three-fold.

1) indenting for readability and maintainability

2) I have a nasty habit of doing cut and pastes where inadvertently a space is
inserted before a line.

3) I really, really , really hate any language that has a column 1 requirement
on philosophical grounds.  Personally, I think that if you design a language that
uses block structure, it should be a block structured language.  Otherwise, blocks
of text should be treated like comments.


regards,

scott


"Peters, Stephen" wrote:

> Hi Scott:
>
>   In regards to point 1) below -- the case I cited was a production file and
> not an example.  I find it very reasonable to include something like "To use
> this model your simulator must support the [XYZ] keyword" in the notes
> section.  I don't think we can forbid someone from doing so.
>
>   On point 2) -- The futures committee has discussed requiring [End] type
> keywords for text blocks (in addition to the ones already there for major
> sections).  Note that to be consistent an [End Block] keyword would have to
> follow [Notes], [Source], [Disclaimer], [Copyright], [Support] and
> [Redistribution Text].  I'm not mortally opposed to adding new keywords that
> serve only to aid parsing or delimit text, but at some point we end up with
> keyword clutter.
>   Is the real issue here simply trying to find a way to make a long file
> more understandable and/or easily parsable by the human eye? Is indenting
> the best way, or are there other ways to get the file to read smoothly?
> Understand, I think you raise a legitimate concern. I'm just wondering
> what's the best way to solve it, and at what cost.
>
>   Regards,
>   Stephen
>
> -----Original Message-----
> From: Scott McMorrow [mailto:scott@vasthorizons.com]
> Sent: Friday, July 06, 2001 9:55 AM
> To: Peters, Stephen
> Cc: apanella@molex.com; ibis
> Subject: Re: Note on Rev
>
> Stephen,
>
> I have the following suggestions to eliminate this problem:
>
> 1) Require that keywords do not appear in any text blocks.  Where a keyword
> is defined to include the [keyword] syntax.  This would
> be an unusual circumstance anyway.  It is highly unlikely that in production
> models that a [keyword] would appear in a text block
> sections.  These sorts of things generally only occur in examples and can be
> easily removed.
>
> 2) Require an [End Block] keyword for all sections with text blocks.
>
> The requirement that keywords begin in column 1 seems more onerous to me
> than either of these suggestions.  I would "really" like to
> be able to use indented structure within all future models to facilitate
> better understandability.  Also, I would really like to not
> have to deal with a stupid parser that spits out my files when somehow I
> managed to create a model that does not position a keyword
> in column 1.
>
> regards,
>
> scott
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
>
> "Peters, Stephen" wrote:
>
> > Hi Scott:
> >
> >   The reason for the column 1 requirement lies in the arbitrary length of
> > the [Notes] field. As IBIS is defined, (implicitly by the golden parser in
> > Ver 3.2, explicitly in IBIS-X), the [Notes] field ends when the next
> keyword
> > is encountered.  However, a real life case arose in which a keyword was
> used
> > *within* the note.  The parser encountered it, ended the [Notes] section,
> > and subsequently bombed on the remaining notes text.  The fix was to
> > recognize [...] as keyword only when the opening bracket was in column 1.
> > As I mentioned, this rule was formalized in IBIS-X (which is where the
> > General Syntax Rules and Guidelines in the connector spec came from).
> >
> >   Regards,
> >   Stephen Peters
> >   Intel Corp.
> >
> >
> > -----Original Message-----
> > From: Scott McMorrow [mailto:scott@vasthorizons.com]
> > Sent: Thursday, July 05, 2001 12:21 PM
> > To: apanella@molex.com; ibis
> > Subject: Re: Note on Rev
> >
> > All,
> >
> > I see no reason why on page 3 of the document the following
> > is a requirement:
> >
> > 3) Keywords must be enclosed in square brackets, [ ] , and must start in
> > column 1
> > of the line.
> >
> > The column 1 requirement seems a bit antiquated to me.
> >
> > regards,
> >
> > scott
> >
> > --
> > Scott McMorrow
> > Principal Engineer
> > SiQual, Signal Quality Engineering
> > 18735 SW Boones Ferry Road
> > Tualatin, OR  97062-3090
> > (503) 885-1231
> > http://www.siqual.com
> >
> > apanella@molex.com wrote:
> >
> > > <<File: icm0.pdf>>Good Catch Arpad...
> > >
> > > All...  See attached...  with correct revision number
> > >
> > > I am sending the doc again... see attached...  I didn't think this
> > correction
> > > was worth a revision number.
> > >
> > > _gus
> > >
> > > -----Original Message-----
> > > From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
> > > Sent: Thursday, July 05, 2001 1:35 PM
> > > To: apanella
> > > Subject: RE: 0.969 attached...
> > >
> > > The title page still shows rev 0.968...
> > >
> > > Arpad
> > > =======================================
> > >
> > > -----Original Message-----
> > > From: apanella
> > > Sent: Thursday, July 05, 2001 1:16 PM
> > > To: '"Peters, Stephen" <stephen.peters@intel.com>'; '"Al Davis
> > > <aldavis@ieee.org>" <aldavis@ieee.org>'; '"Bob Ross
> > > <bob_ross@mentorg.com>" <bob_ross@mentorg.com>'; '"Chris Reid
> > > <chris_reid@mentorg.com>" <chris_reid@mentorg.com>'; '"DC Sessions
> > > <ibis@lumbercartel.com>" <ibis@lumbercartel.com>'; '"Gerald Bannert
> > > <gerald.bannert@icn.siemens.de>" <gerald.bannert@icn.siemens.de>';
> > > '"Greg Edlund <gedlund@us.ibm.com>" <gedlund@us.ibm.com>'; '"John Angulo
> > > <angulo@hyperlynx.com>" <angulo@hyperlynx.com>'; '"Lynne Green
> > > <lgreen@cadence.com>" <lgreen@cadence.com>'; '"Muranyi, Arpad"
> > > <arpad.muranyi@intel.com>'; '"Scott McMorrow <scott@vasthorizons.com>"
> > > <scott@vasthorizons.com>'; '"Steve Nolan <s-nolan1@ti.com>"
> > > <s-nolan1@ti.com>'
> > > Subject: RE: 0.969 attached...
> > >
> > > See attached...
> > >
> > > The major revision in the attached document is per the last
> teleconference
> > that
> > > I attended.
> > >
> > > Basically it revolves around making the subparameters in 968 more line
> an
> > > assigned variable as seen in IBISX
> > >
> > > This was done for both the sub parameters for [Begin Cn Model] and the
> > matrix
> > > section.
> > >
> > > The "matrix" portion probably needs more work.
> > >
> > > We can use this for review on Tuesday.
> > >
> > > _gus
> > >
> > >
> >
> ----------------------------------------------------------------------------
> > --------------------------------------------------------
> > >                Name: ICM0.PDF
> > >    ICM0.PDF    Type: Acrobat (application/pdf)
> > >            Encoding: base64

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


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n:McMorrow;Scott
tel;work:503-239-4400
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--------------5EC0E63348F8ED21BA4C3032--

 
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Date: Tue, 10 Jul 2001 00:21:21 -0700
From: Scott McMorrow <scott@vasthorizons.com>
Organization: SiQual
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To: gus panella <databits@earthlink.net>, gus panella <apanella@molex.com>,
   ibis <ibis-users@eda.org>
Subject: SiQual comments on ICM 0.969 specification
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Gus and all,

Please find SiQual's comments on the ICM specfication
attached.  There are quite a few issues which will need to
be addressed.  Our comments are in bold in the attached
file.

I will try to call in for the meeting.


regards,

scott


--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


--------------734BB913D49B55307BF7DB45
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Content-Type: text/x-vcard; charset=us-ascii;
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Content-Transfer-Encoding: 7bit
Content-Description: Card for Scott McMorrow
Content-Disposition: attachment;
 filename="scott.vcf"

begin:vcard 
n:McMorrow;Scott
tel;work:503-239-4400
x-mozilla-html:TRUE
url:www.siqual.com
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All,

I would like to initiate a discussion for ICM concerning connectors
that can be split into multiple mating connectors.   Examples of
this are pcb headers that can accomodate two or more mating
connectors.  Edge card connectors with multiple blades which
plug into multiple backplane mates ... etc.

In each of these cases, the connector on one subsystem has
a larger number of pins than each of the mated subsystems, and
multiple subsystems can be mated simultaneously.  Without
an ability to take a large connector  and split it from one side to
the other, it is not possible to automatically map connector models
across a connector in a CAD system.

I would propose a connector [Split] keyword that allows a
connector to be split into multiple smaller mating ports.  A
[Split] would be a new type of mapping function which allows
for one input port and multiple output ports.  It might look like this:

[SplitMap] MateNumber1
Side1            PinSide1       Side2                PinSide2
ModelMapName1    A1             ModelMapName2        A1
ModelMapName1    A2             ModelMapName2        A2
[End SplitMap] MateNumber1

[SplitMap] MateNumber2
ModelMapName1    A20            ModelMapName3        A1
ModelMapName2    A21            ModelMapName3        A2
...
[End SplitMap] MateNumber2

Matrices on the "left" or "input" side of the split would be of the same
size as ModelMapName1 implys.

Matrices on the "right" or "output" side of the split would be of the same
size as the ModelMapName2 or 3 implys.

It is assumed that the ports on the split side of the connector are isolated
and as such no coupling exists across the split boundary.  This is the
case for many real connector systems, but may pose a limitation for some
more complex systems.

With a [SplitMap] defined, a split could be accomplished in the following
way (Do see my comments on the current ICM specification regarding
[Begin Cn Model] blocks to understand the proposed changes I have made
to attach multiple ports to sections.  In this case, a Split - EndSplit block is
similar to a Fork - Endfork block):

Split Example :  (a simple two line model with one section split to two ports)

[Begin Cn Model] MyExample1
  Cn_Model_Type = SLM
  Model_Name = MyModel1
  Model_PinMap = MyModelPinMapA
  Model_PinMap = MyModelPinMapB
  Model_PinMap = MyModelPinMapC
  GSR = 3:1
  MyModelPinMapA
  Cn_Section 1.0 Diagonal_matrix1
  Split MateNumber1
      Cn_Section 1.0 Diagonal_matrix2
      MyModelPinMapB
  EndSplit MateNumber1
  Split MateNumber2
     Cn_Section 1.0 Diagonal_matrix2
     MyModelPinMapC
  EndSplit MateNumber2
[End Cn Model] MyExample1



There may be a more elegant way of doing this.
Your comments are welcome.


regards,


scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com


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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
All,
<p>I would like to initiate a discussion for ICM concerning connectors
<br>that can be split into multiple mating connectors.&nbsp;&nbsp; Examples
of
<br>this are pcb headers that can accomodate two or more mating
<br>connectors.&nbsp; Edge card connectors with multiple blades which
<br>plug into multiple backplane mates ... etc.
<p>In each of these cases, the connector on one subsystem has
<br>a larger number of pins than each of the mated subsystems, and
<br>multiple subsystems can be mated simultaneously.&nbsp; Without
<br>an ability to take a large connector&nbsp; and split it from one side
to
<br>the other, it is not possible to automatically map connector models
<br>across a connector in a CAD system.
<p>I would propose a connector [Split] keyword that allows a
<br>connector to be split into multiple smaller mating ports.&nbsp; A
<br>[Split] would be a new type of mapping function which allows
<br>for one input port and multiple output ports.&nbsp; It might look like
this:
<p><tt>[SplitMap] MateNumber1</tt>
<br><tt>Side1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
PinSide1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Side2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
PinSide2</tt>
<br><tt>ModelMapName1&nbsp;&nbsp;&nbsp; A1&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
ModelMapName2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; A1</tt>
<br><tt>ModelMapName1&nbsp;&nbsp;&nbsp; A2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
ModelMapName2&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; A2</tt>
<br><tt>[End SplitMap] MateNumber1</tt><tt></tt>
<p><tt>[SplitMap] MateNumber2</tt>
<br><tt>ModelMapName1&nbsp;&nbsp;&nbsp; A20&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
ModelMapName3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; A1</tt>
<br><tt>ModelMapName2&nbsp;&nbsp;&nbsp; A21&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
ModelMapName3&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; A2</tt>
<br><tt>...</tt>
<br><tt>[End SplitMap] MateNumber2</tt><tt></tt>
<p>Matrices on the "left" or "input" side of the split would be of the
same
<br>size as ModelMapName1 implys.
<p>Matrices on the "right" or "output" side of the split would be of the
same
<br>size as the ModelMapName2 or 3 implys.
<p>It is assumed that the ports on the split side of the connector are
isolated
<br>and as such no coupling exists across the split boundary.&nbsp; This
is the
<br>case for many real connector systems, but may pose a limitation for
some
<br>more complex systems.
<p>With a [SplitMap] defined, a split could be accomplished in the following
<br>way (Do see my comments on the current ICM specification regarding
<br>[Begin Cn Model] blocks to understand the proposed changes I have made
<br>to attach multiple ports to sections.&nbsp; In this case, a Split -
EndSplit block is
<br>similar to a Fork - Endfork block):
<p><tt>Split Example :&nbsp; (a simple two line model with one section
split to two ports)</tt><tt></tt>
<p><tt>[Begin Cn Model] MyExample1</tt>
<br><tt>&nbsp; Cn_Model_Type = SLM</tt>
<br><tt>&nbsp; Model_Name = MyModel1</tt>
<br><tt>&nbsp; Model_PinMap = MyModelPinMapA</tt>
<br><tt>&nbsp; Model_PinMap = MyModelPinMapB</tt>
<br><tt>&nbsp; Model_PinMap = MyModelPinMapC</tt>
<br><tt>&nbsp; GSR = 3:1</tt>
<br><tt>&nbsp; MyModelPinMapA</tt>
<br><tt>&nbsp; Cn_Section 1.0 Diagonal_matrix1</tt>
<br><tt>&nbsp; Split MateNumber1</tt>
<br><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Cn_Section 1.0 Diagonal_matrix2</tt>
<br><tt>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MyModelPinMapB</tt>
<br><tt>&nbsp; EndSplit MateNumber1</tt>
<br><tt>&nbsp; Split MateNumber2</tt>
<br><tt>&nbsp;&nbsp;&nbsp;&nbsp; Cn_Section 1.0 Diagonal_matrix2</tt>
<br><tt>&nbsp;&nbsp;&nbsp;&nbsp; MyModelPinMapC</tt>
<br><tt>&nbsp; EndSplit MateNumber2</tt>
<br><tt>[End Cn Model] MyExample1</tt>
<br>&nbsp;
<br>&nbsp;<tt></tt>
<p>There may be a more elegant way of doing this.
<br>Your comments are welcome.
<br>&nbsp;
<p>regards,
<br>&nbsp;
<p>scott
<p>--
<br>Scott McMorrow
<br>Principal Engineer
<br>SiQual, Signal Quality Engineering
<br>18735 SW Boones Ferry Road
<br>Tualatin, OR&nbsp; 97062-3090
<br>(503) 885-1231
<br><A HREF="http://www.siqual.com">http://www.siqual.com</A>
<br>&nbsp;</html>

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Date: Wed, 11 Jul 2001 12:15:06 -0700
From: Prasad Rau <prasad.rau@xilinx.com>
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Hi,

I am modelling onchip termination for certain IO standards and unfortunately the [POWER_clamp] curve
puts out information from -VDD to 0v. The region of interest( termination effects) is 0v to +VDD. Is there a way to input information
( without modifying the source code of the simulator ) such that the IBIS file spits out -VDD to +VDD in the
[POWER_clamp] curve. By the way, the termination is modelled as a split termination ie 50 Ohms to VDD and
50 Ohms to GND. These are not passive devices but active( transistors) devices.

Thanks in advance,

Regards,

Prasad Rau
Xilinx

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From owner-ibis Wed Jul 11 13:00:14 2001
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To: Prasad Rau <prasad.rau@xilinx.com>
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Prasad,

The numbers in an IBIS POWER_clamp curve will go from -VDD to 0V,
but this is because they are relative to VDD and inverted. They
are not absolute voltages. Basically, positive voltage values
in the POWER_clamp curve correspond to actual voltages below VDD,
and negative curve voltage values correspond to actual voltages
above VDD.

You can extend the data into the positive region to model a
terminator, and I believe any IBIS simulator will simulate the
entire curve as expected.

Mike

Prasad Rau wrote:
> 
> Hi,
> 
> I am modelling onchip termination for certain IO standards and unfortunately the [POWER_clamp] curve
> puts out information from -VDD to 0v. The region of interest( termination effects) is 0v to +VDD. Is there a way to input information
> ( without modifying the source code of the simulator ) such that the IBIS file spits out -VDD to +VDD in the
> [POWER_clamp] curve. By the way, the termination is modelled as a split termination ie 50 Ohms to VDD and
> 50 Ohms to GND. These are not passive devices but active( transistors) devices.
> 
> Thanks in advance,
> 
> Regards,
> 
> Prasad Rau
> Xilinx
 
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Date: Wed, 11 Jul 2001 15:54:40 -0700
From: Bob Ross <bob_ross@mentorg.com>
Organization: Mentor Graphics Corporation
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Prasad:

To add to Mike LaBonte's response, it is permissible
to extend both [Gnd Clamp] and [Power Clamp] tables over
the full -vdd to 2*Vdd range.  For internal terminators,
this would be a good idea.

If you have ideal 50 ohm resistors to Gnd and also to
Vdd, the [Gnd Clamp] and [Power Clamp] tables might
look like this for Vdd = 3.3 V:

[Gnd Clamp]
-3.3 -66ma  -66ma  -66ma
0      0      0      0
6.6  132ma  132ma  132ma

[Power Clamp]
-3.3  66ma   66ma   66ma
0      0      0      0
6.6 -132ma -132ma -132ma

For your active devices, you would need to find a
method to extract the actual (transistor) table
information and to properly decompose the extracted
information into the two tables.

A presentation that proposes improvements to
s2ibis2 for internal termination situations was
given under:

  http://www.eda.org/pub/ibis/summits/oct99/nasef.zip

Bob Ross
Mentor Graphics

> Prasad Rau wrote:
> 
> Hi,
> 
> I am modelling onchip termination for certain IO standards and unfortunately
> the [POWER_clamp] curve
> puts out information from -VDD to 0v. The region of interest( termination
> effects) is 0v to +VDD. Is there a way to input information
> 
> ( without modifying the source code of the simulator ) such that the IBIS file
> spits out -VDD to +VDD in the
> [POWER_clamp] curve. By the way, the termination is modelled as a split
> termination ie 50 Ohms to VDD and
> 50 Ohms to GND. These are not passive devices but active( transistors)
> devices.
> 
> Thanks in advance,
> 
> Regards,
> 
> Prasad Rau
> Xilinx
> 
>
 
From owner-ibis Wed Jul 11 16:35:02 2001
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Bob,

I found out that Prasad's issue is indeed how to get s2ibis2
to produce an IBIS file where drivers with internal termination.
My proposed workaround is run s2ibis2 twice, once with model type
Terminator, and steal the clamp curves to use in the other IBIS
file. But I tried it and found that s2ibis2 seems to double count
the resistance, because it appears in both the POWER_clamp and
GND_clamp curves. Does it seem reasonable to steal only one of
the curves from the Terminator run to include in the IBIS file?

Mike

P.S. I find that the Nasef presentation contains unresolved
     references to image files.

Bob Ross wrote:
> 
> Prasad:
> 
> To add to Mike LaBonte's response, it is permissible
> to extend both [Gnd Clamp] and [Power Clamp] tables over
> the full -vdd to 2*Vdd range.  For internal terminators,
> this would be a good idea.
> 
> If you have ideal 50 ohm resistors to Gnd and also to
> Vdd, the [Gnd Clamp] and [Power Clamp] tables might
> look like this for Vdd = 3.3 V:
> 
> [Gnd Clamp]
> -3.3 -66ma  -66ma  -66ma
> 0      0      0      0
> 6.6  132ma  132ma  132ma
> 
> [Power Clamp]
> -3.3  66ma   66ma   66ma
> 0      0      0      0
> 6.6 -132ma -132ma -132ma
> 
> For your active devices, you would need to find a
> method to extract the actual (transistor) table
> information and to properly decompose the extracted
> information into the two tables.
> 
> A presentation that proposes improvements to
> s2ibis2 for internal termination situations was
> given under:
> 
>   http://www.eda.org/pub/ibis/summits/oct99/nasef.zip
> 
> Bob Ross
> Mentor Graphics
> 
> > Prasad Rau wrote:
> >
> > Hi,
> >
> > I am modelling onchip termination for certain IO standards and unfortunately
> > the [POWER_clamp] curve
> > puts out information from -VDD to 0v. The region of interest( termination
> > effects) is 0v to +VDD. Is there a way to input information
> >
> > ( without modifying the source code of the simulator ) such that the IBIS file
> > spits out -VDD to +VDD in the
> > [POWER_clamp] curve. By the way, the termination is modelled as a split
> > termination ie 50 Ohms to VDD and
> > 50 Ohms to GND. These are not passive devices but active( transistors)
> > devices.
> >
> > Thanks in advance,
> >
> > Regards,
> >
> > Prasad Rau
> > Xilinx
> >
> >
 
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Mike:

The proper way is to improve the s2ibis2 utility or
the surrounding processes as you attempted to do.

I was able to download and read the nasef.zip file.
I can send you privately a copy if you have trouble.

More responses are in your response.

Bob
Mentor Graphics

> Mike LaBonte wrote:
> 
> Bob,
> 
> I found out that Prasad's issue is indeed how to get s2ibis2
> to produce an IBIS file where drivers with internal termination.
> My proposed workaround is run s2ibis2 twice, once with model type
> Terminator, and steal the clamp curves to use in the other IBIS
> file. But I tried it and found that s2ibis2 seems to double count
> the resistance, because it appears in both the POWER_clamp and
> GND_clamp curves.

This may be a flaw in the s2ibis2 algorithms.  Also, s2ibis2
never was designed to handle internal terminators.

> Does it seem reasonable to steal only one of
> the curves from the Terminator run to include in the IBIS file?

No.  The proper method is to figure out a way to partition
the currents to the proper rails.

> 
> Mike
> 
> P.S. I find that the Nasef presentation contains unresolved
>      references to image files.
> 
> Bob Ross wrote:
> >
 
From owner-ibis Thu Jul 12 10:32:21 2001
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: "'Bob Ross'" <bob_ross@mentorg.com>, Mike LaBonte <mike@labonte.com>
Cc: Prasad Rau <prasad.rau@xilinx.com>, ibis-users@eda.org
Subject: RE: Question regarding the [POWER_clamp] curve
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Mike,

The algorithm s2ibis would need to do is described in my IBIS
Modeling class presentation on pages 78-81.  You can find
this presentation IBIS_class_JEDEC.pdf on the IBIS web site:

http://www.eda.org/pub/ibis/training/

inside the IBIS_class_JEDEC.zip file.  I hope this helps.

Arpad
=============================================================

-----Original Message-----
From: Bob Ross [mailto:bob_ross@mentorg.com]
Sent: Wednesday, July 11, 2001 5:09 PM
To: Mike LaBonte
Cc: Bob Ross; Prasad Rau; ibis-users@eda.org
Subject: Re: Question regarding the [POWER_clamp] curve


Mike:

The proper way is to improve the s2ibis2 utility or
the surrounding processes as you attempted to do.

I was able to download and read the nasef.zip file.
I can send you privately a copy if you have trouble.

More responses are in your response.

Bob
Mentor Graphics

> Mike LaBonte wrote:
> 
> Bob,
> 
> I found out that Prasad's issue is indeed how to get s2ibis2
> to produce an IBIS file where drivers with internal termination.
> My proposed workaround is run s2ibis2 twice, once with model type
> Terminator, and steal the clamp curves to use in the other IBIS
> file. But I tried it and found that s2ibis2 seems to double count
> the resistance, because it appears in both the POWER_clamp and
> GND_clamp curves.

This may be a flaw in the s2ibis2 algorithms.  Also, s2ibis2
never was designed to handle internal terminators.

> Does it seem reasonable to steal only one of
> the curves from the Terminator run to include in the IBIS file?

No.  The proper method is to figure out a way to partition
the currents to the proper rails.

> 
> Mike
> 
> P.S. I find that the Nasef presentation contains unresolved
>      references to image files.
> 
> Bob Ross wrote:
> >

 
From owner-ibis Fri Jul 20 10:25:56 2001
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From: Alan Hilton-Nickel <ahilton@transmeta.com>
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To: Al Davis <aldavis@ieee.org>
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   ibis <ibis-users@eda.org>
Subject: Re: Note on Rev
References: <7FD5C79AD680D211AC4100A0C96B501C084A7872@orsmsx49.jf.intel.com> <3B45ED65.51A21F55@vasthorizons.com> <01070611530801.00805@spiff.c207-202-218-223.sea1.cablespeed.com>
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I'm glad the IBIS and IBIS-X committes are looking at backward
compatibility. 

However, there is a required keyword in the IBIS spec called [IBIS ver].
Seems to me it should be pretty straightforward for a parser to treat
old files as requiring the column 1 limitation, while allowing and [End
Notes] keyword at the end of a [Notes] section in future versions.

Thanks for bringing this up, Scott. This limitation has bugged me for a
while, as it has anyone with a programming background (which should be
the majority of us!)

Alan Hilton-Nickel
Transmeta Corp.

Al Davis wrote:
> 
> On Friday 06 July 2001 09:55 am, Scott McMorrow wrote:
> ? Stephen,
> ?
> ? I have the following suggestions to eliminate this problem:
> ?
> ? 1) Require that keywords do not appear in any text blocks.  Where a
> ? keyword is defined to include the [keyword] syntax.  This would be
> ? an unusual circumstance anyway.  It is highly unlikely that in
> ? production models that a [keyword] would appear in a text block
> ? sections.  These sorts of things generally only occur in examples
> ? and can be easily removed.
> ?
> ? 2) Require an [End Block] keyword for all sections with text
> ? blocks.
> ?
> ?
> ? The requirement that keywords begin in column 1 seems more onerous
> ? to me than either of these suggestions.  I would "really" like to
> ? be able to use indented structure within all future models to
> ? facilitate better understandability.  Also, I would really like to
> ? not have to deal with a stupid parser that spits out my files when
> ? somehow I managed to create a model that does not position a
> ? keyword in column 1.
> 
> We discussed this, both in connector and IBIS-X.  The problem is
> backward compatibility.
> 
> Under suggestion #1, this basically prohibits any use of "[" in a
> text block.  This was the original intended way of doing it.  In
> testing, I found that there were too many old files being rejected.
> 
> Suggestion #2 is the obviously superior method, except that there are
> lots of files that don't have the end marker, and we want to maintain
> 100% backward compatibility.
> 
> Still, this does not require that EVERY keyword begin in column 1.
> The restriction could only apply to those terminating a text block,
> or the text block could be terminated by a line containing a "[" as
> the first non-whitespace character, following a blank line.
 
From owner-ibis Mon Jul 23 18:36:07 2001
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Message-ID: <00c001c113e1$4b671260$14180b0a@huawei.com>
From: "LiuWeidong" <liuweidong@huawei.com>
To: "Gregory R Edlund" <gedlund@us.ibm.com>
Cc: <ibis-users@eda.org>, <ibis@eda.org>
References: <OF78FED261.F9155C6F-ON86256A56.0045F72D@rchland.ibm.com>
Subject: about  the  IBIS  "checklist.txt."  
Date: Tue, 24 Jul 2001 09:38:09 +0800
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Hello, Greg
I have some questions about your IBIS Datasheet Checklist :

"3. Has the modeling engineer performed a visual inspection of IV and  VT  curves to screen for non-monotonicity, discontinuities, and other obvious errors?"
If a IV curves is non-monotonicity,How can  I deal with it ? Can the model be uesd by the simulation tools? 
There are so many  IBIS models provided by IC venders whose IV curves is non-monotonicity  .

"8. Does the output reach Vmeas under standard load conditions for   rising   and falling waveforms?"
For this item , I don't think it should be in the IBIS Datasheet Checklist , Whether the output can reach Vmeas under standard load conditions for   rising   and falling waveforms mainly depend on the output buffer's driving  capability . If a  buffer's driving  capability is very weak, the output  maybe can't  reach Vmeas under standard load conditions for   rising   and falling waveforms,but you can't think the IBIS model is wrong.

Hope for your reply!
Thanks!
LiuWeidong


----- Original Message ----- 
From: Gregory R Edlund <gedlund@us.ibm.com>
To: <Anbu@scmmicro.co.in>
Cc: <ibis-users@vhdl.org>
Sent: Thursday, May 24, 2001 8:53 PM
Subject: Re: Clarification needed.


> 
> Anbazhagan,
> 
> Looks like you're on the right track.  I would recommend your ASIC vendor
> read the "IBIS Cookbook," which can be found on the IBIS web page:
> http://www.eigroup.org/ibis/tools.htm
> 
> As part of the "I/O Buffer Accuracy Handbook" (also available on the IBIS
> web page), we published a checklist that should help you.  This list was
> compiled from suggestions by members of the SI community who have
> experience with IBIS.  I am attaching the most recent version of this list.
> 
> Bob, Could you please post this list as an ASCII text file under Accuracy?
> Pleas name it "checklist.txt."  Thanks.
> 
> 
> IBIS Datasheet Checklist                                  version 1.1,
> 05/07/01
> ------------------------
> 
> 
> IBIS datasheet:
> Component manufacturer:
> Component part number:
> Engineer verifying this component:
> Email address:
> Behavioral simulator and version:
> Date:
> 
> 
> Note:   If answer is N or N/A, provide explanation.
>         The user may verify items 1-9 but is unable to verify items 10-20
>         because the data involved are only available to the semiconductor
>         vendor.
> 
> 
> ___  1. Does the IBIS datasheet pass the IBIS syntax checker?
>         (Note: Some models generate warnings for non-monotonicities that
> are
>         actually part of the characteristics of the device. Other non-
>         monotonicities are so small as to be irrelevant.)
> 
> ___  2. Is an "I/O Buffer Accuracy Report" available for this component?
>         (http://www.vhdl.org/pub/ibis/accuracy)
> 
> ___  3. Has the modeling engineer performed a visual inspection of IV and
> VT
>         curves to screen for non-monotonicity, discontinuities, and other
>         obvious errors?
> 
> ___  4. Has the modeling engineer tested the IBIS datasheet using a
> behavioral
>         simulator?
> 
> ___  5. Do MIN and MAX data exist for all keywords and sub-parameters?
> 
> ___  6. Does the IBIS datasheet include all four 50 Ohm VT tables as
> described
>         in the IBIS Cookbook?
> 
> ___  7. Do the keywords Cref, Rref, Vref, and Vmeas match the values
> specified
>         in the component datasheet for all output and bidirectional models?
> 
> ___  8. Does the output reach Vmeas under standard load conditions for
> rising
>         and falling waveforms?
> 
> ___  9. Does the pin table match the component datasheet?
> 
> 
> ___ 10. Do the keywords Vihl and Vinh represent the unity gain points
> derived
>         from the dc transfer characteristics for all inputs?
> 
> ___ 11. Has the modeling engineer verified the accuracy of the C_comp
>         subparameter?
> 
> ___ 12. Has the modeling engineer verified the accuracy of the R_pkg,
> L_pkg,
>         and C_pkg subparameters?
> 
> ___ 13. For CMOS logic, do all MAX data represent maximum voltage, minimum
>         temperature, and fast process?
> 
> ___ 14. For CMOS logic, do all MIN data represent minimum voltage, maximum
>         temperature, and slow process?
> 
> ___ 15. For bipolar logic, do all MAX data represent maximum voltage,
> maximum
>         temperature, and fast process?
> 
> ___ 16. For bipolar logic, do all MIN data represent minimum voltage,
> minimum
>         temperature, and slow process?
> 
> ___ 17. Do the keywords dV/dt_r and dV/dt_f contain the correct 20%-80%
> edge
>         rate data measured using a 50 & load as specified in IBIS?
> 
> ___ 18. If the I/O buffer employs dynamic clamping, does the IBIS datasheet
>         contain the appropriate keywords and subparameters?
> 
> ___ 19. If the I/O buffer employs a multi-stage driver, does the IBIS
> datasheet
>         contain the appropriate keywords and subparameters?
> 
> ___ 20. If the I/O buffer design employs dynamic edge rate control, dynamic
>         impedance control, or any form of feedback, has the modeling
> engineer
>         assessed the impact of this circuitry on behavioral model accuracy?
> 
> 
> Greg Edlund
> Electrical Packaging
> IBM Server Technology Development
> 3605 Hwy. 52 N, Dept. HDC
> Rochester, MN 55901
> gedlund@us.ibm.com
> 
> 
> Anbu@scmmicro.co.in on 05/24/2001 01:48:13 AM
> 
> To:   "ibis-users@eda.org":
> cc:
> Subject:  Clarification needed.
> 
> 
> 
> Hello Users,
> 
>         I am using XTK to simulate a PCBA. The board has a 100pin ASIC.  In
> order to model the ASIC properly I need the IBIS model of the ASIC which I
> can convert it to XTK format. Now if I directly request for an IBIS model
> the vendor may hesistate. So I am requesting the following data from the
> vendor with which I can create a IBIS model. Below is the data I am
> requesting them. Is it OK. Does it cover everything necessary to create a
> proper IBIS model?. The ASIC does not have any clamp diodes. Please reply.
> The following data whichever is applicable for each pin of the ASIC are
> needed
>  1. Package parasitics namely, the Resistance, capacitance and Inductance.
> Typical, max, min values required.
> 
> 2. Die capacitance as seen at the die pad. Typical, max, min values
> required
> 
> 3. Output impedance of the I/O buffers. Typical, max, min values required.
> 
> 4. Rise time and fall time values (dv/dt typical, max, min) of buffers
> excluding the effect of packaging but including the effect of die
> capacitance. Load conditions required.
> 
> 6. Rising edge and falling edge waveforms (Voltage vs. time curve with the
> voltage values having typical, max, min values) of the driver along with
> the test conditions.
> 
> 5. V/I characteristics of Pull up and Pull down resistor, if present, when
> the buffer is driven high and low respectively. The voltage sweep must be
> from ?3.3V to +6.6V. Current measurement with typical, max, min values are
> required.
> 
> Thanks,
> 
> Anbazhagan.
> 
> 
> 
> 
> 
> 
 
From owner-ibis Tue Jul 24 06:45:44 2001
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From: "Yaping Zhou" <y.zhou@motorola.com>
To: <ibis-users@eda.org>
References: <10C8636AE359D4119118009027AE99870C5A7443@FMSMSX34>
Subject: Mutual coupling in package IBIS model
Date: Tue, 24 Jul 2001 08:44:19 -0500
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All:

I am writing a program to generate IBIS package model using Len and per
length LRC values. Since coupling between signals is not included in the
model, I alway face a question about the applicability of the model. What I
can say is that thus-obtained model is not good for crosstalk and ground
bounce simulation (in packages), but it's still valid for simulating delay,
reflection etc. Could anyone give me a more comprehensive and "official"
answer or reference article?

Thanks in advance.

--
**************************************
Yaping Zhou (r3aadv)
(512) 933-5803
Motorola Semiconductor Products Sector
Final Manufacturing Technology Center
Ed Bluestein, Austin, Texas
**************************************


 
From owner-ibis Tue Jul 24 12:43:46 2001
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	 <ibis-users@eda.org>
Subject: Minutes, IBIS Teleconference Meeting 7/20
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DATE: 7/24/01

SUBJECT: 7/20/01 EIA IBIS Open Forum Meeting Minutes

VOTING MEMBERS AND 2001 PARTICIPANTS LIST:
3Com (& CommWorks)             Roy Leventhal*
Ansoft Corporation             (Eric Bracken)
Apple Computer                 John Figueroa
Applied Simulation Technology  [Raj Raghuram], Norio Matsui, Fred Balistreri
Avanti                         (Chen Hongyu)
Cadence Design                 [Ian Dodd], Patrick Dos Santos, Heiko Dudek
                               Lynne Green, Lance Wang
Cisco Systems                  Syed Huq, Lungfu Chen
EMC Corporation                Brian Arsenault, Jinhua Chen
Fairchild Semiconductor        Adam Tambone
Huawei Technologies            Rachild Chen
IBM                            Michael Cohen, Greg Edlund*, Wes Martin,
                               Yeon-Chang Hahm, Bill DeVey, Pravin Patel*
Innoveda (& HyperLynx)         Guy de Burgh, John Angulo*, Cary Mandel, 
                               Matthew Flora, Steve Kaufer
Intel Corporation              Stephen Peters*, Arpad Muranyi*, Dave Lorang,
                               Michael Mirmak, Qinglun Chen, Will Hobbs,
                               Wei-hsing Huang
LSI Logic                      Larry Barnes
Mentor Graphics                Bob Ross*, Tom Dagostino, Chris Reid,
                               Mike Donnelly, Hazem Hegazy, Tony Dunbar,
                               Griff Derryberry, Dan Lake, Sherif Hammad,
                               Mohammed Korany, Weston Beal, Chris Swaim,
                               Ali Samii, Eric Ronger, Karine Loudet,
                               Daisaku Shiga, Kenji Kushima
Micron Technology              Randy Wolff*, Yong Phan*
Mitsubishi                     Pat Hefferan
Molex Incorporated             Gus Panella, Brian O'Malley
National Semiconductor         Milt Schwartz
North East Systems Associates  Edward Sayre
Philips Semiconductor          Zack Ciccone, Rob Mataheroe
Quantic EMC                    (Mike Ventham)
Signal Integrity Software      Douglas Burns, Barry Katz, Walter Katz
SiQual                         Scott McMorrow, Rob Hinz, Bernard Voss,
                               Chris Brewster
Texas Instruments              Thomas Fisher, Stephen Nolan, Ramzi Ammar,
                               Jean Claude Perrin, Moshiul Haque
Time Domain Analysis Systems   Dima Smolyansky, Steve Corey
Tyco Electronics               (Russell Moser)
Via Technologies               (Weber Chuang)
Zuken (& Incases)              John Berrie, Ralf Bruening

OTHER PARTICIPANTS IN 2001:
Actel Corporation              Silvia Montoya
Acuson                         Kim Helliwell
AMCC                           Jeff Smith
ASIS Ltd                       David Wright
Brocade Communications         Robert Badal
BMW                            Friedrich Hasinger
Cereva Networks                Bob Haller
Compaq                         [Peter LaFlamme], Ron Bellomio, Quang Dam,
                               Bill Ham
Cypress                        (Rajesh Manapat)
EADS Airbus Industry           Claude Huet
  (Aerospatiale)
EFM                            Ekkehard Miersch, Horle Raines
EIA                            Cecilia Fleming
Ericsson Radio Systems         Anders Ekholm
FCI                            Sercu Stefaan
Foundary Networks              Bertram Chan
Framatom Conectors             Danny Morlion
Fraunhofer Institute           Mariusz Faferko, Peter Kralicek
  Reliability and
  Integration
Fujitsu Ltd                    Tadashi Arai, Takeshi Murakami
Heidelberger Druchmaschinen AG Wolfgang Kleinfeldt
Hyundai Electronics            Jongho Kang
Idaho State University         Al Davis
Infineon Technologies          Christian Sporrer
Intrinsix Corporation          Steven Chin
Motorola                       (Rick Kingen)
National Institute of Applied  Etienne Sicard
  Science (INSA)
Nokia                          Tapani von Ravner, Mika Castren,
                               Janne Uusitalo
Nortel Networks                Calvin Trowell
Oak Technology                 Darmin Jin
Plexus Technology Group        Joseph Socha
Siemens (& Automotive) AG      Bernhard Unger, Helmut Katzier, Katja Koller,
                               Wolfram Meyer, Eckhard Lenski, Gerald
Bannert,
                               Burkhard Muller, Christian Marot,
                               Manfred Maurer, Amir Motamedi,
                               Hans Pichlmaier
Sigrity                        Raj Raghuram*
Sintecs                        Hans Klos
STMicroelectronics             Peter Hirt, Fabrice Boissieres
Sun                            Adrian Udenze
Toshiba Corp.                  Hirokaza Kato, Yuichi Koga, Toshio Sudo
Xilinx                         Susan Wu

In the list above, attendees at the meeting are indicated by *. Principal
members or other active members who have not attended are in parentheses.
Participants who no longer are in the organization are in square brackets.

Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are
as
follows:

  Date                Bridge Number    Reservation #    Passcode
  August 10           (877) 299-1938   none             6350164    
  August 31           (916) 356-2663   2                4779396  
  Thursday, September 13, 2001 IBIS Summit Meeting, No Phone Bridge

All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas
out
7 days before each Open Forum, and meeting minutes out within 7 days after.
When you call into the meeting, ask for the IBIS Open Forum hosted by
Stephen
Peters and give the reservation number and passcode.

NOTE: "AR" = Action Required.

-------------------------------- MINUTES
-------------------------------------
INTRODUCTIONS AND MEETING QUORUM
Raj Raghuram, who has been involved for years with IBIS as a model developer
and as a tool developer joined Sigrity.  Sigrity is involved with power and
signal integrity simulations and uses IBIS models.  Raj stated that Sigrity
plans to become an EIA IBIS Open Forum member.


MEMBERSHIP UPDATE AND TREASURER'S REPORT
Stephen Peters reported about 28-29 members (down from 30) since there were
some payment issues.  These are being resolved.  Bob Ross reported there are
three potential members that are being processed (including Sigrity).  So we
expect about 32 members, ahead of the 30 member target from which our budget
is based.


REVIEW OF MINUTES AND AR'S
The June 01, 2001 IBIS Minutes were approved without change.

Bob Ross submitted a spelling correction for Ralf Bruening of Zuken in the
participants list for the June 21, 2001 IBIS Summit Meeting minutes.  The
Minutes were approved with this change.  Bob stated that the uploaded
minutes
have been corrected.

The ARs will be discussed during the meeting.


MISCELLANY/ANNOUNCEMENTS
Stephen Peters stated that several officers have been on vacation, but are
now
returning.  Guy de Burgh will return after July 27, 2001.


PRESS AND WEB PAGE UPDATES
Stephen Peters reported that Syed Huq made more Roster updates, did an FAQ
update (for ibischk3 source code license purchases), uploaded some IBIS
Summit
presentations, and updated the Upcoming Events link.


NEW MODELS AVAILABLE, LIBRARY UPDATE
Stephen Peters stated that Roy Leventhal provided more updates as of 6/26/01
on the IBIS Models link.

Bob Ross reported that Mindspeed Technologies (a Conexant Business) has IBIS

Models under (URL split into two lines to avoid mailer truncation):

 http://web2.mindspeed.com/default.sph/SaServletEngine.class/Web/products/
      documents.jsp?doc_type=27


OPENS FOR NEW ISSUES
None.


INTERNATIONAL/EXTERNAL PROGRESS
- IEC 62014-1 (IBIS Version 3.2) - No report.  Bob Ross stated that the
  document is probably still in prepublication status.

- pr EIAJ ED-5302 Standard for I/O Interface Model for Integrated Circuits
  (IMIC) - Bob Ross still cannot find the new link to the IMIC document.  

- IEC 62014-3 (ICEM) Integrated Circuit Electromagnetic Model Proposal
  (formerly, IEC 93/67/NP IBIS and EMC Simulation) - Bob Ross stated that 
  Etienne Sicard plans to present work at the September 13, 2001 IBIS Summit
  meeting.  This will be discussed later in the meeting.

- JEDEC JC-16 - Modeling and Testing - No report.

- T10, Project 1414-DT - SCSI Signal Modeling (a Technical Committee of the
  National Committee for Information Technology (NCITS)) - No report.


DESIGN AUTOMATION CONFERENCE 2001 IBIS SUMMIT MEETING FEEDBACK
Stephen Peters enjoyed the meeting.  However, he felt that we did not have
as
many questions and interactions as in some other meetings and is looking for
suggestions for more interactions.  He expected more questions on IBIS-X.
Arpad Muranyi reported that some people discussed things after the meeting, 
but he did not think there was an IBIS-X parser demonstration offered by Al
Davis.  Several people had to catch plane connections after the meeting.

Bob Ross stated that we had more presentations than expected and had to
limit
questions to keep the meeting going.  We did not have copies of all slides
available at the meeting.  The presentations are all now uploaded under:

  http://www.eda.org/pub/ibis/summits/jun01/


PCB CONFERENCE EAST 2001 IBIS SUMMIT MEETING PLANS
Bob Ross reported that an IBIS Summit Meeting is planned all day on
Thursday, 
September 13, 2001 in Worcester, Massachusetts at the Crowne Plaza Hotel
near
the PCB Conference East 2001 show.  The meeting follows on the next day the
trade show portion of the show.  The Upcoming events link of the IBIS Home
page already contains the sign-up information and hotel information.  A free
lunch and refreshments are included.

Kathy Breda of NESA has been handling the arrangements and signups.  She
will
also coordinate making copies of presentations for the meeting.  Bob stated
that we need to address the funding issue.  In the past the EDA vendors have
shared the meeting expenses.

So far Bob expects these presentations (titles may change):

  "Modeling the Radiated Emission of Micro-controllers", Etienne Sicard,
    National Institute of Applied Science (INSA) in France
  "A Proposal for s2ibis3", Michael Steer, North Carolina State University
  
  Plus IBIS Version 4.0, IBIS-X and IBIS Connector Specification Progress

Bob indicated that the IBIS Futures Working Group had discussed
demonstrating
the IBIS-X parser at the Summit meeting.  This follows up on Stephen Peters
comment to make the meeting have more interactive and promote more questions
and discussions.

Bob plans that the first announcement will be sent next week.
  

NORTH CAROLINA STATE UNIVERSITY S2IBIS3 PROJECT
Stephen Peters reported that he and Michael Steer of North Carolina State
University (NCSU) have made recent contact.  NCSU is working on a cell
design
project under a DARPA contract and is now interested in using IBIS.  Michael
is interested in developing s2ibis3 as part of this research.  His team
would
be interested in using the ibischk3 as a basis, but Stephen stated that NCSU
would have to pay for the source code.  NCSU will probably develop their
own parser independently.

Bob Ross mentioned that NCSU would release s2ibis3 source code and
executables
under a GPL (GNU public license).  Michael Steer is scheduled to discuss the
project at the September 13, 2001 IBIS Summit Meeting.


IBIS MODEL REVIEW COMMITTEE DISCUSSION
John Angulo sent out a model from STMicroelectronics for review.  John also
has two other models that are being processed prior to being distributed.

John stated that he cannot continue heading the IBIS Model Review Committee
because of work commitments.  He suggested several other people.  Stephen
Peters will work offline to find a replacement.


MAJORDOMO AND SPAM MAIL UPDATE
Stephen Peters reported that there seems to be more spam messages on the
IBIS
reflectors.  Possibly someone is harvesting names off the mailing list
(which
is protected) or off of e-mail correspondence.  One solution is to control
the
messages from a list server such as Majordomo.  Using Majordomo, only folks
that
have subscribed and have known valid e-mail addresses could post to the IBIS
reflectors, thus cutting down on SPAM to the list.

John Angulo is still working with the eda.org systems administrators on
using
Majordomo.  John would want to set up a test reflector before we actually
make the change.  There might be more restrictive access.  John also noted
that some of the spam messages have been sent to the ibis-request and
ibis-info addresses.


CONNECTOR PROPOSAL REVIEW
The Working Group has been meet on June 12, July 3, and July 10, 2001.  The
attendance was down because of vacations.  Stephen Peters summarized that
work
is continuing on reviewing the Connector Specification to align it with the
IBIS document and also with some IBIS-X conventions.  This work is
proceeding
more slowly than expected.

Some recent topics include uncoupled and coupled lines, the transmission
line
syntax and frequency dependent matrices.

Bob Ross stated that more people are now involved.  Some earlier decisions
are
subject to review.  The original choices included focusing on connector only
issues versus trying to make this a combined package/connector model
document,
and postponing lossy matrices.  Arpad Muranyi stated that it might not be
difficult to put in frequency dependent matrices.  Bob agreed and stated
that
the earlier consensus continues to implement losses based on matrices as a
function of frequency.  This is a superset of just assuming skin effect and
conductance matrix relationships.

Stephen stated that he preferred using the matrix approach as implemented in
the document and wanted to proceed in a rapid manner to get the Connector
Specification approved by the end of the year.  It has been under
development
for several years.

The next meeting is scheduled on July 24, 2001, and they should continue on
a
weekly basis.


IBIS FUTURES (IBIS-X, API, BIRDxx)
Stephen Peters summarized the progress based on meetings on June 12, July 3,
10 and 17, 2001.  The discussions included the basic elements, some
transmission line syntax (similar to the Connector Specification), LRC
matrix issues and the Laplace element.  John Angulo added that the syntax
for
controlled sources was discussed at the last meeting.

Stephen stated that Scott McMorrow has issued comments on the Connector 
Specification and now is providing good comments on the IBIS futures
documents.

Work is continuing and the next meeting is scheduled for July 24, 2001.
These
should continue on a weekly basis.


BIRD70.3 - GOLDEN WAVEFORMS
Greg Edlund indicated that he put out several messages on the IBIS reflector
in response to comments made at previous meetings.  He got one positive
comment back.

Bob Ross stated that vacations and other IBIS activities prevented him from
looking at BIRD70.3 and Greg's comments until now.  He summarized his
response
as follows:

  He agrees with Issue 1 that a new [Test Data] subparameter
Driver_model_inv
  should be added to support unsymmetrical differential drivers.

  He suggests that [Test Load] should add the subparamater
Receiver_model_inv
  for completeness and to support unsymmetrical receivers with internal 
  terminations.

  Bob noted that the [Test Load] subparameter Test_load_type was incorrectly
  entered as "Test_data_type" in some portions of BIRD70.3.

  Bob agreed with Greg's proposed Issue 2 restriction that only these
  combinations of Test_data_type and Test_load_type would be supported:

     Single_ended, Single_ended
     Differential, Differential

  While the combination Differential, Single_ended is also possible, it is
  not necessary since the Single_ended test load can be created with default
  large values of Rdiff*.  The rules need to be stated for the Single_ended
  case how to interpret the differential golden waveforms [Diff ...] and the
  Rdiff* and *_inv parameters.  Bob proposed that should be ignored.  The
  parser probably would accept the model, but issue an Warning message.

  Finally the single_ended golden waveforms given for Test_data_type
  Differential should be for the non-inverting side of the net when *-inv
  models are used.  The inverting golden waveform data can be obtained by a
  separate test, but with the inverting and non-inverting models
interchanged.
  If the differential network is symmetrical, this is not an issue since the
  inverting and non-inverting models are the same.

Bob plans to respond on the reflector to Greg's e-mail to capture these
points.  Greg should review this and issue BIRD70.4 in time for a vote at
the
next IBIS Meeting.  

AR - Bob Ross respond to Greg Edlunds comments.  Greg issue BIRD70.4 by July
27, 2001 so that it can be presented for a vote at the next IBIS Meeting.


BIRD71 - TIMING TEST LOADS IN [Model Spec] TO SUPPORT PCI & PCI-X
Stephen Peters stated that there have not been any reflector comments on
BIRD71.  BIRD71 completes the list of [Model Spec] subparameters in a manner
that supports PCI and PCI-X specifications.  There have been some concerns
on
how EDA tools should use the new information.

Bob Ross stated that he had questions because some of the new specification
subparameters interacted with the model data itself.  The loads, for example
may be different for the min and max corners.  This does not relate to how
a physical part is specified or measured since the measurement is set up
independent of the electrical characteristics of the component.  So there
may
be some ambiguity on how EDA tools are to process the new subparameters.

One suggestion is that the new subparameters is related to the actual model
corners and are used to set up best and worst cases.  Bob had suggested that
there might be some discussion about on this in BIRD71.  He did not have
specific suggestions.  Bob favors adding the subparameters per BIRD71 and
letting the EDA tools decide how to process the new information.  He will
communicate any new ideas, if any, by next week.

Stephen proposed that BIRD71 be scheduled for a vote at the next meeting.


OTHER PENDING BIRDS
Stephen Peters stated that he wanted IBIS Version 4.0 to be finished soon
and
voted by the end of the year.  Votes are planned for BIRD70.4 and BIRD71.
All
other pending BIRDs need to be issued or deferred until IBIS-X.

Bob stated that the SSO improvement proposal is pending, but might be
deferred
to IBIS-X where structural interactions could be programmed.  This
improvement
may not work in all cases and may open up some technical issues.  A fallback
submodel BIRD is needed for some existing technologies needs to be generated
if it is to be considered.  Bob also stated that a clarification BIRD for
Series Switch models is being developed by Tom Dagostino (following up on
the
Ad Hoc presentation at the June 21, 2001 IBIS Summit Meeting).  This pending
BIRD will make the discussion more general, but will not propose any syntax
change.


IBISCHK3 BUG TRACKING
- BUG57 Non-Mononic Table Causes Waveform Endpoint Test to Fail
  Bob Ross introduced BUG57 by pointing out that if the [Pulldown] and/or
  the [Pullup] table contains non-monotonic data in the clamping regions,
and
  there are no [Gnd Clamp] or [Power Clamp] tables, ibischk3 gives an
  incorrect Error message.  

  The non-monotonic data itself causes ibischk3 to calculate the wrong
  endpoint values because the algorithm probably has numerical difficulties.
  It probably starts its convergence calculation at one end of the table
  rather than from the middle and gets numerically confused with the
  non-monotonic data.

  Even though the model is non-monotonic, it may represent real data.  Some
  EDA tools will correctly process the model.  However, the recently
  implemented Waveform endpoint tests now report an Error instead of a
  Warning, preventing the model to be processed in systems that uses
ibischk3
  for input model parsing.

  Bob suggested classifying BUG57 as Annoying, Low, and Open.

  The problem is how to resolve BUG57.  The choices are (1) fix the test,
(2)
  change the Error back to a Warning, or (3) ignore this problem and force
the
  user to modify the IBIS file.

  Bob suggested that we work on (1) as a low priority activity.  If the fix
is
  too difficult, then we might consider (3).  No one wanted (2).  Stephen
  Peters suggested that a note could be added to the Warning or Error
message
  to alert the user of a possible reason for the Error Message so that the
  user could modify the model.  Bob suggested that because this is a low
  priority bug, it should be investigated after all the other open bugs are
  fixed.  Then we can decide how to proceed.


END OF MEETING TOPIC
Roy Leventhal stated that he talked about signal integrity and IBIS at a 
recent IPC Design Learning Symposium meeting.  He will track their activity.


NEXT MEETING:
The next teleconference meeting will be on Friday, August 10, 2001, from 
8:00 AM to 10:00 AM.  BIRD70.4 and BIRD71 are scheduled for a vote.
============================================================================
==
                                      NOTES

IBIS CHAIR: Stephen Peters (503) 264-4108, Fax: (503) 264-1831
            stephen.peters@intel.com
            Senior Hardware Engineer, Intel Corporation
            M/S JF4-215
            2111 NE 25th Ave.
            Hillsboro, OR 97124-5961

VICE CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
            bob_ross@mentor.com
            Modeling Engineer, Mentor Graphics
            8005 S.W. Boeckman Road, Wilsonville, OR 97070

SECRETARY:  Guy de Burgh (805) 988-8250, Fax: (805) 988-8259
            gdeburgh@innoveda.com
            Senior Manager, Innoveda
            1369 Del Norte Rd.
            Camarillo, CA 93010-8437

LIBRARIAN:  Roy Leventhal (837) 797-2152, Fax: (847) 222-2799
            roy_leventhal@3com.com
            Senior Engineer, CommWorks Corp. (a wholly owned 3Com
subsidiary)
            1800 W. Central Rd.
            Mt. Prospect, IL 60056-2293

WEBMASTER:  Syed Huq (408) 525-3399, Fax: (408) 526-5504
            shuq@cisco.com
            Manager, Hardware Engineering, Cisco Systems
            170 West Tasman Drive
            San Jose, CA 95134-1706

POSTMASTER: John Angulo (425) 869-2320, Fax: (425) 881-1008
            jangulo@innoveda.com
            Development Engineer, Innoveda
            14715 N.E. 95th Street, Suite 200
            Redmond, WA 98052

This meeting was conducted in accordance with the EIA Legal Guides and EIA
Manual of Organization and Procedure.

The following e-mail addresses are used:

  ibis-request@eda.org
      To join, change, or drop from either the IBIS Open Forum Reflector
      (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
      or both.  State your request.

  ibis-info@eda.org
      To obtain general information about IBIS, to ask specific questions
      for individual response, and to inquire about joining the EIA-IBIS
      Open Forum as a full Member.

  ibis@eda.org
      To send a message to the general IBIS Open Forum Reflector.  This
      is used mostly for IBIS Standardization business and future IBIS
      technical enhancements.  Job posting information is not permitted.

  ibis-users@eda.org
      To send a message to the IBIS Users' Group Reflector.  This is
      used mostly for IBIS clarification, current modeling issues, and
      general user concerns.  Job posting information is not permitted.

  ibischk-bug@eda.org
      To report ibischk2/3 parser bugs.  The Bug Report Form Resides on
      eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported
bugs.

      To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
      which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt,
      /pub/ibis/bugs/s2ibis2/bugs2i2.txt, &
/pub/ibis/bugs/s2iplt/bugsplt.txt
      respectively.

Information on IBIS technical contents, IBIS participants, and actual
IBIS models are available on the IBIS Home page found by selecting the
Electronic Information Group under:

  http://www.eigroup.org/ibis/ibis.htm

Check the pub/ibis directory on eda.org for more information on previous
discussions and results.  You can get on via FTP anonymous.
============================================================================
==
 
From owner-ibis Tue Jul 24 18:11:38 2001
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Message-ID: <002a01c114a7$040c6660$14180b0a@huawei.com>
From: "LiuWeidong" <liuweidong@huawei.com>
To: "Peters, Stephen" <stephen.peters@intel.com>
Cc: <ibis-users@eda.org>, <ibis@eda.org>
References: <7FD5C79AD680D211AC4100A0C96B501C084A789A@orsmsx49.jf.intel.com>
Subject: Re: Minutes, IBIS Teleconference Meeting 7/20
Date: Wed, 25 Jul 2001 09:13:30 +0800
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For the message bellow, 
" Even though the model is non-monotonic, it may represent real data"
" (3) ignore this problem and force  the   user to modify the IBIS file."
" Bob suggested that we work on (1) as a low priority activity.  If the fix  is   too difficult, then we might consider (3).  No one wanted (2).  "

I want to ask:
It seems that a  good model maybe is non-monotonic(right or wrong ?),Then how can we modefy the IBIS file ?

Thanks,
regards,
LiuWeidong

----- Original Message ----- > 
> 
> IBISCHK3 BUG TRACKING
> - BUG57 Non-Mononic Table Causes Waveform Endpoint Test to Fail
>   Bob Ross introduced BUG57 by pointing out that if the [Pulldown] and/or
>   the [Pullup] table contains non-monotonic data in the clamping regions,
> and
>   there are no [Gnd Clamp] or [Power Clamp] tables, ibischk3 gives an
>   incorrect Error message.  
> 
>   The non-monotonic data itself causes ibischk3 to calculate the wrong
>   endpoint values because the algorithm probably has numerical difficulties.
>   It probably starts its convergence calculation at one end of the table
>   rather than from the middle and gets numerically confused with the
>   non-monotonic data.
> 
>   Even though the model is non-monotonic, it may represent real data.  Some
>   EDA tools will correctly process the model.  However, the recently
>   implemented Waveform endpoint tests now report an Error instead of a
>   Warning, preventing the model to be processed in systems that uses
> ibischk3
>   for input model parsing.
> 
>   Bob suggested classifying BUG57 as Annoying, Low, and Open.
> 
>   The problem is how to resolve BUG57.  The choices are (1) fix the test,
> (2)
>   change the Error back to a Warning, or (3) ignore this problem and force
> the
>   user to modify the IBIS file.
> 
>   Bob suggested that we work on (1) as a low priority activity.  If the fix
> is
>   too difficult, then we might consider (3).  No one wanted (2).  Stephen
>   Peters suggested that a note could be added to the Warning or Error
> message
>   to alert the user of a possible reason for the Error Message so that the
>   user could modify the model.  Bob suggested that because this is a low
>   priority bug, it should be investigated after all the other open bugs are
>   fixed.  Then we can decide how to proceed.
> 
> 

 
From owner-ibis Wed Jul 25 06:50:29 2001
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Importance: Normal
Subject: Re: about the IBIS "checklist.txt."
To: "LiuWeidong" <liuweidong@huawei.com>
Cc: ibis-users@vhdl.org, ibis@vhdl.org
X-Mailer: Lotus Notes Release 5.0.3 (Intl) 21 March 2000
Message-ID: <OF39CD6693.8C137BA7-ON86256A94.004A9874@rchland.ibm.com>
From: "Gregory R Edlund" <gedlund@us.ibm.com>
Date: Wed, 25 Jul 2001 08:50:11 -0500
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Dear LiuWeidong,

Please see my answers below your questions.  I hope this helps you.

Greg Edlund
Electrical Packaging
IBM Server Technology Development
3605 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com


"LiuWeidong" <liuweidong@huawei.com> on 07/23/2001 08:38:09 PM

To:   Gregory R Edlund/Rochester/IBM@IBMUS
cc:   <ibis-users@eda.org>, <ibis@eda.org>
Subject:  about  the  IBIS  "checklist.txt."



Hello, Greg
I have some questions about your IBIS Datasheet Checklist :

"3. Has the modeling engineer performed a visual inspection of IV and  VT
curves to screen for non-monotonicity, discontinuities, and other obvious
errors?"
If a IV curves is non-monotonicity,How can  I deal with it ? Can the model
be used by the simulation tools?
There are so many  IBIS models provided by IC venders whose IV curves is
non-monotonicity  .

[GREG]  Non-monotonicity can be OK in some circumstances.  Page 20 of the
IBIS Cookbook shows an example of a pull-down curve that becomes
non-monotonic after you subtract out the ground clamp current (I believe
this is a numerical effect).  Once you add the two curves back together,
the composite becomes monotonic again, so this is OK.  In other
circumstances non-monotonicity may be indicative of a circuit feature such
as bus hold, which uses a feedback circuit.  This can make the simulator
fail, so I usually smooth out the non-monotonicity in the IV curve of a
circuit that has bus hold.  The point is that you need to know what's
causing the non-monotonicity.  Your IBIS vendor should do this for you.

"8. Does the output reach Vmeas under standard load conditions for   rising
and falling waveforms?"
For this item , I don't think it should be in the IBIS Datasheet Checklist
, Whether the output can reach Vmeas under standard load conditions for
rising   and falling waveforms mainly depend on the output buffer's driving
capability . If a  buffer's driving  capability is very weak, the output
maybe can't  reach Vmeas under standard load conditions for   rising   and
falling waveforms,but you can't think the IBIS model is wrong.

[GREG]  Vmeas comes from the component datasheet, and so the output better
be able to drive it's own standard load.  If it can't, there's something
seriously wrong with the circuit design.  If the behavioral simulations
using the IBIS file don't reach Vmeas with the standard load but the real
component DOES, then something went wrong during the creation of the IBIS
file.

Hope for your reply!
Thanks!
LiuWeidong


----- Original Message -----
From: Gregory R Edlund <gedlund@us.ibm.com>
To: <Anbu@scmmicro.co.in>
Cc: <ibis-users@vhdl.org>
Sent: Thursday, May 24, 2001 8:53 PM
Subject: Re: Clarification needed.


>
> Anbazhagan,
>
> Looks like you're on the right track.  I would recommend your ASIC vendor
> read the "IBIS Cookbook," which can be found on the IBIS web page:
> http://www.eigroup.org/ibis/tools.htm
>
> As part of the "I/O Buffer Accuracy Handbook" (also available on the IBIS
> web page), we published a checklist that should help you.  This list was
> compiled from suggestions by members of the SI community who have
> experience with IBIS.  I am attaching the most recent version of this
list.
>
> Bob, Could you please post this list as an ASCII text file under
Accuracy?
> Pleas name it "checklist.txt."  Thanks.
>
>
> IBIS Datasheet Checklist                                  version 1.1,
> 05/07/01
> ------------------------
>
>
> IBIS datasheet:
> Component manufacturer:
> Component part number:
> Engineer verifying this component:
> Email address:
> Behavioral simulator and version:
> Date:
>
>
> Note:   If answer is N or N/A, provide explanation.
>         The user may verify items 1-9 but is unable to verify items 10-20
>         because the data involved are only available to the semiconductor
>         vendor.
>
>
> ___  1. Does the IBIS datasheet pass the IBIS syntax checker?
>         (Note: Some models generate warnings for non-monotonicities that
> are
>         actually part of the characteristics of the device. Other non-
>         monotonicities are so small as to be irrelevant.)
>
> ___  2. Is an "I/O Buffer Accuracy Report" available for this component?
>         (http://www.vhdl.org/pub/ibis/accuracy)
>
> ___  3. Has the modeling engineer performed a visual inspection of IV and
> VT
>         curves to screen for non-monotonicity, discontinuities, and other
>         obvious errors?
>
> ___  4. Has the modeling engineer tested the IBIS datasheet using a
> behavioral
>         simulator?
>
> ___  5. Do MIN and MAX data exist for all keywords and sub-parameters?
>
> ___  6. Does the IBIS datasheet include all four 50 Ohm VT tables as
> described
>         in the IBIS Cookbook?
>
> ___  7. Do the keywords Cref, Rref, Vref, and Vmeas match the values
> specified
>         in the component datasheet for all output and bidirectional
models?
>
> ___  8. Does the output reach Vmeas under standard load conditions for
> rising
>         and falling waveforms?
>
> ___  9. Does the pin table match the component datasheet?
>
>
> ___ 10. Do the keywords Vihl and Vinh represent the unity gain points
> derived
>         from the dc transfer characteristics for all inputs?
>
> ___ 11. Has the modeling engineer verified the accuracy of the C_comp
>         subparameter?
>
> ___ 12. Has the modeling engineer verified the accuracy of the R_pkg,
> L_pkg,
>         and C_pkg subparameters?
>
> ___ 13. For CMOS logic, do all MAX data represent maximum voltage,
minimum
>         temperature, and fast process?
>
> ___ 14. For CMOS logic, do all MIN data represent minimum voltage,
maximum
>         temperature, and slow process?
>
> ___ 15. For bipolar logic, do all MAX data represent maximum voltage,
> maximum
>         temperature, and fast process?
>
> ___ 16. For bipolar logic, do all MIN data represent minimum voltage,
> minimum
>         temperature, and slow process?
>
> ___ 17. Do the keywords dV/dt_r and dV/dt_f contain the correct 20%-80%
> edge
>         rate data measured using a 50 & load as specified in IBIS?
>
> ___ 18. If the I/O buffer employs dynamic clamping, does the IBIS
datasheet
>         contain the appropriate keywords and subparameters?
>
> ___ 19. If the I/O buffer employs a multi-stage driver, does the IBIS
> datasheet
>         contain the appropriate keywords and subparameters?
>
> ___ 20. If the I/O buffer design employs dynamic edge rate control,
dynamic
>         impedance control, or any form of feedback, has the modeling
> engineer
>         assessed the impact of this circuitry on behavioral model
accuracy?
>
>
> Greg Edlund
> Electrical Packaging
> IBM Server Technology Development
> 3605 Hwy. 52 N, Dept. HDC
> Rochester, MN 55901
> gedlund@us.ibm.com
>
>
> Anbu@scmmicro.co.in on 05/24/2001 01:48:13 AM
>
> To:   "ibis-users@eda.org":
> cc:
> Subject:  Clarification needed.
>
>
>
> Hello Users,
>
>         I am using XTK to simulate a PCBA. The board has a 100pin ASIC.
In
> order to model the ASIC properly I need the IBIS model of the ASIC which
I
> can convert it to XTK format. Now if I directly request for an IBIS model
> the vendor may hesistate. So I am requesting the following data from the
> vendor with which I can create a IBIS model. Below is the data I am
> requesting them. Is it OK. Does it cover everything necessary to create a
> proper IBIS model?. The ASIC does not have any clamp diodes. Please
reply.
> The following data whichever is applicable for each pin of the ASIC are
> needed
>  1. Package parasitics namely, the Resistance, capacitance and
Inductance.
> Typical, max, min values required.
>
> 2. Die capacitance as seen at the die pad. Typical, max, min values
> required
>
> 3. Output impedance of the I/O buffers. Typical, max, min values
required.
>
> 4. Rise time and fall time values (dv/dt typical, max, min) of buffers
> excluding the effect of packaging but including the effect of die
> capacitance. Load conditions required.
>
> 6. Rising edge and falling edge waveforms (Voltage vs. time curve with
the
> voltage values having typical, max, min values) of the driver along with
> the test conditions.
>
> 5. V/I characteristics of Pull up and Pull down resistor, if present,
when
> the buffer is driven high and low respectively. The voltage sweep must be
> from ?3.3V to +6.6V. Current measurement with typical, max, min values
are
> required.
>
> Thanks,
>
> Anbazhagan.
>
>
>
>
>
>



 
From owner-ibis Wed Jul 25 09:08:00 2001
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To: "LiuWeidong" <liuweidong@huawei.com>,
   "Peters, Stephen" <stephen.peters@intel.com>
From: Lynne Green <lgreen@cadence.com>
Subject: Re: Minutes, IBIS Teleconference Meeting 7/20
Cc: <ibis-users@eda.org>, <ibis@eda.org>
In-Reply-To: <002a01c114a7$040c6660$14180b0a@huawei.com>
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The EDA tools have to be able to use these models, which means the models
must pass the parser.

A smart user will send the model back to the person who made it, to verify
whether the non-monotonicity is "real", before proceeding with simulation.

- Lynne

At 09:13 AM 7/25/2001 +0800, LiuWeidong wrote:
>For the message bellow,
>" Even though the model is non-monotonic, it may represent real data"
>" (3) ignore this problem and force  the   user to modify the IBIS file."
>" Bob suggested that we work on (1) as a low priority activity.  If the 
>fix  is   too difficult, then we might consider (3).  No one wanted (2).  "
>
>I want to ask:
>It seems that a  good model maybe is non-monotonic(right or wrong ?),Then 
>how can we modefy the IBIS file ?
>
>Thanks,
>regards,
>LiuWeidong
>
>----- Original Message ----- >
> >
> > IBISCHK3 BUG TRACKING
> > - BUG57 Non-Mononic Table Causes Waveform Endpoint Test to Fail
> >   Bob Ross introduced BUG57 by pointing out that if the [Pulldown] and/or
> >   the [Pullup] table contains non-monotonic data in the clamping regions,
> > and
> >   there are no [Gnd Clamp] or [Power Clamp] tables, ibischk3 gives an
> >   incorrect Error message.
> >
> >   The non-monotonic data itself causes ibischk3 to calculate the wrong
> >   endpoint values because the algorithm probably has numerical 
> difficulties.
> >   It probably starts its convergence calculation at one end of the table
> >   rather than from the middle and gets numerically confused with the
> >   non-monotonic data.
> >
> >   Even though the model is non-monotonic, it may represent real data.  Some
> >   EDA tools will correctly process the model.  However, the recently
> >   implemented Waveform endpoint tests now report an Error instead of a
> >   Warning, preventing the model to be processed in systems that uses
> > ibischk3
> >   for input model parsing.
> >
> >   Bob suggested classifying BUG57 as Annoying, Low, and Open.
> >
> >   The problem is how to resolve BUG57.  The choices are (1) fix the test,
> > (2)
> >   change the Error back to a Warning, or (3) ignore this problem and force
> > the
> >   user to modify the IBIS file.
> >
> >   Bob suggested that we work on (1) as a low priority activity.  If the fix
> > is
> >   too difficult, then we might consider (3).  No one wanted (2).  Stephen
> >   Peters suggested that a note could be added to the Warning or Error
> > message
> >   to alert the user of a possible reason for the Error Message so that the
> >   user could modify the model.  Bob suggested that because this is a low
> >   priority bug, it should be investigated after all the other open bugs are
> >   fixed.  Then we can decide how to proceed.
> >
> >

 
From owner-ibis Wed Jul 25 10:41:14 2001
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Organization: UTMC Microelectronic Systems
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I'm interested in the discussion about
non-monotonicity of I/V curves.  This seems
to be very common in our parts, and is definitely
real, that is, it shows up in the HSPICE simulation
and in the physical part measured on a curve tracer.

One example is an LVDS receiver that has a spike
in the current at about 1 volt above VDD.  This
is not just an artifact of subtracting the ground
clamp current from the pulldown current.
(Incidentally, I can't get a good explanation
for this behavior.  The designers of the parts
don't simulate with voltage outside the rails,
and they typically tell me that the SPICE models
may not be any good in this region anyway!)

I don't know what I should do in this case.  I
don't know which tools customers may want to use
so I don't know if this will really be a problem
for them.  Are there any guidelines about how to 
"smooth out the non-monotonicity"?  And if I do
change the data, how can tools give accurate results
with IBIS models that now do not reflect the
physical part?


-- 
Greg Haynes		  haynes@utmc.aeroflex.com
Aeroflex UTMC Microelectronic Systems
4350 Centennial Blvd           phone: 719 594-8197
Colorado Springs, CO 80907       fax: 719 594-5541
 
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Date: Wed, 25 Jul 2001 11:20:36 -0700
From: Scott McMorrow <scott@vasthorizons.com>
Organization: SiQual
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Greg,

non-monotonic behavior which is outside of the normal
operating range of the device, and be smoothed to
eliminate the behavior.  This will have absolutely no
effect on simulation ... as long as the signalling range
does not enter this region.

regards,

scott


--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com



Greg Haynes wrote:

> I'm interested in the discussion about
> non-monotonicity of I/V curves.  This seems
> to be very common in our parts, and is definitely
> real, that is, it shows up in the HSPICE simulation
> and in the physical part measured on a curve tracer.
>
> One example is an LVDS receiver that has a spike
> in the current at about 1 volt above VDD.  This
> is not just an artifact of subtracting the ground
> clamp current from the pulldown current.
> (Incidentally, I can't get a good explanation
> for this behavior.  The designers of the parts
> don't simulate with voltage outside the rails,
> and they typically tell me that the SPICE models
> may not be any good in this region anyway!)
>
> I don't know what I should do in this case.  I
> don't know which tools customers may want to use
> so I don't know if this will really be a problem
> for them.  Are there any guidelines about how to
> "smooth out the non-monotonicity"?  And if I do
> change the data, how can tools give accurate results
> with IBIS models that now do not reflect the
> physical part?
>
> --
> Greg Haynes               haynes@utmc.aeroflex.com
> Aeroflex UTMC Microelectronic Systems
> 4350 Centennial Blvd           phone: 719 594-8197
> Colorado Springs, CO 80907       fax: 719 594-5541



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fn:Scott McMorrow
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--------------B96D5A47E637C96B2007FC1A--

 
From owner-ibis Wed Jul 25 12:13:31 2001
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From: "Haller, Robert" <rhaller@cereva.com>
To: "'Greg.Haynes+AEA-utmc.aeroflex.com'" <Greg.Haynes@utmc.aeroflex.com>,
   "'Scott McMorrow'" <scott@vasthorizons.com>
Cc: "ibis-users+AEA-eda.org" <ibis-users@eda.org>
Subject: RE: Non-monotonicity in IBIS models
Date: Wed, 25 Jul 2001 15:10:47 -0400
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Greg,
	Non-monotonic IV curves, is a favorite discussion of mine.
First, I would concur with Scott that if the Non-monotonic
behavior is OUTSIDE your area of operation, your simulator should 
produce accurate results (assuming the model is accurate).
	BUT, you must be very cautious because there are parts out there
which 
contain feedback circuits (i.e. ACTQ, Some RAMS)that are truly nonmonotonic
in the 
area of operation. Behavioral simulators (SPICE included) will often have 
trouble with DC convergence when you run AC simulations near the
non-monotonic IV
regions. I have seen cases were after considerable effort I got a simulation
to converge,
only to find out the output wildly oscillated. I placed a part on a test
board, driving a 
long transmission line and guess what. It oscillated too. 

Regards,
Bob Haller
Cereva Networks
508-787-5365

-----Original Message-----
From: Greg Haynes +AFs-mailto:haynes+AEA-utmc.aeroflex.com+AF0-
Sent: Wednesday, July 25, 2001 1:41 PM
To: ibis-users+AEA-eda.org
Subject: Non-monotonicity in IBIS models


I'm interested in the discussion about
non-monotonicity of I/V curves.  This seems
to be very common in our parts, and is definitely
real, that is, it shows up in the HSPICE simulation
and in the physical part measured on a curve tracer.

One example is an LVDS receiver that has a spike
in the current at about 1 volt above VDD.  This
is not just an artifact of subtracting the ground
clamp current from the pulldown current.
(Incidentally, I can't get a good explanation
for this behavior.  The designers of the parts
don't simulate with voltage outside the rails,
and they typically tell me that the SPICE models
may not be any good in this region anyway+ACE-)

I don't know what I should do in this case.  I
don't know which tools customers may want to use
so I don't know if this will really be a problem
for them.  Are there any guidelines about how to 
+ACI-smooth out the non-monotonicity+ACI-?  And if I do
change the data, how can tools give accurate results
with IBIS models that now do not reflect the
physical part?


-- 
Greg Haynes		  haynes+AEA-utmc.aeroflex.com
Aeroflex UTMC Microelectronic Systems
4350 Centennial Blvd           phone: 719 594-8197
Colorado Springs, CO 80907       fax: 719 594-5541
 
From owner-ibis Wed Jul 25 13:59:39 2001
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To: Lynne Green <lgreen@cadence.com>
CC: LiuWeidong <liuweidong@huawei.com>,
   "Peters, Stephen" <stephen.peters@intel.com>, ibis-users@eda.org,
   ibis@eda.org
Subject: IBIS Bug57 Re: Minutes, IBIS Teleconference Meeting 7/20
References: <7FD5C79AD680D211AC4100A0C96B501C084A789A@orsmsx49.jf.intel.com> <5.0.2.1.2.20010725090426.00a91f08@gda.cadence.com>
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Hello LiuWeidong and Lynne:

Let me clarify that the problem in bug57 is
not the non-monotonic behavior itself.  The
issue is that the waveform endpoint test
incorrectly fails.  The waveform endpoints
are actually correct, the the non-monotonic
behavior described in bug57 causes the parser
itself to not find the correct endpoints.  This
causes the model to fail because we recently
changed the endpoint test (bug47) to issue
an Error when the mismatch is greater than 10%.

So a good model may be rejected because of
the ibischk3 bug.  The region where the
failure occurs however, is not critical
(e.g., in an extended clamping region where
no current could possibly flow anyway.  The
easy (3) fix is just to change the current in
that region to be monontonic.  This type of
change would be on a case-by-case basis
based on where the problem is.

I suspect that the parser problem is based
an algorithm that starts at one end of a
table to find a solution.  If the algorithm
started at the middle to find the solution,
this would be less of a problem.

See bug57 for a test case and more information:

  http://www.eda.org/pub/ibis/bugs/ibischk/bug57

Bob Ross
Mentor Graphics



Lynne Green wrote:
> 
> The EDA tools have to be able to use these models, which means the models
> must pass the parser.
> 
> A smart user will send the model back to the person who made it, to verify
> whether the non-monotonicity is "real", before proceeding with simulation.
> 
> - Lynne
> 
> At 09:13 AM 7/25/2001 +0800, LiuWeidong wrote:
> >For the message bellow,
> >" Even though the model is non-monotonic, it may represent real data"
> >" (3) ignore this problem and force  the   user to modify the IBIS file."
> >" Bob suggested that we work on (1) as a low priority activity.  If the
> >fix  is   too difficult, then we might consider (3).  No one wanted (2).  "
> >
> >I want to ask:
> >It seems that a  good model maybe is non-monotonic(right or wrong ?),Then
> >how can we modefy the IBIS file ?
> >
> >Thanks,
> >regards,
> >LiuWeidong
> >
> >----- Original Message ----- >
> > >
> > > IBISCHK3 BUG TRACKING
> > > - BUG57 Non-Mononic Table Causes Waveform Endpoint Test to Fail
> > >   Bob Ross introduced BUG57 by pointing out that if the [Pulldown] and/or
> > >   the [Pullup] table contains non-monotonic data in the clamping regions,
> > > and
> > >   there are no [Gnd Clamp] or [Power Clamp] tables, ibischk3 gives an
> > >   incorrect Error message.
> > >
> > >   The non-monotonic data itself causes ibischk3 to calculate the wrong
> > >   endpoint values because the algorithm probably has numerical
> > difficulties.
> > >   It probably starts its convergence calculation at one end of the table
> > >   rather than from the middle and gets numerically confused with the
> > >   non-monotonic data.
> > >
> > >   Even though the model is non-monotonic, it may represent real data.  Some
> > >   EDA tools will correctly process the model.  However, the recently
> > >   implemented Waveform endpoint tests now report an Error instead of a
> > >   Warning, preventing the model to be processed in systems that uses
> > > ibischk3
> > >   for input model parsing.
> > >
> > >   Bob suggested classifying BUG57 as Annoying, Low, and Open.
> > >
> > >   The problem is how to resolve BUG57.  The choices are (1) fix the test,
> > > (2)
> > >   change the Error back to a Warning, or (3) ignore this problem and force
> > > the
> > >   user to modify the IBIS file.
> > >
> > >   Bob suggested that we work on (1) as a low priority activity.  If the fix
> > > is
> > >   too difficult, then we might consider (3).  No one wanted (2).  Stephen
> > >   Peters suggested that a note could be added to the Warning or Error
> > > message
> > >   to alert the user of a possible reason for the Error Message so that the
> > >   user could modify the model.  Bob suggested that because this is a low
> > >   priority bug, it should be investigated after all the other open bugs are
> > >   fixed.  Then we can decide how to proceed.
> > >
> > >
 
From owner-ibis Thu Jul 26 05:53:30 2001
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Date: Thu, 26 Jul 2001 08:51:47 -0400
From: Jason Leung <jleung@cid.alcatel.com>
Organization: Alcatel
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To: Bob Ross <bob_ross@mentorg.com>, "ibis-users@eda.org" <ibis-users@eda.org>
Subject: Re: IBIS Bug57 Re: Minutes, IBIS Teleconference Meeting 7/20
References: <7FD5C79AD680D211AC4100A0C96B501C084A789A@orsmsx49.jf.intel.com> <5.0.2.1.2.20010725090426.00a91f08@gda.cadence.com> <3B5F323C.84B7B611@mentor.com>
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Hi Bob:

I have been following the non-monotonic question and I have a question to ask
regarding to the end points,  how does the parser calculate the -5.42V ? I wanted to
know where is the -5.42V coming from?

thanks
Jason Leung


"Four Errors are produced.  An example is below

ERROR - Model out_bad: The [Falling Waveform]
      with [R_fixture]=50 Ohms and [V_fixture]=0V
      has TYP column DC endpoints of  0.00V and  2.50v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages (-5.42V and  2.50V),
      a difference of -100.00% and  0.00%, respectively.

The calculated end point of -5.42 is wrong because of the non-monotonic
data.

When the non-monotonic points are commented out, 0 Errors are produced.

The testing routine should check matching voltages starting at the middle
of the I-V tables.  Some EDA tools will accept such a model.

The options are (1) fix the text, (2) reduce Error to Warning - so tools
that accept it will work, or (3) accept this as a failure - and reject the
model if the ibischk3 parser is used for the parsing."

Bob Ross wrote:

> Hello LiuWeidong and Lynne:
>
> Let me clarify that the problem in bug57 is
> not the non-monotonic behavior itself.  The
> issue is that the waveform endpoint test
> incorrectly fails.  The waveform endpoints
> are actually correct, the the non-monotonic
> behavior described in bug57 causes the parser
> itself to not find the correct endpoints.  This
> causes the model to fail because we recently
> changed the endpoint test (bug47) to issue
> an Error when the mismatch is greater than 10%.
>
> So a good model may be rejected because of
> the ibischk3 bug.  The region where the
> failure occurs however, is not critical
> (e.g., in an extended clamping region where
> no current could possibly flow anyway.  The
> easy (3) fix is just to change the current in
> that region to be monontonic.  This type of
> change would be on a case-by-case basis
> based on where the problem is.
>
> I suspect that the parser problem is based
> an algorithm that starts at one end of a
> table to find a solution.  If the algorithm
> started at the middle to find the solution,
> this would be less of a problem.
>
> See bug57 for a test case and more information:
>
>   http://www.eda.org/pub/ibis/bugs/ibischk/bug57
>
> Bob Ross
> Mentor Graphics
>
> Lynne Green wrote:
> >
> > The EDA tools have to be able to use these models, which means the models
> > must pass the parser.
> >
> > A smart user will send the model back to the person who made it, to verify
> > whether the non-monotonicity is "real", before proceeding with simulation.
> >
> > - Lynne
> >
> > At 09:13 AM 7/25/2001 +0800, LiuWeidong wrote:
> > >For the message bellow,
> > >" Even though the model is non-monotonic, it may represent real data"
> > >" (3) ignore this problem and force  the   user to modify the IBIS file."
> > >" Bob suggested that we work on (1) as a low priority activity.  If the
> > >fix  is   too difficult, then we might consider (3).  No one wanted (2).  "
> > >
> > >I want to ask:
> > >It seems that a  good model maybe is non-monotonic(right or wrong ?),Then
> > >how can we modefy the IBIS file ?
> > >
> > >Thanks,
> > >regards,
> > >LiuWeidong
> > >
> > >----- Original Message ----- >
> > > >
> > > > IBISCHK3 BUG TRACKING
> > > > - BUG57 Non-Mononic Table Causes Waveform Endpoint Test to Fail
> > > >   Bob Ross introduced BUG57 by pointing out that if the [Pulldown] and/or
> > > >   the [Pullup] table contains non-monotonic data in the clamping regions,
> > > > and
> > > >   there are no [Gnd Clamp] or [Power Clamp] tables, ibischk3 gives an
> > > >   incorrect Error message.
> > > >
> > > >   The non-monotonic data itself causes ibischk3 to calculate the wrong
> > > >   endpoint values because the algorithm probably has numerical
> > > difficulties.
> > > >   It probably starts its convergence calculation at one end of the table
> > > >   rather than from the middle and gets numerically confused with the
> > > >   non-monotonic data.
> > > >
> > > >   Even though the model is non-monotonic, it may represent real data.  Some
> > > >   EDA tools will correctly process the model.  However, the recently
> > > >   implemented Waveform endpoint tests now report an Error instead of a
> > > >   Warning, preventing the model to be processed in systems that uses
> > > > ibischk3
> > > >   for input model parsing.
> > > >
> > > >   Bob suggested classifying BUG57 as Annoying, Low, and Open.
> > > >
> > > >   The problem is how to resolve BUG57.  The choices are (1) fix the test,
> > > > (2)
> > > >   change the Error back to a Warning, or (3) ignore this problem and force
> > > > the
> > > >   user to modify the IBIS file.
> > > >
> > > >   Bob suggested that we work on (1) as a low priority activity.  If the fix
> > > > is
> > > >   too difficult, then we might consider (3).  No one wanted (2).  Stephen
> > > >   Peters suggested that a note could be added to the Warning or Error
> > > > message
> > > >   to alert the user of a possible reason for the Error Message so that the
> > > >   user could modify the model.  Bob suggested that because this is a low
> > > >   priority bug, it should be investigated after all the other open bugs are
> > > >   fixed.  Then we can decide how to proceed.
> > > >
> > > >

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From owner-ibis Thu Jul 26 11:26:58 2001
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From: John Lipsius <jlipsius@terawave.com>
To: "'Yaping Zhou'" <y.zhou@motorola.com>, ibis-users@eda.org
Subject: RE: Mutual coupling in package IBIS model
Date: Thu, 26 Jul 2001 11:26:55 -0700
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All, 

I just finished the Interconnect Modeling course with 
Gigatest Labs in Sunnyvale, CA. and, from that, I can't 
think of a situation where such an effort would be 
useful except where it's known the pkg resonances and 
coupling effects are above the application BW.  As you say, 
only the single-line characteristics are modeled.  
Also see the si-list (don't have the URL; search it at 
google.com). 

The pkg resonances can be especially pernicious; only 
known through 3D field solving.  

(The Gigatest http://www.gigatest.com/ courses are 1st 
rate. Eric Bogatin has merged with them.)

John Lipsius
Sr. Hardware Engineer 
Terawave Communications
510-401-6690



> -----Original Message-----
> From: Yaping Zhou [mailto:y.zhou@motorola.com]
> Sent: 24 July, 2001 6:44 AM
> To: ibis-users@eda.org
> Subject: Mutual coupling in package IBIS model
> 
> 
> All:
> 
> I am writing a program to generate IBIS package model using 
> Len and per
> length LRC values. Since coupling between signals is not 
> included in the
> model, I alway face a question about the applicability of the 
> model. What I
> can say is that thus-obtained model is not good for crosstalk 
> and ground
> bounce simulation (in packages), but it's still valid for 
> simulating delay,
> reflection etc. Could anyone give me a more comprehensive and 
> "official"
> answer or reference article?
> 
> Thanks in advance.
> 
> --
> **************************************
> Yaping Zhou (r3aadv)
> (512) 933-5803
> Motorola Semiconductor Products Sector
> Final Manufacturing Technology Center
> Ed Bluestein, Austin, Texas
> **************************************
> 
> 

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<P><FONT SIZE=2>All, </FONT>
</P>

<P><FONT SIZE=2>I just finished the Interconnect Modeling course with </FONT>
<BR><FONT SIZE=2>Gigatest Labs in Sunnyvale, CA. and, from that, I can't </FONT>
<BR><FONT SIZE=2>think of a situation where such an effort would be </FONT>
<BR><FONT SIZE=2>useful except where it's known the pkg resonances and </FONT>
<BR><FONT SIZE=2>coupling effects are above the application BW.&nbsp; As you say, </FONT>
<BR><FONT SIZE=2>only the single-line characteristics are modeled.&nbsp; </FONT>
<BR><FONT SIZE=2>Also see the si-list (don't have the URL; search it at </FONT>
<BR><FONT SIZE=2>google.com). </FONT>
</P>

<P><FONT SIZE=2>The pkg resonances can be especially pernicious; only </FONT>
<BR><FONT SIZE=2>known through 3D field solving.&nbsp; </FONT>
</P>

<P><FONT SIZE=2>(The Gigatest <A HREF="http://www.gigatest.com/" TARGET="_blank">http://www.gigatest.com/</A> courses are 1st </FONT>
<BR><FONT SIZE=2>rate. Eric Bogatin has merged with them.)</FONT>
</P>

<P><FONT SIZE=2>John Lipsius</FONT>
<BR><FONT SIZE=2>Sr. Hardware Engineer </FONT>
<BR><FONT SIZE=2>Terawave Communications</FONT>
<BR><FONT SIZE=2>510-401-6690</FONT>
</P>
<BR>
<BR>

<P><FONT SIZE=2>&gt; -----Original Message-----</FONT>
<BR><FONT SIZE=2>&gt; From: Yaping Zhou [<A HREF="mailto:y.zhou@motorola.com">mailto:y.zhou@motorola.com</A>]</FONT>
<BR><FONT SIZE=2>&gt; Sent: 24 July, 2001 6:44 AM</FONT>
<BR><FONT SIZE=2>&gt; To: ibis-users@eda.org</FONT>
<BR><FONT SIZE=2>&gt; Subject: Mutual coupling in package IBIS model</FONT>
<BR><FONT SIZE=2>&gt; </FONT>
<BR><FONT SIZE=2>&gt; </FONT>
<BR><FONT SIZE=2>&gt; All:</FONT>
<BR><FONT SIZE=2>&gt; </FONT>
<BR><FONT SIZE=2>&gt; I am writing a program to generate IBIS package model using </FONT>
<BR><FONT SIZE=2>&gt; Len and per</FONT>
<BR><FONT SIZE=2>&gt; length LRC values. Since coupling between signals is not </FONT>
<BR><FONT SIZE=2>&gt; included in the</FONT>
<BR><FONT SIZE=2>&gt; model, I alway face a question about the applicability of the </FONT>
<BR><FONT SIZE=2>&gt; model. What I</FONT>
<BR><FONT SIZE=2>&gt; can say is that thus-obtained model is not good for crosstalk </FONT>
<BR><FONT SIZE=2>&gt; and ground</FONT>
<BR><FONT SIZE=2>&gt; bounce simulation (in packages), but it's still valid for </FONT>
<BR><FONT SIZE=2>&gt; simulating delay,</FONT>
<BR><FONT SIZE=2>&gt; reflection etc. Could anyone give me a more comprehensive and </FONT>
<BR><FONT SIZE=2>&gt; &quot;official&quot;</FONT>
<BR><FONT SIZE=2>&gt; answer or reference article?</FONT>
<BR><FONT SIZE=2>&gt; </FONT>
<BR><FONT SIZE=2>&gt; Thanks in advance.</FONT>
<BR><FONT SIZE=2>&gt; </FONT>
<BR><FONT SIZE=2>&gt; --</FONT>
<BR><FONT SIZE=2>&gt; **************************************</FONT>
<BR><FONT SIZE=2>&gt; Yaping Zhou (r3aadv)</FONT>
<BR><FONT SIZE=2>&gt; (512) 933-5803</FONT>
<BR><FONT SIZE=2>&gt; Motorola Semiconductor Products Sector</FONT>
<BR><FONT SIZE=2>&gt; Final Manufacturing Technology Center</FONT>
<BR><FONT SIZE=2>&gt; Ed Bluestein, Austin, Texas</FONT>
<BR><FONT SIZE=2>&gt; **************************************</FONT>
<BR><FONT SIZE=2>&gt; </FONT>
<BR><FONT SIZE=2>&gt; </FONT>
</P>

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From owner-ibis Thu Jul 26 12:46:45 2001
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To: Jason Leung <jleung@cid.alcatel.com>
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Subject: Re: IBIS Bug57 Re: Minutes, IBIS Teleconference Meeting 7/20
References: <7FD5C79AD680D211AC4100A0C96B501C084A789A@orsmsx49.jf.intel.com> <5.0.2.1.2.20010725090426.00a91f08@gda.cadence.com> <3B5F323C.84B7B611@mentor.com> <3B601263.48C43F4E@cid.alcatel.com>
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Jason:

For the non-monotonic example, -5.42 (actually 5.4167)
is one solution for which the current from the
extrapolated [Pulldown] table sinks the same current
out of the 50 ohm load.  However, if the algorithm
started with voltages in the normal operating
range or midrange in the pulldown table, the
solution 0.00 would have been found that matches
the waveform end point.

Bob Ross
Mentor Graphics

Jason Leung wrote:
> 
> Hi Bob:
> 
> I have been following the non-monotonic question and I have a question to ask
> regarding to the end points,  how does the parser calculate the -5.42V ? I wanted to
> know where is the -5.42V coming from?
> 
> thanks
> Jason Leung
> 
> "Four Errors are produced.  An example is below
> 
> ERROR - Model out_bad: The [Falling Waveform]
>       with [R_fixture]=50 Ohms and [V_fixture]=0V
>       has TYP column DC endpoints of  0.00V and  2.50v, but
>       an equivalent load applied to the model's I-V tables yields
>       different voltages (-5.42V and  2.50V),
>       a difference of -100.00% and  0.00%, respectively.
> 
> The calculated end point of -5.42 is wrong because of the non-monotonic
> data.
> 
> When the non-monotonic points are commented out, 0 Errors are produced.
> 
> The testing routine should check matching voltages starting at the middle
> of the I-V tables.  Some EDA tools will accept such a model.
> 
> The options are (1) fix the text, (2) reduce Error to Warning - so tools
> that accept it will work, or (3) accept this as a failure - and reject the
> model if the ibischk3 parser is used for the parsing."
> 
> Bob Ross wrote:
> 
> > Hello LiuWeidong and Lynne:
> >
> > Let me clarify that the problem in bug57 is
> > not the non-monotonic behavior itself.  The
> > issue is that the waveform endpoint test
> > incorrectly fails.  The waveform endpoints
> > are actually correct, the the non-monotonic
> > behavior described in bug57 causes the parser
> > itself to not find the correct endpoints.  This
> > causes the model to fail because we recently
> > changed the endpoint test (bug47) to issue
> > an Error when the mismatch is greater than 10%.
> >
> > So a good model may be rejected because of
> > the ibischk3 bug.  The region where the
> > failure occurs however, is not critical
> > (e.g., in an extended clamping region where
> > no current could possibly flow anyway.  The
> > easy (3) fix is just to change the current in
> > that region to be monontonic.  This type of
> > change would be on a case-by-case basis
> > based on where the problem is.
> >
> > I suspect that the parser problem is based
> > an algorithm that starts at one end of a
> > table to find a solution.  If the algorithm
> > started at the middle to find the solution,
> > this would be less of a problem.
> >
> > See bug57 for a test case and more information:
> >
> >   http://www.eda.org/pub/ibis/bugs/ibischk/bug57
> >
> > Bob Ross
> > Mentor Graphics
> >
> > Lynne Green wrote:
> > >
> > > The EDA tools have to be able to use these models, which means the models
> > > must pass the parser.
> > >
> > > A smart user will send the model back to the person who made it, to verify
> > > whether the non-monotonicity is "real", before proceeding with simulation.
> > >
> > > - Lynne
> > >
> > > At 09:13 AM 7/25/2001 +0800, LiuWeidong wrote:
> > > >For the message bellow,
> > > >" Even though the model is non-monotonic, it may represent real data"
> > > >" (3) ignore this problem and force  the   user to modify the IBIS file."
> > > >" Bob suggested that we work on (1) as a low priority activity.  If the
> > > >fix  is   too difficult, then we might consider (3).  No one wanted (2).  "
> > > >
> > > >I want to ask:
> > > >It seems that a  good model maybe is non-monotonic(right or wrong ?),Then
> > > >how can we modefy the IBIS file ?
> > > >
> > > >Thanks,
> > > >regards,
> > > >LiuWeidong
> > > >
> > > >----- Original Message ----- >
> > > > >
> > > > > IBISCHK3 BUG TRACKING
> > > > > - BUG57 Non-Mononic Table Causes Waveform Endpoint Test to Fail
> > > > >   Bob Ross introduced BUG57 by pointing out that if the [Pulldown] and/or
> > > > >   the [Pullup] table contains non-monotonic data in the clamping regions,
> > > > > and
> > > > >   there are no [Gnd Clamp] or [Power Clamp] tables, ibischk3 gives an
> > > > >   incorrect Error message.
> > > > >
> > > > >   The non-monotonic data itself causes ibischk3 to calculate the wrong
> > > > >   endpoint values because the algorithm probably has numerical
> > > > difficulties.
> > > > >   It probably starts its convergence calculation at one end of the table
> > > > >   rather than from the middle and gets numerically confused with the
> > > > >   non-monotonic data.
> > > > >
> > > > >   Even though the model is non-monotonic, it may represent real data.  Some
> > > > >   EDA tools will correctly process the model.  However, the recently
> > > > >   implemented Waveform endpoint tests now report an Error instead of a
> > > > >   Warning, preventing the model to be processed in systems that uses
> > > > > ibischk3
> > > > >   for input model parsing.
> > > > >
> > > > >   Bob suggested classifying BUG57 as Annoying, Low, and Open.
> > > > >
> > > > >   The problem is how to resolve BUG57.  The choices are (1) fix the test,
> > > > > (2)
> > > > >   change the Error back to a Warning, or (3) ignore this problem and force
> > > > > the
> > > > >   user to modify the IBIS file.
> > > > >
> > > > >   Bob suggested that we work on (1) as a low priority activity.  If the fix
> > > > > is
> > > > >   too difficult, then we might consider (3).  No one wanted (2).  Stephen
> > > > >   Peters suggested that a note could be added to the Warning or Error
> > > > > message
> > > > >   to alert the user of a possible reason for the Error Message so that the
> > > > >   user could modify the model.  Bob suggested that because this is a low
> > > > >   priority bug, it should be investigated after all the other open bugs are
> > > > >   fixed.  Then we can decide how to proceed.
> > > > >
> > > > >
 
From owner-ibis Thu Jul 26 14:04:19 2001
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------------------------------
IBIS SUMMIT 
	FIRST CALL FOR 
		PARTICIPATION, 
			PRESENTATIONS 
				& SPONSORSHIP!!!!
-------------------------------------------------------
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

             I B I S   S U M M I T   M E E T I N G

Time/Date:      8:30 AM - 5:00 PM, Thursday, September 13, 2001

Location:       The Crowne Plaza Hotel
                10 Lincoln Square
                Worcester, MA
                Tel:  (508) 791-1600
                Fax:  (508) 791-1796
               
Content:        Presentations and Discussions

Purpose:        Solicit and Exchange IBIS Model Related Information and Ideas.

Sponsors:       North East Systems Associates, Inc. (NESA),
                IBIS Users Group
                Others to be determined
                WE ARE LOOKING FOR ADDITIONAL SPONSORS!
                  (contact Kathy Breda, breda@nesa.com
                  or Bob Ross, bob_ross@mentor.com)

PCB Conference: September 10-14, 2001
East            Worcester's Centrum Centre
                Worcester, Massachusetts
                See http://www.pcbeast.com/ for more information.

BACKGROUND

The IBIS Users Group (IBIS East) has been formed under the leadership of  
Dr. Edward Sayre from North East Systems Associates, Inc. (NESA) and has
been meeting to consider and forward IBIS model user concerns.  As a result
of East coast meetings, the group has developed an IBIS Accuracy Handbook
document and has initiated the project to format Connector Models.  These
topics plus others of current interest to the EIA IBIS Open Forum will be
discussed at this meeting.

This meeting will be conducted as a formal IBIS Summit Meeting.  Presentation
are expected to be available and archived in an electronic format, and minutes
of the meeting will be issued.  Any pending formal decisions (votes) will be
announced at least two weeks prior to the meeting.


CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development, and digital
circuit design are invited to participate to the Summit meeting.  If you plan
to participate, please register with the information below:

  Name:
  E-mail address:
  Company:
  Telephone:

Send to:

  Kathy Breda (breda@nesa.com)
  

CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS experiences
or issues.

Format of Presentation:  Overhead Projections
Time:                    15-30 Minutes
Electronic Archival:     We request electronic versions so that the
                         presentations can be archived and also made
                         available to non-attendees.  Formats used in
                         the past have been text, Power Point, Word, 
                         Postscript, and Acrobat.  Electronic presentations
                         should be made available by September 7, 2001.
                         Otherwise the presenter will be expected to provide
                         up to 50 copies for distribution.


If you plan a presentation, please supply

  Title:
  Presenter:
  E-mail address:
  Company:
  Telephone:

  Estimate Time:

Send this to:

  Kathy Breda (breda@nesa.com)


AGENDA

The agenda includes presentations, discussions, breaks, and a luncheon (which
will be provided).  This will be developed as presentation proposals are
received.  So far the following presentatation is planned:
  
  "A Proposal for s2ibis3", Michael Steer, North Carolina State University

  "Modeling the Radiated Emission of Micro-controllers", Etienne Sicard,
  National Institute of Applied Science (INSA/DEIG), France

  Plus IBIS Macro Language and demonstration, IBIS Connector Specification,
  and other IBIS issues.

LIST OF NEARBY HOTELS

See http://www.pcbeast.com for travel directions, hotels and other
information.

**************************************************************
 
From owner-ibis Sun Jul 29 19:42:08 2001
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Date: Mon, 30 Jul 2001 10:41:34 +0800
From: Hailong Wang <hlwang@avanticorp.com>
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To: ibis@eda.org, ibis-users@eda.org
Subject: About relationshipp between R_pkg,C_pkg,L_pkg and R_dut, C_dut, L_dut
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--------------8426CC510388A44ED7A61FCC
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Hi,
    I found that the R_pkg,C_pkg,L_pkg and R_dut, C_dut, L_dut have the
very similar functions. But form the IBIS Specification V3.2, I found
they are different. So I am confused, and want to the relationship
between them.

Thanks in advance!

--
Best Regards.
Hai-long Wang
Tel:021-62837026x228
Avant! Shanghai R&D Center,  16th Floor, SunTong InfoPort Plaza
No.55, West Huaihai Road, Shanghai, 200030, P.R.China



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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Hi,
<br>&nbsp;&nbsp;&nbsp; I found that the R_pkg,C_pkg,L_pkg and R_dut, C_dut,
L_dut have the very similar functions. But form the IBIS&nbsp;Specification&nbsp;V3.2,
I found they are different. So I am confused, and want to the relationship
between them.
<p>Thanks in advance!
<pre>--&nbsp;
Best Regards.
Hai-long Wang
Tel:021-62837026x228
Avant! Shanghai R&amp;D Center,&nbsp; 16th Floor, SunTong InfoPort Plaza
No.55, West Huaihai Road, Shanghai, 200030, P.R.China</pre>
&nbsp;</html>

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From owner-ibis Tue Jul 31 09:26:06 2001
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From: "Raj Raghuram" <raghu@sigrity.com>
To: <ibis@eda.org>, <ibis_users@eda.org>
Subject: Pin Mapping in IBIS models
Date: Tue, 31 Jul 2001 09:26:03 -0700
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The Pin Mapping section (optional) in IBIS 2.1 was introduced to associate
drivers with appropriate Power and Ground pins for simulation of ground and
power bounce. However, I am not able to locate any IBIS models which have
this section.

Can anybody point me to an IBIS model containing this section?

Raj Raghuram
Sigrity, Inc.
"Achieve what others can't"
raghu@sigrity.com
http://www.sigrity.com
4675 Stevens Creek Blvd. , Ste 130
Santa Clara, CA-95051
PH: 408-260-9344 x116
CELL: 408-390-9614
FAX: 408-260-9342

 
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Date: Tue, 31 Jul 2001 12:40:55 -0400
From: "Perry Qu" <perry.qu@alcatel.com>
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Subject: Using output ECL IBIS model in HSPICE
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Hi! Everyone:

I got some strange results when I tried to simulate an output ECL IBIS
model in HSPICE 99.4. Is there any particular pointd that I should pay
attention to ? I don't have similar problems with regular CMOS or TTL
IBIS models.

Thanks in advance.

Perry Qu

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