 
From owner-ibis Thu Feb  1 21:36:05 2001
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From: Syed Huq <shuq@cisco.com>
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Subject: PCI and IBIS
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IBISgurus:

The PCI spec mentions of multiple Vmeas data points based on Rising edge
or Falling edge. Since IBIS has only one Vmeas for any Output/I_O etc, how
does the model provider spec the PCI Vmeas values ?


Regards,
Syed
Cisco Systems, Inc

 
From owner-ibis Fri Feb  2 05:25:03 2001
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From: "Haller, Robert" <rhaller@cereva.com>
To: "'Syed Huq'" <shuq@cisco.com>, ibis-users@eda.org
Subject: RE: PCI and IBIS
Date: Fri, 2 Feb 2001 08:20:52 -0500 
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Syed,
	I have seen model providers pick one of the Vmeas data points
(rising edge) then insert as a comment the falling edge. It is left 
up the the user to figure out what to do next.

Some tools,  SQ for instance allows you to insert the resultant time 
point into a translated model. With a little manual intervention this
PCI spec problem is handled. A better approach would change IBIS  
to accept rising and fallig data. Othewise change the PCI spec :-)
Another capability I would suggest adding to IBIS, is the capability 
for Fast and Slow Vmeas. This will be useful for HSTL.

Regards,
Bob

Bob HAller
Cereva Networks 
  

-----Original Message-----
From: Syed Huq [mailto:shuq@cisco.com]
Sent: Friday, February 02, 2001 12:32 AM
To: ibis-users@eda.org
Subject: PCI and IBIS


IBISgurus:

The PCI spec mentions of multiple Vmeas data points based on Rising edge
or Falling edge. Since IBIS has only one Vmeas for any Output/I_O etc, how
does the model provider spec the PCI Vmeas values ?


Regards,
Syed
Cisco Systems, Inc
 
From owner-ibis Mon Feb 12 16:33:14 2001
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To: ibis@eda.org, ibis-users@eda.org, si-list@silab.eng.sun.com
Subject: EUROPEAN IBIS SUMMIT MEETING 2ND ANNOUNCEMENT
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To All:

This is the second announcement for the European IBIS Summit Meeting 
to be held on Friday, March 16, 2001 after the DATE 2001 exhibition
in Munich Germany.  The purpose is to promote communication among users
and developers of IBIS models in Europe.

The meeting is free and open to everyone.  Refreshments and a hot
lunch will be provided to all attendees.

Below is more information.  We have four presentations so far.

Bob Ross
Mentor Graphics


          E U R O P E A N   I B I S   S U M M I T   M E E T I N G
                   S E C O N D   A N N O U N C E M E N T 

Time/Date:     8:30 PM - 5:00 PM, Friday, March 16, 2001

Location:      ASTRON HOTEL/Neue Messe
               Eggenfeldener Strasse 100
               Munich, Germany 

               This hotel is near the DATE 2001 Conference

Content:       Presentations and Discussions

Purpose:       Solicit and Exchange IBIS Model Related Information and Ideas

Sponsors:      Cadence Design, Innoveda, Mentor Graphics, Zuken

DATE 2001:     March 13 - 16, 2001.  The IBIS meeting is scheduled
               the day after the DATE 2001 exhibition ends.

Location:      International Congress Center, Munich, Germany

               See http://www.date-conference.com for more information.

BACKGROUND

We have been holding interesting European IBIS Summit Meetings for the
last three years.  This year we are planning another meeting to include:

  Submitted Presentations on IBIS Topics (See below)
  Information about IBIS Version 3.2 and Activities
  Less formal Ad Hoc Presentations and Discussions
  IBIS Questions and Answers
  
Below is an invitation to register and also to submit presentations.

CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development, and digital
circuit design are invited to participate in the European IBIS Summit meeting.
If you plan to participate, please register with the information below
(deadline, March 9, 2001):

  Name:
  E-mail address:
  Company:
  Telephone:

Send to:

  Karine Loudet (karine_loudet@mentor.com)  +33 1 40 94 74 54
  
CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS experiences
or issues.  Some suggested subjects of interest are:

  IBIS Model Development Experiences
  Company IBIS Standards and Requirements
  Generating and Validating IBIS Models
  Future IBIS Requirements
  EMC/EMI IBIS Issues

Format of Presentation:  Overhead Projections
Time:                    15-30 Minutes
Electronic Archival:     We request electronic versions so that the
                         presentations can be archived and also made
                         available to non-attendees.  Formats used in
                         the past have been text, Power Point, Word, 
                         Postscript, and Acrobat.  Electronic presentations
                         should be made available by March 6, 2001.
                         Otherwise the presentor will be expected to provide
                         50 copies for distribution.

If you plan a presentation, please supply

  Title:
  Presenter:
  E-mail address:
  Company:
  Telephone:

  Estimate Time:

Send this to:

  Karine Loudet (karine_loudet@mentor.com)
  Bob Ross (bob_ross@mentor.com)

AGENDA

The agenda includes presentations, discussions.  A free lunch is scheduled
for all attendees.  Several presentations submitted so far are listed:

- Parasitic IC Emission Modeling
  Etienne Sicard, National Institute of Applied Science, Toulouse, France

- DOGEN, A Siemens Internal Model Tool, Extension 1999 - 2001
  Hans Pichlmaier, Siemens, Germany

- Title to be Determined
  Eckhard Lenski, Siemens, Germany

- LVDS Modeling
  Hazem Hegany and Mohammed Korany, Mentor Graphics, Egypt

  
FOR FURTHER INFORMATION:

Bob Ross,
Chair, EIA/IBIS Open Forum
Mentor Graphics
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070
USA

(503) 685-0732
bob_ross@mentor.com
 
From owner-ibis Wed Feb 21 08:36:35 2001
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From: "Mathew, Elizabeth (MED)" <Elizabeth.Mathew@med.ge.com>
To: ibis-users@eda.org
Subject: Question regarding ICX
Date: Wed, 21 Feb 2001 10:31:45 -0600
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Hello IBIS Gurus,
                       I had a question regarding the ICX tool (Mentor
Graphics Signal Integirty Simulation Tool). From where does the tool get
the data regarding VHmax, VHmin, VLmax and VLmin which you see in the
graph?

Thanks,
Elizabeth


Elizabeth Mathew
Signal Integrity Expert,
Global Electrical Technology Center,
GE Medical Systems,
Phone:(262)544-3776
Fax:(262)548-2315
<mailto:Elizabeth.Mathew@med.ge.com>

 
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To: "Mathew, Elizabeth (MED)" <Elizabeth.Mathew@med.ge.com>
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Elizabeth:

You need to contact Mentor Graphics directly.  We do
not discuss vendor tools on the IBIS reflectors.

Bob Ross
Mentor Graphics


"Mathew, Elizabeth (MED)" wrote:
> 
> Hello IBIS Gurus,
>                        I had a question regarding the ICX tool (Mentor
> Graphics Signal Integirty Simulation Tool). From where does the tool get
> the data regarding VHmax, VHmin, VLmax and VLmin which you see in the
> graph?
> 
> Thanks,
> Elizabeth
> 
> Elizabeth Mathew
> Signal Integrity Expert,
> Global Electrical Technology Center,
> GE Medical Systems,
> Phone:(262)544-3776
> Fax:(262)548-2315
> <mailto:Elizabeth.Mathew@med.ge.com>
 
From owner-ibis Wed Feb 23 07:21:20 2000
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To: "Mathew, Elizabeth (MED)" <Elizabeth.Mathew@med.ge.com>,
   ibis-users@eda.org
From: Dave Macemon <davem@siqual.com>
Subject: Re: Question regarding ICX
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 .ge.com>
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Hello Elizabeth,

The parameters you're asking about are derived from the IBIS model you have 
loaded.

There is a good explanation about this in the ICX IBIS User's Guide around 
pages 4-6.

Hope this helps,

davem


At 10:31 AM 2/21/2001 -0600, Mathew, Elizabeth (MED) wrote:
>Hello IBIS Gurus,
>                        I had a question regarding the ICX tool (Mentor
>Graphics Signal Integirty Simulation Tool). From where does the tool get
>the data regarding VHmax, VHmin, VLmax and VLmin which you see in the
>graph?
>
>Thanks,
>Elizabeth
>
>
>Elizabeth Mathew
>Signal Integrity Expert,
>Global Electrical Technology Center,
>GE Medical Systems,
>Phone:(262)544-3776
>Fax:(262)548-2315
><mailto:Elizabeth.Mathew@med.ge.com>

===
Dave Macemon
SiQual, A division of Stilwell Baker
davem@siqual.com
phone (503)885-1231
fax     (503)885-0550
http://www.siqual.com/

 
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Sender: haynes
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To: "ibis-users@eda.org" <ibis-users@eda.org>
Subject: What determines Vref & Rref, R_fixture & V_fixture?
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I'm starting to use s2ibis2 to create models
for a gate array library.  I don't understand
the significance of the Rref and Vref sub-parameters
under [Model].  We characterize propagation delays
for the I/O buffers in SPICE for a range of
capacitive loads on the output pad. It isn't
clear what values to use for Rref and Vref
(or Cref for that matter).

Similarly, how do I determine the values to 
use for R_fixture and V_fixture with
[Rising Waveform] and [Falling Waveform]?

-Greg Haynes
UTMC
 
From owner-ibis Fri Feb 23 11:34:46 2001
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From owner-ibis Sat Feb 24 12:11:29 2001
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Subject: Re: What determines Vref & Rref, R_fixture & V_fixture?
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Greg,

If the standard delay test for your part requires only
a capacitive load, then give C_ref but omit R_ref and
V_ref. Use the latter only if the buffer must be tested
with a pullup or pulldown resistor. You will have to
choose just one capacitive load to give as C_ref. But
this should be the load that was used to make measurements
that went into the timing info for the part.

R_fixture and V_fixture have been discussed before on this
list, but I think the best advice (from Stephen Peters)
was to consult the latest IBIS Cookbook linked from:

  http://www.eigroup.org/ibis/tools.htm

You will not find "R_fixture" in there, but Table 1 gives
recommended values for waveform fixtures.

Mike LaBonte

Greg Haynes wrote:
> 
> I'm starting to use s2ibis2 to create models
> for a gate array library.  I don't understand
> the significance of the Rref and Vref sub-parameters
> under [Model].  We characterize propagation delays
> for the I/O buffers in SPICE for a range of
> capacitive loads on the output pad. It isn't
> clear what values to use for Rref and Vref
> (or Cref for that matter).
> 
> Similarly, how do I determine the values to
> use for R_fixture and V_fixture with
> [Rising Waveform] and [Falling Waveform]?
> 
> -Greg Haynes
> UTMC
 
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From: Koller Katja <Katja.Koller@icn.siemens.de>
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Date: Tue, 27 Feb 2001 15:16:37 +0100
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Katja.Koller@icn.siemens.de
 
From owner-ibis Tue Feb 27 08:59:58 2001
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From: Ted Tontis <ttontis@engagenet.com>
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Ted Tontis 
Design Engineer 
Engage Networks Inc. 
TTontis@engagenet.com 
PH 414.273.7600 Ext. 7607    <http://www.engagenet.com> 


 
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To: ibis@eda.org, ibis-users@eda.org, si-list@silab.eng.sun.com
Subject: EUROPEAN IBIS SUMMIT 3/16/01 - THIRD ANNOUNCEMENT
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To All:

This is the third announcement for the European IBIS Summit Meeting 
to be held on Friday, March 16, 2001 after the DATE 2001 exhibition
in Munich Germany.  The purpose is to promote communication among users
and developers of IBIS models in Europe.

The meeting is free and open to everyone.  Refreshments and a hot
lunch will be provided to all attendees.

Below is more information.  We have approximately 11 presentations
so far listed below.  Some titles are tentative.

If you have not done so, please respond to Karine Loudet if you
are attending.

Bob Ross
Mentor Graphics


          E U R O P E A N   I B I S   S U M M I T   M E E T I N G
                    T H I R D   A N N O U N C E M E N T 

Time/Date:     8:30 PM - 5:00 PM, Friday, March 16, 2001

Location:      ASTRON HOTEL/Neue Messe
               Eggenfeldener Strasse 100
               Munich, Germany 

               This hotel is near the DATE 2001 Conference

Content:       Presentations and Discussions

Purpose:       Solicit and Exchange IBIS Model Related Information and Ideas

Sponsors:      Cadence Design, Innoveda, Mentor Graphics, Zuken

DATE 2001:     March 13 - 16, 2001.  The IBIS meeting is scheduled
               the day after the DATE 2001 exhibition ends.

Location:      International Congress Center, Munich, Germany

               See http://www.date-conference.com for more information.

BACKGROUND

We have been holding interesting European IBIS Summit Meetings for the
last three years.  This year we are planning another meeting to include:

  Submitted Presentations on IBIS Topics (See below)
  Information about IBIS Version 3.2 and Activities
  Less formal Ad Hoc Presentations and Discussions
  IBIS Questions and Answers
  
Below is an invitation to register and also to submit presentations.

CALL FOR PARTICIPANTS

People involved in IBIS Model development, EDA tool development, and digital
circuit design are invited to participate in the European IBIS Summit meeting.
If you plan to participate, please register with the information below
(deadline, March 9, 2001):

  Name:
  E-mail address:
  Company:
  Telephone:

Send to:

  Karine Loudet (karine_loudet@mentor.com)  +33 1 40 94 74 54
  
CALL FOR PRESENTATIONS

We are seeking presentations from individuals who have IBIS experiences
or issues.  Some suggested subjects of interest are:

  IBIS Model Development Experiences
  Company IBIS Standards and Requirements
  Generating and Validating IBIS Models
  Future IBIS Requirements
  EMC/EMI IBIS Issues

Format of Presentation:  Overhead Projections
Time:                    15-30 Minutes
Electronic Archival:     We request electronic versions so that the
                         presentations can be archived and also made
                         available to non-attendees.  Formats used in
                         the past have been text, Power Point, Word, 
                         Postscript, and Acrobat.  Electronic presentations
                         should be made available by March 6, 2001.
                         Otherwise the presentor will be expected to provide
                         50 copies for distribution.

If you plan a presentation, please supply

  Title:
  Presenter:
  E-mail address:
  Company:
  Telephone:

  Estimate Time:

Send this to:

  Karine Loudet (karine_loudet@mentor.com)
  Bob Ross (bob_ross@mentor.com)

AGENDA

The agenda includes presentations, discussions.  A free lunch is scheduled
for all attendees.  Some titles have not been finalized:

- EMC Standardization Progress (title to be determined)
  Jean-Claude Perrin, Texas Instruments, France

- EMC Models (title to be determined)
  Christian Marot, Siemens, France

- Parasitic IC Emisson Modeling
  Etienne Sicard, National Institute of Applied Science, Toulouse, France

- Ground-Noise Model
  Mariusz Faferko, Fraunhofer Institute Reliability and Microintegration,
  Germany

- Radiated Emission Model for IC
  Peter Kralicek, Fraunhofer Institute Reliability and Microintegration,
  Germany

- DOGEN, A Siemens Internal Model Tool, Extension 1999 - 2001
  Hans Pichlmaier, Siemens AG, Germany

- Experiences with and Tips for IBIS Models
  Eckhard Lenski, Siemens AG, Germany

- IBIS Bus Modeling (title to be determined)
  Bernhard Unger, Siemens AG, Germany

- LVDS Modeling
  Hazem Hegany and Mohammed Korany, Mentor Graphics, Egypt

- (title to be determined)
  John Barrie, Zuken, England

- IBIS-X
  Arpad Muranyi, Intel, USA
  
FOR FURTHER INFORMATION:

Bob Ross,
Chair, EIA/IBIS Open Forum
Mentor Graphics
8005 S.W. Boeckman Road
Wilsonville, Oregon 97070
USA

(503) 685-0732
bob_ross@mentor.com
 
From owner-ibis Tue Feb 27 15:34:47 2001
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From: Girish_Singh@Dell.com
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Subject: Subscribe!
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-Girish

Simulation Engineer
Signal Integrity Group
Dell Computer Corporation.
(512)-723-6210
E-Mail:Girish_Singh@Dell.com
www.dell.com


 
From owner-ibis Tue Feb 27 15:34:37 2001
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From: Girish_Singh@Dell.com
To: ibis-users@eda.org
Subject: PCI/PCIX STANDARD IBIS MODELS...
Date: Tue, 27 Feb 2001 17:33:35 -0600
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Hi All,
Does anyone have a standard PCI and PCIX IBIS Model?
I have a standard PCIX Model but the test load seems to be too heavy for the
Weak Buffer(Tval(max)Rising/Falling Edge Test Load).I made my PCIX Model
from the PCIX Bus Specifications,Rev 1.0. 
Thanks in advance for the help.
-Girish 


 
From owner-ibis Tue Feb 27 17:24:22 2001
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-Girish


Simulation Engineer
Signal Integrity Group
Dell Computer Corporation.
(512)-723-6210
E-Mail:Girish_Singh@Dell.com
www.dell.com


 
From owner-ibis Tue Feb 27 17:25:36 2001
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From: Girish_Singh@Dell.com
To: ibis-users@vhdl.org
Subject: PCI?PCIX STANDARD IBIS MODELS...
Date: Tue, 27 Feb 2001 17:35:15 -0600
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Hi All,
Does anyone have a standard PCI and PCIX IBIS Model?
I have a standard PCIX Model but the test load seems to be too heavy for the
Weak Buffer(Tval(max)Rising/Falling Edge Test Load).I made my PCIX Model
from the PCIX Bus Specifications,Rev 1.0. 
Thanks in advance for the help.

-Girish


Simulation Engineer
Signal Integrity Group
Dell Computer Corporation.
(512)-723-6210
E-Mail:Girish_Singh@Dell.com
www.dell.com
	 


