 
From owner-ibis Sun Apr  1 01:49:27 2001
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From: Dimitry Aizenstat <dimita@taux01.nsc.com>
Organization: National Semiconductor
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To: ibis-users@vhdl.org
Subject: hspice failed on io_buffer IBIS model
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 Hi, all!
 I have a problem with IBIS model that I created via s2ibis: when I run
hspice with this model using "b_io" instance statement (actually the
customer needs run it), the error "incorrect Pull_Down and/or Pull_Up
data" appears, but tables itself looks ok in *.ibs file.I use 1999.2
version of the Star-Hspice.
 Maybe someone has experience with using IBIS buffer model in hspice &
debugging of same errors? 
 Thank you for your help.
 Regards,
         Dmitry
-- 
 +---------------------------------------------------------+
 | Dmitry Aizenshtat         Circuit Design Engineer, NSTA | 
 | Tel : 972-9-9702-020               Fax : 972-9-9702-001 |
 | mailto:dimita@taux01.nsc.com                            |
 +---------------------------------------------------------+
 
From owner-ibis Mon Apr  2 08:27:02 2001
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To: Dimitry Aizenstat <dimita@taux01.nsc.com>
CC: ibis-users@vhdl.org
Subject: Re: hspice failed on io_buffer IBIS model
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Dimitry Aizenstat wrote:
> 
>  Hi, all!
>  I have a problem with IBIS model that I created via s2ibis: when I run
> hspice with this model using "b_io" instance statement (actually the
> customer needs run it), the error "incorrect Pull_Down and/or Pull_Up
> data" appears, but tables itself looks ok in *.ibs file.I use 1999.2
> version of the Star-Hspice.
>  Maybe someone has experience with using IBIS buffer model in hspice &
> debugging of same errors?
>  Thank you for your help.
>  Regards,
>          Dmitry
> --
>  +---------------------------------------------------------+
>  | Dmitry Aizenshtat         Circuit Design Engineer, NSTA |
>  | Tel : 972-9-9702-020               Fax : 972-9-9702-001 |
>  | mailto:dimita@taux01.nsc.com                            |
>  +---------------------------------------------------------+

If you have your maintenance in force, your best bet would be
to call the HSPICE hotline: 800.346.5953.

If you don't have maintenance in force, why not?


-- 
Kim Helliwell
Senior CAE Engineer
Acuson Corporation
Phone: 650 694 5030  FAX: 650 943 7260
 
From owner-ibis Mon Apr  2 11:04:04 2001
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From: "Mathew, Elizabeth (MED)" <Elizabeth.Mathew@med.ge.com>
To: "IBIS User Group (E-mail)" <ibis-users@vhdl.org>
Subject: S2IBIS
Date: Mon, 2 Apr 2001 13:02:45 -0500 
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Hi IBIS gurus,
               Is there anyone in the users group who is using the NT
version of the s2ibis tool (Spice to IBIS translator)?  Please reply to
me if you are.

Thanks,
Elizabeth 


Elizabeth Mathew
Signal Integrity Expert,
Global Electrical Technology Center,
GE Medical Systems,
Phone:(262)544-3776
Fax:(262)548-2315
<mailto:Elizabeth.Mathew@med.ge.com>

 
From owner-ibis Tue Apr  3 14:12:37 2001
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Message-ID: <3ACA3B29.BBFF54CB@xilinx.com>
Date: Tue, 03 Apr 2001 15:05:45 -0600
From: "Linda Echo-Hawk" <Linda.Echo-Hawk@xilinx.com>
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Can you tell me if you plan to enhance the golden parser to accept the
longer filenames (20 character basename plus .ibs) supported in Version
3.2?  I just downloaded the latest ibischk3 (V3.2.7) but it complains
about name lengths longer than 12.

Thanks --
Linda Echo-Hawk

 
From owner-ibis Tue Apr  3 15:32:10 2001
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To: Linda Echo-Hawk <Linda.Echo-Hawk@xilinx.com>
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Linda:

If the file is given 

  [IBIS Ver] 3.2

no errors should be issued.

However, if the file is given

  [IBIS Ver] 2.1

or below, you will get the name length error.

IBIS Version 2.1 files still have the 12 character
total name length restriction.

Bob Ross
Mentor Graphics



Linda Echo-Hawk wrote:
> 
> Can you tell me if you plan to enhance the golden parser to accept the
> longer filenames (20 character basename plus .ibs) supported in Version
> 3.2?  I just downloaded the latest ibischk3 (V3.2.7) but it complains
> about name lengths longer than 12.
> 
> Thanks --
> Linda Echo-Hawk
 
From owner-ibis Wed Apr  4 06:34:47 2001
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Date: Wed, 04 Apr 2001 08:33:29 -0500
From: "DORIN OPREA" <dorin.oprea@alcatel.com>
Organization: Newbridge Networks Corporation
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Hi,

The circuit to simulate is: a differential buffer driving a transformer.
The model we received for the IC device is an IBIS model. The question
is: Can IBIS model be used within HSPICE for analog simulation ?

Thanks,
Dorin

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Hi everyone:
I am trying to verify a IBIS model which consists of a zero rise time
for the driver:
| variable       typ                 min                 max
dV/dt_r            0/0                 0/0                  0/0
dV/dt_f          2.0448/0.4029n      1.8546/0.4176n      2.1792/0.4102n
R_load = 50.0000

My question is :does anyone know how the IBIS translator going to handle
this situation??
thanks alot
Best Regards
Jason Leung

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From owner-ibis Wed Apr  4 07:22:30 2001
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Subject: Re: zero risetime in the IBIS model
To: "ibis-users@eda.org" <ibis-users@eda.org>
From: Adam.Tambone@fairchildsemi.com
Date: Wed, 4 Apr 2001 10:18:26 -0400
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Jason,

     I'm not sure what translator you are using but the HSPICE translator
will by default use ramp data for determining switching characteristics in
DC and transient analysis.  You can specify that the translator use the
rising and falling waveform data instead.  See Chapter 18 of the Avanti
HSPICE User's Manual.

Adam Tambone
Fairchild Semiconductor



Hi everyone:
I am trying to verify a IBIS model which consists of a zero rise time
for the driver:
| variable       typ                 min                 max
dV/dt_r            0/0                 0/0                  0/0
dV/dt_f          2.0448/0.4029n      1.8546/0.4176n      2.1792/0.4102n
R_load = 50.0000

My question is :does anyone know how the IBIS translator going to handle
this situation??
thanks alot
Best Regards
Jason Leung

 
From owner-ibis Wed Apr  4 07:33:20 2001
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Subject: Re: zero risetime in the IBIS model
Date: Wed, 4 Apr 2001 07:33:13 -0700
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Dear Jason Leung,

What IBIS translator are you referring to?  The IBIS Golden Parser (IBISCHK3
ver 3.2.7) will flag the model as invalid.

Best regards,
Matthew Flora



----- Original Message ----- 
From: "Jason Leung" <jleung@cid.alcatel.com>
To: <ibis-users@eda.org>
Sent: Wednesday, April 04, 2001 6:58 AM
Subject: Re: zero risetime in the IBIS model


> Hi everyone:
> I am trying to verify a IBIS model which consists of a zero rise time
> for the driver:
> | variable       typ                 min                 max
> dV/dt_r            0/0                 0/0                  0/0
> dV/dt_f          2.0448/0.4029n      1.8546/0.4176n      2.1792/0.4102n
> R_load = 50.0000
> 
> My question is :does anyone know how the IBIS translator going to handle
> this situation??
> thanks alot
> Best Regards
> Jason Leung
> 

 
From owner-ibis Wed Apr  4 07:41:07 2001
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From: Aubrey_Sparkman@Dell.com
To: Adam.Tambone@fairchildsemi.com, ibis-users@eda.org
Subject: RE: zero risetime in the IBIS model
Date: Wed, 4 Apr 2001 09:36:30 -0500 
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Jason,
Even if your simulator's translator doesn't complain, your simulator may go
nuts and give VERY "interesting" results.  Go back to your supplier and
insist that the ramp data match the VT data.

Aubrey Sparkman
Signal Integrity
Aubrey_Sparkman@Dell.com
(512) 723-3592


> -----Original Message-----
> From: Adam.Tambone@fairchildsemi.com
> [mailto:Adam.Tambone@fairchildsemi.com]
> Sent: Wednesday, April 04, 2001 9:18 AM
> To: ibis-users@eda.org
> Subject: Re: zero risetime in the IBIS model
> 
> 
> Jason,
> 
>      I'm not sure what translator you are using but the 
> HSPICE translator
> will by default use ramp data for determining switching 
> characteristics in
> DC and transient analysis.  You can specify that the 
> translator use the
> rising and falling waveform data instead.  See Chapter 18 of 
> the Avanti
> HSPICE User's Manual.
> 
> Adam Tambone
> Fairchild Semiconductor
> 
> 
> 
> Hi everyone:
> I am trying to verify a IBIS model which consists of a zero rise time
> for the driver:
> | variable       typ                 min                 max
> dV/dt_r            0/0                 0/0                  0/0
> dV/dt_f          2.0448/0.4029n      1.8546/0.4176n      
> 2.1792/0.4102n
> R_load = 50.0000
> 
> My question is :does anyone know how the IBIS translator 
> going to handle
> this situation??
> thanks alot
> Best Regards
> Jason Leung
> 
> 


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From owner-ibis Wed Apr  4 08:13:44 2001
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To: Matthew Flora <mbflora@mail.hyperlynx.com>
CC: ibis-users@eda.org
Subject: Re: zero risetime in the IBIS model
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Hi Matthew Flora:
Thanks for your comment . I am using IBIS2XTK V5.01 , but the golden Parser
doesn't show any error message at the end.

Thanks alot
Jason Leung


Matthew Flora wrote:

> Dear Jason Leung,
>
> What IBIS translator are you referring to?  The IBIS Golden Parser (IBISCHK3
> ver 3.2.7) will flag the model as invalid.
>
> Best regards,
> Matthew Flora
>
> ----- Original Message -----
> From: "Jason Leung" <jleung@cid.alcatel.com>
> To: <ibis-users@eda.org>
> Sent: Wednesday, April 04, 2001 6:58 AM
> Subject: Re: zero risetime in the IBIS model
>
> > Hi everyone:
> > I am trying to verify a IBIS model which consists of a zero rise time
> > for the driver:
> > | variable       typ                 min                 max
> > dV/dt_r            0/0                 0/0                  0/0
> > dV/dt_f          2.0448/0.4029n      1.8546/0.4176n      2.1792/0.4102n
> > R_load = 50.0000
> >
> > My question is :does anyone know how the IBIS translator going to handle
> > this situation??
> > thanks alot
> > Best Regards
> > Jason Leung
> >

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From owner-ibis Wed Apr  4 08:34:34 2001
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From: "Dunbar, Tony" <tony_dunbar@mentorg.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: RE: zero risetime in the IBIS model
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Jason,

One subtle point here is whether, or not, the [Model] that has this dV/dt_r
parameter also has waveform tables. If it does, the [Ramp] parameters should
be ignored by the simulator, anyway.

Neverthless, as has been suggested already, I would also strongly encourage
you to throw the model back at the vendor that supplied it.

This sort of clumsy or outright bad modeling continues in part, I believe,
because we, as consumers, tweak this and change that without letting our
suppliers know they are producing garbage. Sorry to rant on, but this is a
pet subject of mine because it wastes too much of my time and WAY TOO MUCH
of my customers' time. If it was a part for my car brakes that didn't quite
fit, what would I do? Closer to the point, if it was a VHDL model that
wasn't quite right and the ASIC didn't work, what would you and your
management do.

Signed,
Mr. Angry
(Tony Angry, that is!)

-----Original Message-----
From: Jason Leung [mailto:jleung@cid.alcatel.com]
Sent: Wednesday, April 04, 2001 8:59 AM
To: ibis-users@eda.org
Subject: Re: zero risetime in the IBIS model


Hi everyone:
I am trying to verify a IBIS model which consists of a zero rise time
for the driver:
| variable       typ                 min                 max
dV/dt_r            0/0                 0/0                  0/0
dV/dt_f          2.0448/0.4029n      1.8546/0.4176n      2.1792/0.4102n
R_load = 50.0000

My question is :does anyone know how the IBIS translator going to handle
this situation??
thanks alot
Best Regards
Jason Leung
 
From owner-ibis Wed Apr  4 08:43:13 2001
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Hi Aubrey Sparkman:
So even though the translator doesn't complain about the zero rise time in the
driver model, the translator will go "nuts" ehh? So the waveform come after
the simulation will have no meaning ehh?
what do you mean by" ramp data match the VT data"?
thanks alot
Jason Leung


> Jason,
> Even if your simulator's translator doesn't complain, your simulator may go
> nuts and give VERY "interesting" results.  Go back to your supplier and
> insist that the ramp data match the VT data.
>
> Aubrey Sparkman
> Signal Integrity
> Aubrey_Sparkman@Dell.com
> (512) 723-3592
>
> > -----Original Message-----
> > From: Adam.Tambone@fairchildsemi.com
> > [mailto:Adam.Tambone@fairchildsemi.com]
> > Sent: Wednesday, April 04, 2001 9:18 AM
> > To: ibis-users@eda.org
> > Subject: Re: zero risetime in the IBIS model
> >
> >
> > Jason,
> >
> >      I'm not sure what translator you are using but the
> > HSPICE translator
> > will by default use ramp data for determining switching
> > characteristics in
> > DC and transient analysis.  You can specify that the
> > translator use the
> > rising and falling waveform data instead.  See Chapter 18 of
> > the Avanti
> > HSPICE User's Manual.
> >
> > Adam Tambone
> > Fairchild Semiconductor
> >
> >
> >
> > Hi everyone:
> > I am trying to verify a IBIS model which consists of a zero rise time
> > for the driver:
> > | variable       typ                 min                 max
> > dV/dt_r            0/0                 0/0                  0/0
> > dV/dt_f          2.0448/0.4029n      1.8546/0.4176n
> > 2.1792/0.4102n
> > R_load = 50.0000
> >
> > My question is :does anyone know how the IBIS translator
> > going to handle
> > this situation??
> > thanks alot
> > Best Regards
> > Jason Leung
> >
> >

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From owner-ibis Wed Apr  4 09:02:42 2001
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From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
Subject: RE: zero risetime in the IBIS model
Date: Wed, 4 Apr 2001 12:02:06 -0400 
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> One subtle point here is whether, or not, the [Model] that has this
> dV/dt_r
> parameter also has waveform tables. If it does, the [Ramp] parameters
> should
> be ignored by the simulator, anyway.
 
Not all simulators use the [Rising Waveform] and [Falling Waveform] data if
it's there.  That is one reason why IBIS requires the [Ramp] data even if
the waveforms are also provided.

Even if the simulator does use the waveform tables, is it prohibited from
looking at the [Ramp] data?  Conceivably, its algorithms might use the
[Ramp] data, either to enhance its accuracy somehow, or as an internal
"sanity check" that the tables and [Ramp] data are consistent.

Presumably, the 0/0 values mean the person who created the IBIS data sheet,
didn't finish.  There may be valid reasons for doing that; perhaps this is a
preliminary model and its customers know and understand that.  I won't argue
that it needs to be fixed, but I don't know the circumstances here.

In the interim, personally I would want to avoid 0/0, since it might be
mathematically problematic, with unpredictable results.  If I were you, I'd
substitute something like 1/1, which I think should be less likely to cause
an unexpected outcome.  Either the simulator doesn't use it, or you should
see very slow rising edges in your simulations which should stand out and
tell you that this model is incomplete for those edges.  That is better than
the simulator blowing its brain to bits and scribbling all over your disk or
something.

Andy

 
From owner-ibis Wed Apr  4 09:15:39 2001
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Subject: RE: zero risetime in the IBIS model
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
From: Adam.Tambone@fairchildsemi.com
Date: Wed, 4 Apr 2001 12:11:46 -0400
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Jason,

     If  V/t data is included in the IBIS datasheet a solution might be to
determine the slope of the line defined by the 20% and 80% points of the
V/t waveform and use this value for the ramp parameter of interest.  As
previously mentioned you should not have to do this 'fix'.

Adam Tambone



 
From owner-ibis Wed Apr  4 09:21:01 2001
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Andy,

I think you have a pretty good handle on what is likely to happen.
I can expand a little ...

Some environments use the Ramp data to make some basic decisions about
how to set up the simulations.

e.g. which driver on a bi-directional net is likely to cause the
greatest amount of crosstalk.

The infinite edge rate in this case could cause unintended results
even before it gets to the simulator.

Ian Dodd

"Ingraham, Andrew" wrote:
> 
> > One subtle point here is whether, or not, the [Model] that has this
> > dV/dt_r
> > parameter also has waveform tables. If it does, the [Ramp] parameters
> > should
> > be ignored by the simulator, anyway.
> 
> Not all simulators use the [Rising Waveform] and [Falling Waveform] data if
> it's there.  That is one reason why IBIS requires the [Ramp] data even if
> the waveforms are also provided.
> 
> Even if the simulator does use the waveform tables, is it prohibited from
> looking at the [Ramp] data?  Conceivably, its algorithms might use the
> [Ramp] data, either to enhance its accuracy somehow, or as an internal
> "sanity check" that the tables and [Ramp] data are consistent.
> 
> Presumably, the 0/0 values mean the person who created the IBIS data sheet,
> didn't finish.  There may be valid reasons for doing that; perhaps this is a
> preliminary model and its customers know and understand that.  I won't argue
> that it needs to be fixed, but I don't know the circumstances here.
> 
> In the interim, personally I would want to avoid 0/0, since it might be
> mathematically problematic, with unpredictable results.  If I were you, I'd
> substitute something like 1/1, which I think should be less likely to cause
> an unexpected outcome.  Either the simulator doesn't use it, or you should
> see very slow rising edges in your simulations which should stand out and
> tell you that this model is incomplete for those edges.  That is better than
> the simulator blowing its brain to bits and scribbling all over your disk or
> something.
> 
> Andy
 
From owner-ibis Wed Apr  4 11:47:58 2001
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From: Aubrey_Sparkman@Dell.com
To: jleung@cid.alcatel.com
Cc: Adam.Tambone@fairchildsemi.com, ibis-users@eda.org
Subject: RE: zero risetime in the IBIS model
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Jason,
Yes, I have seen a simulator go nuts and produce a very strange meaningless
waveform.  Problem went away when the [Ramp] data was corrected.

ramp data matching the VT data means that they should agree, both come from
time-based data, perhaps even the same load.

From a purist point of view, I'm not an IBIS expert and I don't want to
change the data my supplier gives me.  But if your boss wants results NOW
with your best GUESS, as another suggested, you can build your own Ramp data
from the V/T data.  Use the Rising Waveform for the dV/dt_r (R_fixture to
ground if there are two).  Use the Falling Waveform for the dV/dt_f
(R_fixture to V_fixtuer if there are two).
dV=0.6*(Vmax-Vmin)
dt_x is the difference in time between the 20% and 80% voltage points.

Good Luck!

Aubrey Sparkman
Signal Integrity
Aubrey_Sparkman@Dell.com
(512) 723-3592


> -----Original Message-----
> From: Jason Leung [mailto:jleung@cid.alcatel.com]
> Sent: Wednesday, April 04, 2001 10:36 AM
> To: Aubrey_Sparkman@exchange.dell.com
> Cc: Adam.Tambone@fairchildsemi.com; ibis-users@eda.org
> Subject: Re: zero risetime in the IBIS model
> 
> 
> Hi Aubrey Sparkman:
> So even though the translator doesn't complain about the zero 
> rise time in the
> driver model, the translator will go "nuts" ehh? So the 
> waveform come after
> the simulation will have no meaning ehh?
> what do you mean by" ramp data match the VT data"?
> thanks alot
> Jason Leung
> 
> 
> > Jason,
> > Even if your simulator's translator doesn't complain, your 
> simulator may go
> > nuts and give VERY "interesting" results.  Go back to your 
> supplier and
> > insist that the ramp data match the VT data.
> >
> > Aubrey Sparkman
> > Signal Integrity
> > Aubrey_Sparkman@Dell.com
> > (512) 723-3592
> >
> > > -----Original Message-----
> > > From: Adam.Tambone@fairchildsemi.com
> > > [mailto:Adam.Tambone@fairchildsemi.com]
> > > Sent: Wednesday, April 04, 2001 9:18 AM
> > > To: ibis-users@eda.org
> > > Subject: Re: zero risetime in the IBIS model
> > >
> > >
> > > Jason,
> > >
> > >      I'm not sure what translator you are using but the
> > > HSPICE translator
> > > will by default use ramp data for determining switching
> > > characteristics in
> > > DC and transient analysis.  You can specify that the
> > > translator use the
> > > rising and falling waveform data instead.  See Chapter 18 of
> > > the Avanti
> > > HSPICE User's Manual.
> > >
> > > Adam Tambone
> > > Fairchild Semiconductor
> > >
> > >
> > >
> > > Hi everyone:
> > > I am trying to verify a IBIS model which consists of a 
> zero rise time
> > > for the driver:
> > > | variable       typ                 min                 max
> > > dV/dt_r            0/0                 0/0                  0/0
> > > dV/dt_f          2.0448/0.4029n      1.8546/0.4176n
> > > 2.1792/0.4102n
> > > R_load = 50.0000
> > >
> > > My question is :does anyone know how the IBIS translator
> > > going to handle
> > > this situation??
> > > thanks alot
> > > Best Regards
> > > Jason Leung
> > >
> > >
> 


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	Thu, 5 Apr 2001 14:16:15 +0200 (IST)
Subject: IBIS connector modeling
To: ibis-users@eda.org, ibis-info@eda.org
Cc: Yossi.Makai@ecitele.com, Daniel.Adar@ecitele.com,
   Naftali.Refaeli@ecitele.com
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We at ECI are interested in getting information from users who have
generated IBIS connector models.
(The "Connector Info" button at the http://www.eigroup.org/ibis/ibis.htm
site gave us gibberish).
Please send me information, references, and/or contact information on this
subject.

 
From owner-ibis Thu Apr  5 13:11:07 2001
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From owner-ibis Thu Apr  5 17:49:26 2001
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To: Larry.Odess@ecitele.com
CC: ibis-users@eda.org, ibis-info@eda.org, Yossi.Makai@ecitele.com,
   Daniel.Adar@ecitele.com, Naftali.Refaeli@ecitele.com
Subject: Re: IBIS connector modeling
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Larry:

The IBIS Connector Specification is still being developed.
There are no official IBIS models or users at this time.

You would need to contact EDA Vendors directly regarding their
connector modeling solutions.

Best Regards,
Bob Ross
Mentor Graphics

Larry.Odess@ecitele.com wrote:
> 
> We at ECI are interested in getting information from users who have
> generated IBIS connector models.
> (The "Connector Info" button at the http://www.eigroup.org/ibis/ibis.htm
> site gave us gibberish).
> Please send me information, references, and/or contact information on this
> subject.
 
From owner-ibis Mon Apr  9 06:19:27 2001
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Hi all:
Morning!
I am trying to obtain the output impedance of a driver, so that I can
match the driver with a transmission line and proper termination.
The way that I have tried is I used the IBIS model and then translate
the model into QUAD model, so that I can used the XNS to observe their
rising and falling waveform. Moreover I am trying to find its output
impedance in XNS.
My question is : Does anyone ever try finding the output impedance of a
driver? AND how did you achieve that?

Thanks very much for your comment!
Jason leung


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From owner-ibis Mon Apr  9 07:59:23 2001
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: ibis-users@eda.org
Subject: RE: output impedance of a driver
Date: Mon, 9 Apr 2001 07:58:16 -0700 
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Jason,

The DC impedance can be found by dividing V/I on the IV curve of
the buffer.  You will find that you get a different value at
practically any of the voltages due to the non linear shape of
the IV curve.  Plus, the process variation of a chip can give
you a variation on the order of 2-3x.  So finding the impedance
and matching the T-line to it is like shooting at a moving target.

The reason I said DC impedance above is because the capacitive
components of the buffer will also alter the impedance of the
buffer a higher frequencies.

Arpad Muranyi
Intel Corporation
================================================================

-----Original Message-----
From: Jason Leung [mailto:jleung@cid.alcatel.com]
Sent: Monday, April 09, 2001 6:14 AM
To: ibis-users@eda.org
Subject: Re: output impedance of a driver


Hi all:
Morning!
I am trying to obtain the output impedance of a driver, so that I can
match the driver with a transmission line and proper termination.
The way that I have tried is I used the IBIS model and then translate
the model into QUAD model, so that I can used the XNS to observe their
rising and falling waveform. Moreover I am trying to find its output
impedance in XNS.
My question is : Does anyone ever try finding the output impedance of a
driver? AND how did you achieve that?

Thanks very much for your comment!
Jason leung


 
From owner-ibis Mon Apr  9 09:16:48 2001
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Date: Mon, 09 Apr 2001 09:16:01 -0700
From: Scott McMorrow <scott@vasthorizons.com>
Organization: SiQual
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To: Jason Leung <jleung@cid.alcatel.com>
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Jason,

If the ibis model has been extracted correctly, then the Ramp data
will tell you what the saturated output impedance is.

The IBIS V/I curves give you the impedance of an output buffer
at any voltage.  I usually use 1 volts as a good place to measure
impedance, since it is in the linear portion of the buffer curve.
For the pullup and pulldown curve, go to the 1V row and read
off the current.  Since R=V/I, the output channel resistance can
be calculated.

For example, if at 1 Volt the current is 35mA, then the
output impedance is 28.57 ohms.

regards,

scott


--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com



Jason Leung wrote:

> Hi all:
> Morning!
> I am trying to obtain the output impedance of a driver, so that I can
> match the driver with a transmission line and proper termination.
> The way that I have tried is I used the IBIS model and then translate
> the model into QUAD model, so that I can used the XNS to observe their
> rising and falling waveform. Moreover I am trying to find its output
> impedance in XNS.
> My question is : Does anyone ever try finding the output impedance of a
> driver? AND how did you achieve that?
>
> Thanks very much for your comment!
> Jason leung



 
From owner-ibis Mon Apr  9 09:43:07 2001
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CC: "ibis-users@eda.org" <ibis-users@eda.org>
Subject: Re: output impedance of a driver
References: <3AD1B598.C7F5B835@cid.alcatel.com> <3AD1E041.88040233@vasthorizons.com>
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Hi Scott McMorrow :
Thanks very much for your advice!
So if we wanted to find the output impedance for the driver ,we just have to

go to 1V row and then read off the corresponding current value eh?
Should I do that on the Pull up curve or the pull down curve?

thanks
Regards
Jason Leung


> Jason,
>
> If the ibis model has been extracted correctly, then the Ramp data
> will tell you what the saturated output impedance is.
>
> The IBIS V/I curves give you the impedance of an output buffer
> at any voltage.  I usually use 1 volts as a good place to measure
> impedance, since it is in the linear portion of the buffer curve.
> For the pullup and pulldown curve, go to the 1V row and read
> off the current.  Since R=V/I, the output channel resistance can
> be calculated.
>
> For example, if at 1 Volt the current is 35mA, then the
> output impedance is 28.57 ohms.
>
> regards,
>
> scott
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
>
> Jason Leung wrote:
>
> > Hi all:
> > Morning!
> > I am trying to obtain the output impedance of a driver, so that I can
> > match the driver with a transmission line and proper termination.
> > The way that I have tried is I used the IBIS model and then translate
> > the model into QUAD model, so that I can used the XNS to observe their
> > rising and falling waveform. Moreover I am trying to find its output
> > impedance in XNS.
> > My question is : Does anyone ever try finding the output impedance of a
> > driver? AND how did you achieve that?
> >
> > Thanks very much for your comment!
> > Jason leung

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From owner-ibis Mon Apr  9 09:48:46 2001
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From: "Dagostino, Tom" <tom_dagostino@mentorg.com>
To: "'Jason Leung'" <jleung@cid.alcatel.com>,
   Scott McMorrow
	 <scott@vasthorizons.com>
Cc: ibis-users@eda.org
Subject: RE: output impedance of a driver
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If you do both you will find there is usually a difference in pullup and
pulldown impedance.  Makes the design job more interesting.  What trade-off
are you going to make?

Tom Dagostino
IBIS and Tau Modeling Manager
SDD
Mentor Graphics Corp.
503-685-1613
tom_dagostino@mentor.com


-----Original Message-----
From: Jason Leung [mailto:jleung@cid.alcatel.com]
Sent: Monday, April 09, 2001 9:41 AM
To: Scott McMorrow
Cc: ibis-users@eda.org
Subject: Re: output impedance of a driver


Hi Scott McMorrow :
Thanks very much for your advice!
So if we wanted to find the output impedance for the driver ,we just have to

go to 1V row and then read off the corresponding current value eh?
Should I do that on the Pull up curve or the pull down curve?

thanks
Regards
Jason Leung


> Jason,
>
> If the ibis model has been extracted correctly, then the Ramp data
> will tell you what the saturated output impedance is.
>
> The IBIS V/I curves give you the impedance of an output buffer
> at any voltage.  I usually use 1 volts as a good place to measure
> impedance, since it is in the linear portion of the buffer curve.
> For the pullup and pulldown curve, go to the 1V row and read
> off the current.  Since R=V/I, the output channel resistance can
> be calculated.
>
> For example, if at 1 Volt the current is 35mA, then the
> output impedance is 28.57 ohms.
>
> regards,
>
> scott
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
>
> Jason Leung wrote:
>
> > Hi all:
> > Morning!
> > I am trying to obtain the output impedance of a driver, so that I can
> > match the driver with a transmission line and proper termination.
> > The way that I have tried is I used the IBIS model and then translate
> > the model into QUAD model, so that I can used the XNS to observe their
> > rising and falling waveform. Moreover I am trying to find its output
> > impedance in XNS.
> > My question is : Does anyone ever try finding the output impedance of a
> > driver? AND how did you achieve that?
> >
> > Thanks very much for your comment!
> > Jason leung
 
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To: "Muranyi, Arpad" <arpad.muranyi@intel.com>
CC: ibis-users@eda.org
Subject: Re: output impedance of a driver
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Hi Muranyi, Arpad:
Thanks for your advice!
one more question I would like to ask you: because I have been asked from
my colleague to use
XTK/XNS to find the output impedance of the driver, I know that in the
spawn -> VI viewer ,
we can import the corresponding .wvi curve to observe the waveform.
Among all those waveform, you can just pick on one waveform, and then do a

delta x and delta y function, then you will be able to find the impedance.

However, there are so many curves I have to choose(shunt and high, shunt
and low and many
many more) , do u know which one I have to choose for an accurate
approximation of the
output impedance of the driver .
The whole point here is , since I know I can find the output impedance of
the driver in the IBIS model
I also wanted to try and find the output impedance of the driver in the
XNS (QUAD) model ,so that
I am able to compare what we have before the simulation and after the
simulation( i.e. how the XTK/XNS
interpret the output impedance of that driver ).

thanks alot
Jason Leung


> Jason,
>
> The DC impedance can be found by dividing V/I on the IV curve of
> the buffer.  You will find that you get a different value at
> practically any of the voltages due to the non linear shape of
> the IV curve.  Plus, the process variation of a chip can give
> you a variation on the order of 2-3x.  So finding the impedance
> and matching the T-line to it is like shooting at a moving target.
>
> The reason I said DC impedance above is because the capacitive
> components of the buffer will also alter the impedance of the
> buffer a higher frequencies.
>
> Arpad Muranyi
> Intel Corporation
> ================================================================
>
> -----Original Message-----
> From: Jason Leung [mailto:jleung@cid.alcatel.com]
> Sent: Monday, April 09, 2001 6:14 AM
> To: ibis-users@eda.org
> Subject: Re: output impedance of a driver
>
> Hi all:
> Morning!
> I am trying to obtain the output impedance of a driver, so that I can
> match the driver with a transmission line and proper termination.
> The way that I have tried is I used the IBIS model and then translate
> the model into QUAD model, so that I can used the XNS to observe their
> rising and falling waveform. Moreover I am trying to find its output
> impedance in XNS.
> My question is : Does anyone ever try finding the output impedance of a
> driver? AND how did you achieve that?
>
> Thanks very much for your comment!
> Jason leung

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From owner-ibis Mon Apr  9 12:16:09 2001
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From: "Chris Rokusek" <crokusek@innoveda.com>
To: <ibis-users@eda.org>
Subject: RE: output impedance of a driver
Date: Mon, 9 Apr 2001 12:16:47 -0700
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Jason,

The curves shown in the VI viewer are identical (in most cases) to the
tables in the IBIS file.  You can use the output XTK file directly just as
you did with the IBIS file using the following mapping.

	IBIS          XTK
	------        -------
	Pullup        High
	Pulldown      Low
       POWER_Clamp   Shunt
       GND_Clamp     Shunt_Neg


However...

It is somewhat dangerous to provide only a single static impedance value as
others have pointed out due to the large variance over the typical operating
range, current state, process variation, and dynamic switching nature.  But
if you are trying to perform a first-order approximation then you must first
decide which voltage range(s) and which state(s) is of the most importance
to your application because Z will vary with both state and voltage range.

In some sense you should ask your colleague what he will use the Z value for
because that will determine which Z value you give him.

For instance if he wants to know what voltage will propagate down the TLine
during the initial rising edge then you might approximate the Z by
connecting two points on the HIGH VI curve in the middle of the operating
range.  This is poor approximation for at least three reasons:  1) The VI
curve may be non-linear, 2) The transition from off to on may be non-linear,
3) The opposing state (LOW) may still be driving simultaneously and turns
off non-linearly.

Another example is that your colleague may want to use the driver Z to
insure that reflections are absorbed.  In this case you would need to figure
out in which voltage range/state the reflections will occur.  If they occur
above/below the operating range of the device then the shunt curves (diodes)
will come into play...

Another methodology would be to create a linear driver (one with VI curves
of constant slope) and that is tweaked until its response matches the
response of the driver you are trying to approximate.

My advice is to instead of providing an impedance, give him waveforms that
cover all of the driving/loading cases (TLine/Receivers/Terminators/Process)
you are expecting to see.

Good luck,

Chris Rokusek
Innoveda



> -----Original Message-----
> From: Jason Leung [mailto:jleung@cid.alcatel.com]
> Sent: Monday, April 09, 2001 11:17 AM
> To: Muranyi, Arpad
> Cc: ibis-users@eda.org
> Subject: Re: output impedance of a driver
>
>
> Hi Muranyi, Arpad:
> Thanks for your advice!
> one more question I would like to ask you: because I have been asked from
> my colleague to use
> XTK/XNS to find the output impedance of the driver, I know that in the
> spawn -> VI viewer ,
> we can import the corresponding .wvi curve to observe the waveform.
> Among all those waveform, you can just pick on one waveform, and then do a
>
> delta x and delta y function, then you will be able to find the impedance.
>
> However, there are so many curves I have to choose(shunt and high, shunt
> and low and many
> many more) , do u know which one I have to choose for an accurate
> approximation of the
> output impedance of the driver .
> The whole point here is , since I know I can find the output impedance of
> the driver in the IBIS model
> I also wanted to try and find the output impedance of the driver in the
> XNS (QUAD) model ,so that
> I am able to compare what we have before the simulation and after the
> simulation( i.e. how the XTK/XNS
> interpret the output impedance of that driver ).
>
> thanks alot
> Jason Leung
>
>
> > Jason,
> >
> > The DC impedance can be found by dividing V/I on the IV curve of
> > the buffer.  You will find that you get a different value at
> > practically any of the voltages due to the non linear shape of
> > the IV curve.  Plus, the process variation of a chip can give
> > you a variation on the order of 2-3x.  So finding the impedance
> > and matching the T-line to it is like shooting at a moving target.
> >
> > The reason I said DC impedance above is because the capacitive
> > components of the buffer will also alter the impedance of the
> > buffer a higher frequencies.
> >
> > Arpad Muranyi
> > Intel Corporation
> > ================================================================
> >
> > -----Original Message-----
> > From: Jason Leung [mailto:jleung@cid.alcatel.com]
> > Sent: Monday, April 09, 2001 6:14 AM
> > To: ibis-users@eda.org
> > Subject: Re: output impedance of a driver
> >
> > Hi all:
> > Morning!
> > I am trying to obtain the output impedance of a driver, so that I can
> > match the driver with a transmission line and proper termination.
> > The way that I have tried is I used the IBIS model and then translate
> > the model into QUAD model, so that I can used the XNS to observe their
> > rising and falling waveform. Moreover I am trying to find its output
> > impedance in XNS.
> > My question is : Does anyone ever try finding the output impedance of a
> > driver? AND how did you achieve that?
> >
> > Thanks very much for your comment!
> > Jason leung
>

 
From owner-ibis Mon Apr  9 12:51:10 2001
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: ibis-users@eda.org
Subject: RE: output impedance of a driver
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You have to add up all of the curves which are ON and then
calculate the impedance. This may consist of a pulldown
plus GND_clamp, plus Vcc_clamp if it is driving low, or
pullup, and the same two clamps when it is driving high.

I hope this helps,

Arpad
========================================================

-----Original Message-----
From: Jason Leung [mailto:jleung@cid.alcatel.com]
Sent: Monday, April 09, 2001 11:17 AM
To: Muranyi, Arpad
Cc: ibis-users@eda.org
Subject: Re: output impedance of a driver


Hi Muranyi, Arpad:
Thanks for your advice!
one more question I would like to ask you: because I have been asked from
my colleague to use
XTK/XNS to find the output impedance of the driver, I know that in the
spawn -> VI viewer ,
we can import the corresponding .wvi curve to observe the waveform.
Among all those waveform, you can just pick on one waveform, and then do a

delta x and delta y function, then you will be able to find the impedance.

However, there are so many curves I have to choose(shunt and high, shunt
and low and many
many more) , do u know which one I have to choose for an accurate
approximation of the
output impedance of the driver .
The whole point here is , since I know I can find the output impedance of
the driver in the IBIS model
I also wanted to try and find the output impedance of the driver in the
XNS (QUAD) model ,so that
I am able to compare what we have before the simulation and after the
simulation( i.e. how the XTK/XNS
interpret the output impedance of that driver ).

thanks alot
Jason Leung


> Jason,
>
> The DC impedance can be found by dividing V/I on the IV curve of
> the buffer.  You will find that you get a different value at
> practically any of the voltages due to the non linear shape of
> the IV curve.  Plus, the process variation of a chip can give
> you a variation on the order of 2-3x.  So finding the impedance
> and matching the T-line to it is like shooting at a moving target.
>
> The reason I said DC impedance above is because the capacitive
> components of the buffer will also alter the impedance of the
> buffer a higher frequencies.
>
> Arpad Muranyi
> Intel Corporation
> ================================================================
>
> -----Original Message-----
> From: Jason Leung [mailto:jleung@cid.alcatel.com]
> Sent: Monday, April 09, 2001 6:14 AM
> To: ibis-users@eda.org
> Subject: Re: output impedance of a driver
>
> Hi all:
> Morning!
> I am trying to obtain the output impedance of a driver, so that I can
> match the driver with a transmission line and proper termination.
> The way that I have tried is I used the IBIS model and then translate
> the model into QUAD model, so that I can used the XNS to observe their
> rising and falling waveform. Moreover I am trying to find its output
> impedance in XNS.
> My question is : Does anyone ever try finding the output impedance of a
> driver? AND how did you achieve that?
>
> Thanks very much for your comment!
> Jason leung

 
From owner-ibis Mon Apr  9 13:08:12 2001
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Hi Scott McMorrow :
Thanks very much for your advice!
So if we wanted to find the output impedance for the driver ,we just have to

go to 1V row and then read off the corresponding current value eh?
Should I do that on the Pull up curve or the pull down curve?

thanks
Regards
Jason Leung


> Jason,
>
> If the ibis model has been extracted correctly, then the Ramp data
> will tell you what the saturated output impedance is.
>
> The IBIS V/I curves give you the impedance of an output buffer
> at any voltage.  I usually use 1 volts as a good place to measure
> impedance, since it is in the linear portion of the buffer curve.
> For the pullup and pulldown curve, go to the 1V row and read
> off the current.  Since R=V/I, the output channel resistance can
> be calculated.
>
> For example, if at 1 Volt the current is 35mA, then the
> output impedance is 28.57 ohms.
>
> regards,
>
> scott
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
>
> Jason Leung wrote:
>
> > Hi all:
> > Morning!
> > I am trying to obtain the output impedance of a driver, so that I can
> > match the driver with a transmission line and proper termination.
> > The way that I have tried is I used the IBIS model and then translate
> > the model into QUAD model, so that I can used the XNS to observe their
> > rising and falling waveform. Moreover I am trying to find its output
> > impedance in XNS.
> > My question is : Does anyone ever try finding the output impedance of a
> > driver? AND how did you achieve that?
> >
> > Thanks very much for your comment!
> > Jason leung

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Jason,

If the ibis model has been extracted correctly, then the Ramp data
will tell you what the saturated output impedance is.

The IBIS V/I curves give you the impedance of an output buffer
at any voltage.  I usually use 1 volts as a good place to measure
impedance, since it is in the linear portion of the buffer curve.
For the pullup and pulldown curve, go to the 1V row and read
off the current.  Since R=V/I, the output channel resistance can
be calculated.

For example, if at 1 Volt the current is 35mA, then the
output impedance is 28.57 ohms.

regards,

scott


--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com



Jason Leung wrote:

> Hi all:
> Morning!
> I am trying to obtain the output impedance of a driver, so that I can
> match the driver with a transmission line and proper termination.
> The way that I have tried is I used the IBIS model and then translate
> the model into QUAD model, so that I can used the XNS to observe their
> rising and falling waveform. Moreover I am trying to find its output
> impedance in XNS.
> My question is : Does anyone ever try finding the output impedance of a
> driver? AND how did you achieve that?
>
> Thanks very much for your comment!
> Jason leung



 
From owner-ibis Mon Apr  9 13:14:27 2001
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From: "Dagostino, Tom" <tom_dagostino@mentorg.com>
To: "'Jason Leung'" <jleung@cid.alcatel.com>,
   Scott McMorrow
	 <scott@vasthorizons.com>
Cc: ibis-users@eda.org
Subject: RE: output impedance of a driver
Date: Mon, 9 Apr 2001 09:48:04 -0700 
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If you do both you will find there is usually a difference in pullup and
pulldown impedance.  Makes the design job more interesting.  What trade-off
are you going to make?

Tom Dagostino
IBIS and Tau Modeling Manager
SDD
Mentor Graphics Corp.
503-685-1613
tom_dagostino@mentor.com


-----Original Message-----
From: Jason Leung [mailto:jleung@cid.alcatel.com]
Sent: Monday, April 09, 2001 9:41 AM
To: Scott McMorrow
Cc: ibis-users@eda.org
Subject: Re: output impedance of a driver


Hi Scott McMorrow :
Thanks very much for your advice!
So if we wanted to find the output impedance for the driver ,we just have to

go to 1V row and then read off the corresponding current value eh?
Should I do that on the Pull up curve or the pull down curve?

thanks
Regards
Jason Leung


> Jason,
>
> If the ibis model has been extracted correctly, then the Ramp data
> will tell you what the saturated output impedance is.
>
> The IBIS V/I curves give you the impedance of an output buffer
> at any voltage.  I usually use 1 volts as a good place to measure
> impedance, since it is in the linear portion of the buffer curve.
> For the pullup and pulldown curve, go to the 1V row and read
> off the current.  Since R=V/I, the output channel resistance can
> be calculated.
>
> For example, if at 1 Volt the current is 35mA, then the
> output impedance is 28.57 ohms.
>
> regards,
>
> scott
>
> --
> Scott McMorrow
> Principal Engineer
> SiQual, Signal Quality Engineering
> 18735 SW Boones Ferry Road
> Tualatin, OR  97062-3090
> (503) 885-1231
> http://www.siqual.com
>
> Jason Leung wrote:
>
> > Hi all:
> > Morning!
> > I am trying to obtain the output impedance of a driver, so that I can
> > match the driver with a transmission line and proper termination.
> > The way that I have tried is I used the IBIS model and then translate
> > the model into QUAD model, so that I can used the XNS to observe their
> > rising and falling waveform. Moreover I am trying to find its output
> > impedance in XNS.
> > My question is : Does anyone ever try finding the output impedance of a
> > driver? AND how did you achieve that?
> >
> > Thanks very much for your comment!
> > Jason leung

 
From owner-ibis Mon Apr  9 14:11:44 2001
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From: "Todd Westerhoff" <twester@hhnetwk.com>
To: <ibis-users@eda.org>
Subject: RE: output impedance of a driver
Date: Mon, 9 Apr 2001 17:11:14 -0400
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In-Reply-To: <NCBBIPNACIFLPPLOIJECGEKNCOAA.crokusek@innoveda.com>

Jason,

I prefer to measure (delta V)/(delta I) from the linear portion of the
transistor curves.  I just eyeball the curves and pick points from the
largest portion of the curve I can perceive as "linear" (squinting is
optional). There are potential pitfalls as Chris points out, but for common
application the technique seems to work just fine.  It's just a starting
point anyway, as you should use simulation to test your assumptions.

As others have pointed out, be sure the check the slopes for both the pullup
and pulldown devices, as you need to balance the needs of both edges.
Should you find yourself dealing with one transistor significantly stronger
than the other, parallel termination to either power or ground may be in
order, as was discussed last week.

Todd.



-----Original Message-----
From: Chris Rokusek [mailto:crokusek@innoveda.com]
Sent: Monday, April 09, 2001 3:17 PM
To: ibis-users@eda.org
Subject: RE: output impedance of a driver


Jason,

The curves shown in the VI viewer are identical (in most cases) to the
tables in the IBIS file.  You can use the output XTK file directly just as
you did with the IBIS file using the following mapping.

	IBIS          XTK
	------        -------
	Pullup        High
	Pulldown      Low
       POWER_Clamp   Shunt
       GND_Clamp     Shunt_Neg


However...

It is somewhat dangerous to provide only a single static impedance value as
others have pointed out due to the large variance over the typical operating
range, current state, process variation, and dynamic switching nature.  But
if you are trying to perform a first-order approximation then you must first
decide which voltage range(s) and which state(s) is of the most importance
to your application because Z will vary with both state and voltage range.

In some sense you should ask your colleague what he will use the Z value for
because that will determine which Z value you give him.

For instance if he wants to know what voltage will propagate down the TLine
during the initial rising edge then you might approximate the Z by
connecting two points on the HIGH VI curve in the middle of the operating
range.  This is poor approximation for at least three reasons:  1) The VI
curve may be non-linear, 2) The transition from off to on may be non-linear,
3) The opposing state (LOW) may still be driving simultaneously and turns
off non-linearly.

Another example is that your colleague may want to use the driver Z to
insure that reflections are absorbed.  In this case you would need to figure
out in which voltage range/state the reflections will occur.  If they occur
above/below the operating range of the device then the shunt curves (diodes)
will come into play...

Another methodology would be to create a linear driver (one with VI curves
of constant slope) and that is tweaked until its response matches the
response of the driver you are trying to approximate.

My advice is to instead of providing an impedance, give him waveforms that
cover all of the driving/loading cases (TLine/Receivers/Terminators/Process)
you are expecting to see.

Good luck,

Chris Rokusek
Innoveda



> -----Original Message-----
> From: Jason Leung [mailto:jleung@cid.alcatel.com]
> Sent: Monday, April 09, 2001 11:17 AM
> To: Muranyi, Arpad
> Cc: ibis-users@eda.org
> Subject: Re: output impedance of a driver
>
>
> Hi Muranyi, Arpad:
> Thanks for your advice!
> one more question I would like to ask you: because I have been asked from
> my colleague to use
> XTK/XNS to find the output impedance of the driver, I know that in the
> spawn -> VI viewer ,
> we can import the corresponding .wvi curve to observe the waveform.
> Among all those waveform, you can just pick on one waveform, and then do a
>
> delta x and delta y function, then you will be able to find the impedance.
>
> However, there are so many curves I have to choose(shunt and high, shunt
> and low and many
> many more) , do u know which one I have to choose for an accurate
> approximation of the
> output impedance of the driver .
> The whole point here is , since I know I can find the output impedance of
> the driver in the IBIS model
> I also wanted to try and find the output impedance of the driver in the
> XNS (QUAD) model ,so that
> I am able to compare what we have before the simulation and after the
> simulation( i.e. how the XTK/XNS
> interpret the output impedance of that driver ).
>
> thanks alot
> Jason Leung
>
>
> > Jason,
> >
> > The DC impedance can be found by dividing V/I on the IV curve of
> > the buffer.  You will find that you get a different value at
> > practically any of the voltages due to the non linear shape of
> > the IV curve.  Plus, the process variation of a chip can give
> > you a variation on the order of 2-3x.  So finding the impedance
> > and matching the T-line to it is like shooting at a moving target.
> >
> > The reason I said DC impedance above is because the capacitive
> > components of the buffer will also alter the impedance of the
> > buffer a higher frequencies.
> >
> > Arpad Muranyi
> > Intel Corporation
> > ================================================================
> >
> > -----Original Message-----
> > From: Jason Leung [mailto:jleung@cid.alcatel.com]
> > Sent: Monday, April 09, 2001 6:14 AM
> > To: ibis-users@eda.org
> > Subject: Re: output impedance of a driver
> >
> > Hi all:
> > Morning!
> > I am trying to obtain the output impedance of a driver, so that I can
> > match the driver with a transmission line and proper termination.
> > The way that I have tried is I used the IBIS model and then translate
> > the model into QUAD model, so that I can used the XNS to observe their
> > rising and falling waveform. Moreover I am trying to find its output
> > impedance in XNS.
> > My question is : Does anyone ever try finding the output impedance of a
> > driver? AND how did you achieve that?
> >
> > Thanks very much for your comment!
> > Jason leung
>

 
From owner-ibis Tue Apr 10 06:53:09 2001
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This might be a simple question, but I couldn't find it in any of the
documentation...

Can IBIS model an input with a build in termination?  

I created a model with the termination in the spice simulation (for
s2ibis).  The ibischk3 didn't report any problems with it.  But when I
simulated it in Hspice, first Hspice complained that the current wasn't
0 at gnd (for gnd clamp) and 0 at vdd (for power clamp).  The resultant
waveforms were the correct shape but offset from the proper voltage (I
ran the transistor version of the input in the same circuit for
comparison).

I then removed the termination and recreated the ibis model.  I
resimulated with an external termination in Hspice (but connected
directly to the input node) and everything matched fine.


-- 
Chris Burton Cad Support
603-546-0617 chris.burton@xanoptix.com
 
From owner-ibis Tue Apr 10 08:00:01 2001
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From: Aubrey_Sparkman@Dell.com
To: chris.burton@xanoptix.com, ibis-users@eda.org
Subject: RE: built in termination
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Chris,
This sounds like an HSpice problem.  Many of the models I use have pull-up
terminators modeled in the power clamp.  I see no reason why one couldn't
model a termination to ground in the ground clamp.

Aubrey Sparkman
Signal Integrity
Aubrey_Sparkman@Dell.com
(512) 723-3592


> -----Original Message-----
> From: Chris Burton [mailto:chris.burton@xanoptix.com]
> Sent: Tuesday, April 10, 2001 8:53 AM
> To: ibis-users@eda.org
> Subject: built in termination
> 
> 
> 
> This might be a simple question, but I couldn't find it in any of the
> documentation...
> 
> Can IBIS model an input with a build in termination?  
> 
> I created a model with the termination in the spice simulation (for
> s2ibis).  The ibischk3 didn't report any problems with it.  But when I
> simulated it in Hspice, first Hspice complained that the 
> current wasn't
> 0 at gnd (for gnd clamp) and 0 at vdd (for power clamp).  The 
> resultant
> waveforms were the correct shape but offset from the proper voltage (I
> ran the transistor version of the input in the same circuit for
> comparison).
> 
> I then removed the termination and recreated the ibis model.  I
> resimulated with an external termination in Hspice (but connected
> directly to the input node) and everything matched fine.
> 
> 
> -- 
> Chris Burton Cad Support
> 603-546-0617 chris.burton@xanoptix.com
> 


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From owner-ibis Tue Apr 10 09:54:13 2001
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: ibis-users@eda.org
Subject: RE: built in termination
Date: Tue, 10 Apr 2001 09:53:32 -0700
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Chris,

We do this all the time without any problems in the
waveforms (with the B-element).  From your description,
it sounds like your clamp waveforms are not correct.
Even if you have on die terminations, the clamp curves
should go through the origin.

For example, if you have a termination that is connected
to GND, your GND_clamp IV curve will look similar to
a pulldown IV curve.  In this case the Power_clamp IV
curve should look like a normal diode curve having about
zero current between GND and Vcc.

If you have a terminator to Vcc, the mirror of the previous
description should be true.  Notice that the IV curve have
zero current at the origin in both cases.  If your curves
don't look like this, than your buffer has either some
fancy features (other than a normal terminator) or the
IBIS model was not generated correctly.  Keep in mind that
it is very easy to double count for the terminator in these
IV curves, and some numerical massaging of the data may be
necessary to get it right.

I do have a few foils on this issue in my IBIS class presentation
which you can get from

http://www.eigroup.org/ibis/ibis.htm

under Articles/Training/IBIS_class_JEDEC.ZIP, in the PDF file,
pages 78-81.

Arpad Muranyi
Intel Corporation
==========================================================

-----Original Message-----
From: Chris Burton [mailto:chris.burton@xanoptix.com]
Sent: Tuesday, April 10, 2001 6:53 AM
To: ibis-users@eda.org
Subject: built in termination



This might be a simple question, but I couldn't find it in any of the
documentation...

Can IBIS model an input with a build in termination?  

I created a model with the termination in the spice simulation (for
s2ibis).  The ibischk3 didn't report any problems with it.  But when I
simulated it in Hspice, first Hspice complained that the current wasn't
0 at gnd (for gnd clamp) and 0 at vdd (for power clamp).  The resultant
waveforms were the correct shape but offset from the proper voltage (I
ran the transistor version of the input in the same circuit for
comparison).

I then removed the termination and recreated the ibis model.  I
resimulated with an external termination in Hspice (but connected
directly to the input node) and everything matched fine.


-- 
Chris Burton Cad Support
603-546-0617 chris.burton@xanoptix.com

 
From owner-ibis Tue Apr 10 11:14:56 2001
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Subject: Re: output impedance of a driver
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Hi Michael:
Thanks for showing me the way to find the output impedance!! It really helps me.

Now, I would like to show you some interesting results:
Right now I am working on LVT162244 from TI and I am trying to measure the
output impedance of the driver .I have used the method you show me to do (i.e.
-motive and I am able to get the output impedance for the high state which is
36.5 ohms and output impedance for the low
state which is 29.81 ohms) .
The schematic  that I have used for testing is :


[Image]

where I have got a driver ->tline of 0.01 inch 60 ohms , series resistance
->tline of 10 inch 60 ohms-> and receiver.

Since I wanted to compare the real value for the  output impedance of the driver
, I have tried different values for the series termination.
The calculations are like these: I assumed  the output impedance of the driver
is in high state , so RH=36.5 , in order to match that with the tline,
I have to use 23.5 ohms for the series termination, and I do the same thing by
assuming the output impedance of the driver is in low state, then
the series termination is 30.19 ohms . The third case is (RH+RL)/2 =33.2 so the
series termination 60-33.2 =26.8 ohms.the last case is when the series
termination is 60 ohms

and you can see from the output waveform :

[Image]


here we see that the red curve is with series termination of 23.5 ohms , and the
one below the red curve is when series termination of 26.8 ohms
and the third one is when  series termination of 30.15 ohms and finally series
termination of 60 ohms.
This is interesting to us because at the red curve where series termination is
23.5 ohms the rising edge is ok , but the falling edge is not ok .
When the series termination is 26.845 ohms , the  rising edge is not ok , but
the falling edge is  ok. Also when the series termination is 30.19 ohms , the
rising edge is not ok , but the falling edge is  ok.Finally for the series
termination is 60 ohms , the  rising edge is not ok , but the falling edge is
not ok.
My question is how do we determine the output impedance for the driver in this
case, whether we should use RH , RL or (RH+RL)/2 . ???
Please feel free to comment.
Thanks
Jason Leung




Michael Mayer wrote:

> You can use ibis2xtk. One of the options generates a BLAST (formerly MOTIVE)
> model. This is a simple linear model that includes the high and low
> impedance. Try ibis2xtk -motive
>
> It will generate a .src file. At the bottom of the file will be a DEFDRIVER
> statement for each buffer. RL and RH are the low and high impedances.
>
> =======================================================================
> Mike Mayer                                          mmayer@innoveda.com
> Applications Engineer                             Office: (608)523-1960
> Innoveda, Inc                                     Mobile: (608)575-2732
>
> -----Original Message-----
> From: Jason Leung [mailto:jleung@cid.alcatel.com]
> Sent: Monday, April 09, 2001 8:14 AM
> To: ibis-users@eda.org
> Subject: Re: output impedance of a driver
>
> Hi all:
> Morning!
> I am trying to obtain the output impedance of a driver, so that I can
> match the driver with a transmission line and proper termination.
> The way that I have tried is I used the IBIS model and then translate
> the model into QUAD model, so that I can used the XNS to observe their
> rising and falling waveform. Moreover I am trying to find its output
> impedance in XNS.
> My question is : Does anyone ever try finding the output impedance of a
> driver? AND how did you achieve that?
>
> Thanks very much for your comment!
> Jason leung

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Hi Michael:
<br>Thanks for showing me the way to find the output impedance!! It really
helps me.
<br>Now, I would like to show you some interesting results:
<br>Right now I am working on LVT162244 from TI and I am trying to measure
the output impedance of the driver .I have used the method you show me
to do (i.e. -motive and I am able to get the output impedance for the high
state which is 36.5 ohms and output impedance for the low
<br>state which is 29.81 ohms) .
<br>The schematic&nbsp; that I have used for testing is :
<br>&nbsp;
<p><img SRC="cid:part1.3AD34C65.375D92E@cid.alcatel.com" height=123 width=742>
<p>where I have got a driver ->tline of 0.01 inch 60 ohms , series resistance
->tline of 10 inch 60 ohms-> and receiver.
<p>Since I wanted to compare the real value for the&nbsp; output impedance
of the driver , I have tried different values for the series termination.
<br>The calculations are like these: I assumed&nbsp; the output impedance
of the driver is in high state , so RH=36.5 , in order to match that with
the tline,
<br>I have to use 23.5 ohms for the series termination, and I do the same
thing by assuming the output impedance of the driver is in low state, then
<br>the series termination is 30.19 ohms . The third case is (RH+RL)/2
=33.2 so the series termination 60-33.2 =26.8 ohms.the last case is when
the series termination is 60 ohms
<p>and you can see from the output waveform :
<p><img SRC="cid:part2.3AD34C65.375D92E@cid.alcatel.com" height=697 width=847>
<br>&nbsp;
<p>here we see that the red curve is with series termination of 23.5 ohms
, and the one below the red curve is when series termination of 26.8 ohms
<br>and the third one is when&nbsp; series termination of 30.15 ohms and
finally series termination of 60 ohms.
<br>This is interesting to us because at the red curve where series termination
is&nbsp; 23.5 ohms the rising edge is ok , but the falling edge is not
ok .
<br>When the series termination is 26.845 ohms , the&nbsp; rising edge
is not ok , but the falling edge is&nbsp; ok. Also when the series termination
is 30.19 ohms , the&nbsp; rising edge is not ok , but the falling edge
is&nbsp; ok.Finally for the series termination is 60 ohms , the&nbsp; rising
edge is not ok , but the falling edge is&nbsp; not ok.
<br>My question is how do we determine the output impedance for the driver
in this case, whether we should use RH , RL or (RH+RL)/2 . ???
<br>Please feel free to comment.
<br>Thanks
<br>Jason Leung<br>
<BR>
<br>&nbsp;
<br>&nbsp;
<p>Michael Mayer wrote:
<blockquote TYPE=CITE>You can use ibis2xtk. One of the options generates
a BLAST (formerly MOTIVE)
<br>model. This is a simple linear model that includes the high and low
<br>impedance. Try ibis2xtk -motive
<p>It will generate a .src file. At the bottom of the file will be a DEFDRIVER
<br>statement for each buffer. RL and RH are the low and high impedances.
<p>=======================================================================
<br>Mike Mayer&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
mmayer@innoveda.com
<br>Applications Engineer&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Office: (608)523-1960
<br>Innoveda, Inc&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Mobile: (608)575-2732
<p>-----Original Message-----
<br>From: Jason Leung [<a href="mailto:jleung@cid.alcatel.com">mailto:jleung@cid.alcatel.com</a>]
<br>Sent: Monday, April 09, 2001 8:14 AM
<br>To: ibis-users@eda.org
<br>Subject: Re: output impedance of a driver
<p>Hi all:
<br>Morning!
<br>I am trying to obtain the output impedance of a driver, so that I can
<br>match the driver with a transmission line and proper termination.
<br>The way that I have tried is I used the IBIS model and then translate
<br>the model into QUAD model, so that I can used the XNS to observe their
<br>rising and falling waveform. Moreover I am trying to find its output
<br>impedance in XNS.
<br>My question is : Does anyone ever try finding the output impedance
of a
<br>driver? AND how did you achieve that?
<p>Thanks very much for your comment!
<br>Jason leung</blockquote>
</html>

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From owner-ibis Wed Apr 11 07:27:30 2001
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Subject: A question for IBIS data
To: "'ibis-users@eda.org'" <ibis-users@eda.org>
From: Adam.Tambone@fairchildsemi.com
Date: Wed, 11 Apr 2001 10:24:04 -0400
Message-ID: <OF43E97ADA.A9483940-ON85256A2B.004F134A@fairchildsemi.com>
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Moo-yeul,

The voltages in the V-t waveforms represent the output voltages of the DUT.
The node these voltages are taken from is the output node.  The question is
what were the loading conditions in which the data was taken and did it
include package parasitics.  The sub-parameters:

L_fixture, R_fixture, V_fixture, C_fixture

specify the loading conditions in which the V-t data was taken.  The
sub-parameters:

L_dut, R_dut, C_dut

specify the package parasitics that are included in the V-t data taken.

If the above subparameters are not included in the IBIS datasheet then the
V-t data was taken at a node that does not include packaging or a load.
The effect of c_comp is included in the V-t data.

See pgs42-44 of the 3.2 spec.

Adam Tambone



 
From owner-ibis Thu Apr 12 08:15:08 2001
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Subject: Ibisx-conference call
Date: Thu, 12 Apr 2001 09:10:24 -0600
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Top levei june fInal 1year tools 1year after that

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From owner-ibis Fri Apr 13 07:43:49 2001
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From: "Kris Young" <kyoung@phaseiv.com>
To: <ibis-users@eda.org>
Subject: arbitrary length in ebd files?
Date: Fri, 13 Apr 2001 09:42:46 -0500
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Hello:

I have a question about path descriptions in electronic board description
(ebd) files (IBIS 3.2).  I'm wondering how to get an accurate simulation of
signal reflections when the path length is given in terms of an arbitrary
length.  It seems like running an accurate SI simulation will require an
estimate as to what factor to scale the path lengths by to get them to match
the device specified by the ebd.  Why isn't there a way to specify a scale
factor in the ebd file?  Am I missing something?

Thanks in advance for your assistance.

Regards,

Kris Young
Phase IV Systems, Inc.
Huntsville, AL

 
From owner-ibis Fri Apr 13 08:42:51 2001
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From: "Dunbar, Tony" <tony_dunbar@mentorg.com>
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Subject: RE: arbitrary length in ebd files?
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Hi Kris,

It's not that intuitive, so don't feel bad for missing this.
The "scaling factor" is in the L and C values for the path.
If you look at the following (fairly well documented) example,
you can see/derive from the scale of the L and C values that
sqrt(LC) gives an answer of delay per unit length in s/m
(i.e. seconds per meter). But I also need the scale of the
L and C values to be correct to obtain the correct Zo=sqrt(L/C).
So I then use a Len value to specify the length of the segment.

In this example, one of segment my lengths needs to be 520mil
but I'm working in meters.

Hope this helps!

Regards,
Tony

[Path Description] XYZ
Pin B18
| 1. Path 1
Len = 0 L = 168.00e-12 C = 0.00 R = 0.006 /
| 2. Via
Len = 0 L = 570.00e-12 C = 0.00 R = 0.0021 /
| 3. Seg. #2 Use slow = 520mil, HighZ 50.3ohm.
Len = 0.013205 L = 3.591440e-07 C = 1.419672e-10 R = 6.931417e01 /
| 4. Seg. #1 Use slow = 80mil, HighZ 42.46ohm.
Len = 0.002032 L = 3.072277e-07 C = 1.704113e-10 R = 5.862795e01 /
| 5. Die bump
Len = 0 L = 20.00e-12 C = 0.0 R = 0.002 /
Node U1.B18

-----Original Message-----
From: Kris Young [mailto:kyoung@phaseiv.com]
Sent: Friday, April 13, 2001 9:43 AM
To: ibis-users@eda.org
Subject: arbitrary length in ebd files?


Hello:

I have a question about path descriptions in electronic board description
(ebd) files (IBIS 3.2).  I'm wondering how to get an accurate simulation of
signal reflections when the path length is given in terms of an arbitrary
length.  It seems like running an accurate SI simulation will require an
estimate as to what factor to scale the path lengths by to get them to match
the device specified by the ebd.  Why isn't there a way to specify a scale
factor in the ebd file?  Am I missing something?

Thanks in advance for your assistance.

Regards,

Kris Young
Phase IV Systems, Inc.
Huntsville, AL
 
From owner-ibis Fri Apr 13 08:56:57 2001
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From: "Reid, Chris" <chris_reid@mentorg.com>
To: "Dunbar, Tony" <tony_dunbar@mentorg.com>, ibis-users@eda.org
Subject: RE: arbitrary length in ebd files?
Date: Fri, 13 Apr 2001 08:54:44 -0700
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Hello,

There is no specified units for the length of the
transmission lines in EBD because it is not needed.
Given any particular specification of the transmission
line properties it does not matter wether you take the
units to be inches, feet, meeters, or miles.  The
answer will always be the same.

The reason for this is that L and C are given per
unit length.  L is Henrys per unit length.  C is
Farads per unit length.  So, the impedance of the
line is sqrt(L/C) and the length unit cancels in
the ratio.  The delay per unit length is sqrt(LC)
so the total delay is sqrt(LC)*Len, where again the
length units cancel.

Thus the simulator does not need to know the scale
to get a unique answer.  The length unit just needs
to be consistent.

Chris

-----Original Message-----
From: Dunbar, Tony [mailto:tony_dunbar]
Sent: Friday, April 13, 2001 8:42 AM
To: ibis-users@eda.org
Subject: RE: arbitrary length in ebd files?


Hi Kris,

It's not that intuitive, so don't feel bad for missing this.
The "scaling factor" is in the L and C values for the path.
If you look at the following (fairly well documented) example,
you can see/derive from the scale of the L and C values that
sqrt(LC) gives an answer of delay per unit length in s/m
(i.e. seconds per meter). But I also need the scale of the
L and C values to be correct to obtain the correct Zo=sqrt(L/C).
So I then use a Len value to specify the length of the segment.

In this example, one of segment my lengths needs to be 520mil
but I'm working in meters.

Hope this helps!

Regards,
Tony

[Path Description] XYZ
Pin B18
| 1. Path 1
Len = 0 L = 168.00e-12 C = 0.00 R = 0.006 /
| 2. Via
Len = 0 L = 570.00e-12 C = 0.00 R = 0.0021 /
| 3. Seg. #2 Use slow = 520mil, HighZ 50.3ohm.
Len = 0.013205 L = 3.591440e-07 C = 1.419672e-10 R = 6.931417e01 /
| 4. Seg. #1 Use slow = 80mil, HighZ 42.46ohm.
Len = 0.002032 L = 3.072277e-07 C = 1.704113e-10 R = 5.862795e01 /
| 5. Die bump
Len = 0 L = 20.00e-12 C = 0.0 R = 0.002 /
Node U1.B18

-----Original Message-----
From: Kris Young [mailto:kyoung@phaseiv.com]
Sent: Friday, April 13, 2001 9:43 AM
To: ibis-users@eda.org
Subject: arbitrary length in ebd files?


Hello:

I have a question about path descriptions in electronic board description
(ebd) files (IBIS 3.2).  I'm wondering how to get an accurate simulation of
signal reflections when the path length is given in terms of an arbitrary
length.  It seems like running an accurate SI simulation will require an
estimate as to what factor to scale the path lengths by to get them to match
the device specified by the ebd.  Why isn't there a way to specify a scale
factor in the ebd file?  Am I missing something?

Thanks in advance for your assistance.

Regards,

Kris Young
Phase IV Systems, Inc.
Huntsville, AL
 
From owner-ibis Fri Apr 13 11:22:10 2001
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From owner-ibis Fri Apr 13 17:46:08 2001
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Sender: "Prasad Rau" <Prasad.Rau@xilinx.com>
Message-ID: <3AD7A084.250A8EAC@xilinx.com>
Date: Fri, 13 Apr 2001 17:57:40 -0700
From: Prasad Rau <prasad.rau@xilinx.com>
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Subject: On chip Active termination
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Hi,

On our current design we support several standards using controlled impedance. By using this scheme
we can mimic driver or receiver end terminations for standards like SSTL,HSTLs
and GTL. The onchip termination is done using active devices as opposed to passive
elements.  For example in the SSTL2 Class I the parallel termination is at the receiver end.
Using the controlled impedance scheme we can eliminate the series & parallel termination resistor son the board.
I have created seperate IBIS models for the output and the input. When I use the output model
and drive the input model through a Tline using the HyperLynx tool I am not seeing the right
levels at the receiver end. It is telling me that the termination at the receiver is missing. I know
that the input IBIS model makes sense because if I look at the GND clamp curve I observe ~ 0mA
current at 1.3V ( which is the valid voltage level with the output tristated). The same driver model
if it drives a non controlled impedance receiver with the appropriate board termination at the receiver
gives me the correct levels at the receiver.

 Is HyperLynx unable to recognize onchip termination input IBIS models ? Has aynone
worked with controlled impedance and have suggestions in modelling them in IBIS.


Appreciate your help in this regard.


Thanks in advance,


Regards,

Prasad Rau
Xilinx



 
From owner-ibis Sat Apr 14 11:01:09 2001
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Subject: Re: On chip Active termination
Date: Sat, 14 Apr 2001 11:00:43 -0700
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Dear Prasad Rau,

Might I suggest that you ask technical support for the HyperLynx products at
support@hyperlynx.com or (425) 869-2320?

Best regards,
Matthew Flora



----- Original Message -----
From: "Prasad Rau" <prasad.rau@xilinx.com>
To: <ibis-users@eda.org>
Sent: Friday, April 13, 2001 5:57 PM
Subject: On chip Active termination


> Hi,
>
> On our current design we support several standards using controlled
impedance. By using this scheme
> we can mimic driver or receiver end terminations for standards like
SSTL,HSTLs
> and GTL. The onchip termination is done using active devices as opposed to
passive
> elements.  For example in the SSTL2 Class I the parallel termination is at
the receiver end.
> Using the controlled impedance scheme we can eliminate the series & parallel
termination resistor son the board.
> I have created seperate IBIS models for the output and the input. When I use
the output model
> and drive the input model through a Tline using the HyperLynx tool I am not
seeing the right
> levels at the receiver end. It is telling me that the termination at the
receiver is missing. I know
> that the input IBIS model makes sense because if I look at the GND clamp
curve I observe ~ 0mA
> current at 1.3V ( which is the valid voltage level with the output
tristated). The same driver model
> if it drives a non controlled impedance receiver with the appropriate board
termination at the receiver
> gives me the correct levels at the receiver.
>
>  Is HyperLynx unable to recognize onchip termination input IBIS models ? Has
aynone
> worked with controlled impedance and have suggestions in modelling them in
IBIS.
>
>
> Appreciate your help in this regard.
>
>
> Thanks in advance,
>
>
> Regards,
>
> Prasad Rau
> Xilinx
>
>
>

 
From owner-ibis Sun Apr 15 20:08:43 2001
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From: "=?euc-kr?b?sK3Bvsij?="<jhkang@sr.hynix.com>
Reply-To: 
To: ibis-users@eda.org
Cc: 
Subject: About EBD Generation
Date: Mon, 16 Apr 2001 12:07:40 +0900
Message-ID: <OF5D8802B2.102D7E55-ON49256A30.00112E93@LocalDomain>
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 3.2//EN">
<html>
<head>
<title>Untitled</title>
<meta name=3D"GENERATOR" content=3D"Namo WebEditor ActiveX Control v2.1">
</head>
<body bgcolor=3D"white" text=3D"black" link=3D"blue" vlink=3D"purple" alink=
=3D"red">

<p align=3D"left"><font size=3D"2">Hi, All</font></p>
<p style=3D"margin-top:0; margin-bottom:0;">&nbsp;</p>
<p align=3D"left"><font size=3D"2">I'm using Cadece SPECCTRAQuest as my sys=
tem level simulator.</font></p>
<p align=3D"left"><font size=3D"2">In case of SPECCTRAQuest, it does not su=
pport EBD model generation.</font></p>
<p align=3D"left"><font size=3D"2">Is there any software which produces EBD=
 from gerber ?</font></p>
<p align=3D"left"><font size=3D"2">Is there any freeware for it ?</font></p>
<p align=3D"left"><font size=3D"2">If any s/w is not available for me, how =
can I generate EBD with ease ?</font></p>
<p align=3D"left">&nbsp;</p>
<p style=3D"margin-top:0; margin-bottom:0;"><font size=3D"2">Thanks in adva=
nce,</font></p>
<p align=3D"left"><font size=3D"2">J.H. Kang</font></p>
</body>
</html>=
 
From owner-ibis Mon Apr 16 00:28:01 2001
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From: "=?euc-kr?b?sK3Bvsij?="<jhkang@sr.hynix.com>
Reply-To: 
To: ibis-users@eda.org
Cc: 
Subject: About EBD Generation
Date: Mon, 16 Apr 2001 16:26:55 +0900
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<meta name=3D"GENERATOR" content=3D"Namo WebEditor ActiveX Control v2.1">
</head>
<body bgcolor=3D"white" text=3D"black" link=3D"blue" vlink=3D"purple" alink=
=3D"red">

<p align=3D"left"><font size=3D"2">Hi, All</font></p>
<p align=3D"left"><font size=3D"2">I'm using Cadece SPECCTRAQuest as my sys=
tem level simulator.</font></p>
<p align=3D"left"><font size=3D"2">In case of SPECCTRAQuest, it does not su=
pport EBD model generation.</font></p>
<p align=3D"left"><font size=3D"2">Is there any software which produces EBD=
 from gerber ?</font></p>
<p align=3D"left"><font size=3D"2">Is there any freeware for it ?</font></p>
<p align=3D"left"><font size=3D"2">If any s/w is not available for me, how =
can I generate EBD with ease ?</font></p>
<p align=3D"left"><font size=3D"2">Thanks in advance,</font></p>
<p align=3D"left"><font size=3D"2">J.H. Kang</font></p>
</body>
</html>=
 
From owner-ibis Mon Apr 16 09:57:21 2001
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'Prasad Rau'" <prasad.rau@xilinx.com>, ibis-users@eda.org
Subject: RE: On chip Active termination
Date: Mon, 16 Apr 2001 09:56:19 -0700
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Hi Prasad:

  If by 'controlled impedance' you mean builing termination resistors or
clamps on die then yes, IBIS does support this.  Simply include the on die
termination in the circuit when extracting the I/V data for the [Gnd Clamp]
or [PWR Clamp] curves.

  Also, everyone please note that for vendor specific tool questions you
should contact the vendor directly.  Per EIA policy, the ibis-users and ibis
reflectors are for IBIS related discussions only.

  Regards,
  Stephen Peters
  Intel Corp.
  Vice Chair, EIA/IBIS Open Forum


-----Original Message-----
From: Prasad Rau [mailto:prasad.rau@xilinx.com]
Sent: Friday, April 13, 2001 5:58 PM
To: ibis-users@eda.org
Subject: On chip Active termination


Hi,

On our current design we support several standards using controlled
impedance. By using this scheme
we can mimic driver or receiver end terminations for standards like
SSTL,HSTLs
and GTL. The onchip termination is done using active devices as opposed to
passive
elements.  For example in the SSTL2 Class I the parallel termination is at
the receiver end.
Using the controlled impedance scheme we can eliminate the series & parallel
termination resistor son the board.
I have created seperate IBIS models for the output and the input. When I use
the output model
and drive the input model through a Tline using the HyperLynx tool I am not
seeing the right
levels at the receiver end. It is telling me that the termination at the
receiver is missing. I know
that the input IBIS model makes sense because if I look at the GND clamp
curve I observe ~ 0mA
current at 1.3V ( which is the valid voltage level with the output
tristated). The same driver model
if it drives a non controlled impedance receiver with the appropriate board
termination at the receiver
gives me the correct levels at the receiver.

 Is HyperLynx unable to recognize onchip termination input IBIS models ? Has
aynone
worked with controlled impedance and have suggestions in modelling them in
IBIS.


Appreciate your help in this regard.


Thanks in advance,


Regards,

Prasad Rau
Xilinx




 
From owner-ibis Mon Apr 16 11:12:44 2001
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Sender: "Prasad Rau" <Prasad.Rau@xilinx.com>
Message-ID: <3ADB38BB.C61088F1@xilinx.com>
Date: Mon, 16 Apr 2001 11:23:55 -0700
From: Prasad Rau <prasad.rau@xilinx.com>
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To: "Peters Stephen" <stephen.peters@intel.com>
CC: ibis-users@eda.org
Subject: On chip Active termination
References: <7FD5C79AD680D211AC4100A0C96B501C084A7645@orsmsx49.jf.intel.com>
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Hi Stephen,

Thanks for your feedback. My intention was to make sure I was not
making a modelling mistake before I questioned the tool. I should have
perhaps, framed my questions differently. My apologies to the IBIS
community.

Regards,

Prasad




"Peters, Stephen" wrote:

> Hi Prasad:
>
>   If by 'controlled impedance' you mean builing termination resistors or
> clamps on die then yes, IBIS does support this.  Simply include the on die
> termination in the circuit when extracting the I/V data for the [Gnd Clamp]
> or [PWR Clamp] curves.
>
>   Also, everyone please note that for vendor specific tool questions you
> should contact the vendor directly.  Per EIA policy, the ibis-users and ibis
> reflectors are for IBIS related discussions only.
>
>   Regards,
>   Stephen Peters
>   Intel Corp.
>   Vice Chair, EIA/IBIS Open Forum
>
> -----Original Message-----
> From: Prasad Rau [mailto:prasad.rau@xilinx.com]
> Sent: Friday, April 13, 2001 5:58 PM
> To: ibis-users@eda.org
> Subject: On chip Active termination
>
> Hi,
>
> On our current design we support several standards using controlled
> impedance. By using this scheme
> we can mimic driver or receiver end terminations for standards like
> SSTL,HSTLs
> and GTL. The onchip termination is done using active devices as opposed to
> passive
> elements.  For example in the SSTL2 Class I the parallel termination is at
> the receiver end.
> Using the controlled impedance scheme we can eliminate the series & parallel
> termination resistor son the board.
> I have created seperate IBIS models for the output and the input. When I use
> the output model
> and drive the input model through a Tline using the HyperLynx tool I am not
> seeing the right
> levels at the receiver end. It is telling me that the termination at the
> receiver is missing. I know
> that the input IBIS model makes sense because if I look at the GND clamp
> curve I observe ~ 0mA
> current at 1.3V ( which is the valid voltage level with the output
> tristated). The same driver model
> if it drives a non controlled impedance receiver with the appropriate board
> termination at the receiver
> gives me the correct levels at the receiver.
>
>  Is HyperLynx unable to recognize onchip termination input IBIS models ? Has
> aynone
> worked with controlled impedance and have suggestions in modelling them in
> IBIS.
>
> Appreciate your help in this regard.
>
> Thanks in advance,
>
> Regards,
>
> Prasad Rau
> Xilinx

 
From owner-ibis Mon Apr 16 11:36:11 2001
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From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
To: "'Prasad Rau'" <prasad.rau@xilinx.com>
Cc: ibis-users@eda.org
Subject: RE: On chip Active termination
Date: Mon, 16 Apr 2001 14:34:18 -0400
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... if I look at the GND clamp curve I observe ~ 0mA
> current at 1.3V ( which is the valid voltage level with the output
> tristated).
 
This may not be directly related to your question....

I am just curious whether it is appropriate to put your active termination
in the [GND clamp] curve.

If a supply voltage is involved in this on-chip termination, then the I/V
characteristics would vary with the supply voltage.  Putting the termination
I/V data in only the [GND Clamp] table means that it would not vary with
supply voltage, in the IBIS model.

If the termination is (or behaves like) something other than a resistance to
just the supply, then you could split the termination current between the
[GND Clamp] and [POWER Clamp] tables, to make the model more accurate.

Sorry if this is what you have already done.

Regards,
Andy

 
From owner-ibis Mon Apr 16 14:45:53 2001
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From: "Yaping Zhou" <y.zhou@motorola.com>
To: <ibis-users@eda.org>
Subject: signup for IBIS Users' Group Reflector
Date: Mon, 16 Apr 2001 16:45:12 -0500
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Thanks,
-- 
**************************************
Yaping Zhou (r3aadv)
(512) 933-5803
Motorola Semiconductor Products Sector
Final Manufacturing Technology Center
Ed Bluestein, Austin, Texas
**************************************


 
From owner-ibis Mon Apr 16 17:03:49 2001
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From: "=?euc-kr?b?sK3Bvsij?="<jhkang@sr.hynix.com>
Reply-To: 
To: ibis-users@eda.org
Cc: 
Subject: cadence dml (BoardModel) syntax
Date: Tue, 17 Apr 2001 09:02:41 +0900
Message-ID: <OFB1BFBD81.C0E4D234-ON49256A31.00003F34@LocalDomain>
X-MIMETrack: Serialize by Router on HIC2000/S/HEI(Release 5.0.5 |September 22, 2000) at
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<html>
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<meta name=3D"GENERATOR" content=3D"Namo WebEditor ActiveX Control v2.1">
</head>
<body bgcolor=3D"white" text=3D"black" link=3D"blue" vlink=3D"purple" alink=
=3D"red">

<p style=3D"margin-top:0; margin-bottom:0;"><font face=3D"=B1=BC=B8=B2">I n=
eed to convert Cadence dml file(BoardModel) to EBD file.</font></p>
<p style=3D"margin-top:0; margin-bottom:0;"><font face=3D"=B1=BC=B8=B2">So,=
 I need to understand syntax of dml file exactly.</font></p>
<p style=3D"margin-top:0; margin-bottom:0;"><font face=3D"=B1=BC=B8=B2">But=
 I have little information about dml.</font></p>
<p style=3D"margin-top:0; margin-bottom:0;"><font face=3D"=B1=BC=B8=B2">Is =
there any Cadence engineer who can help me ?</font></p>
<p style=3D"margin-top:0; margin-bottom:0;"><font face=3D"=B1=BC=B8=B2">I n=
eed detail information about dml syntax.</font></p>
<p style=3D"margin-top:0; margin-bottom:0;">&nbsp;</p>
</body>
</html>=
 
From owner-ibis Mon Apr 16 17:19:27 2001
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From: "Peters, Stephen" <stephen.peters@intel.com>
To: "'???'" <jhkang@sr.hynix.com>, ibis-users@eda.org
Subject: RE: cadence dml (BoardModel) syntax
Date: Mon, 16 Apr 2001 17:16:43 -0700
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Hi Mr Kang:
 
  For questions related directly to a vendors product please contact the
vendor directly.  Per EIA policy, the ibis-users reflector is for
discussion of quesitons related to IBIS models only.
 
  Thanks and regards,
  Stephen Peters
  Intel Corp.
  Vice Chair, EIA/IBIS Open Forum
  

-----Original Message-----
From: jhkang@sr.hynix.com [mailto:jhkang@sr.hynix.com]
Sent: Monday, April 16, 2001 5:03 PM
To: ibis-users@eda.org
Subject: cadence dml (BoardModel) syntax



I need to convert Cadence dml file(BoardModel) to EBD file.

So, I need to understand syntax of dml file exactly.

But I have little information about dml.

Is there any Cadence engineer who can help me ?

I need detail information about dml syntax.

 


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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dks_c_5601-1987">
<TITLE>Untitled</TITLE>

<META content=3D"MSHTML 5.00.2920.0" name=3DGENERATOR></HEAD>
<BODY aLink=3Dred bgColor=3Dwhite link=3Dblue text=3Dblack =
vLink=3Dpurple>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D320411200-17042001>Hi Mr=20
Kang:</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D320411200-17042001></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D320411200-17042001>&nbsp;=20
For questions related directly to a vendors product please contact the =
vendor=20
directly.&nbsp; Per EIA policy, the ibis-users reflector is for =
discussion=20
of&nbsp;quesitons related to IBIS models only.</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D320411200-17042001></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D320411200-17042001>&nbsp;=20
Thanks and regards,</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D320411200-17042001>&nbsp;=20
Stephen Peters</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D320411200-17042001>&nbsp;=20
Intel Corp.</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D320411200-17042001>&nbsp;=20
Vice Chair,&nbsp;EIA/IBIS Open Forum</SPAN></FONT></DIV>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D320411200-17042001>&nbsp;=20
</SPAN></FONT></DIV>
<BLOCKQUOTE style=3D"MARGIN-RIGHT: 0px">
  <DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
  size=3D2>-----Original Message-----<BR><B>From:</B> =
jhkang@sr.hynix.com=20
  [mailto:jhkang@sr.hynix.com]<BR><B>Sent:</B> Monday, April 16, 2001 =
5:03=20
  PM<BR><B>To:</B> ibis-users@eda.org<BR><B>Subject:</B> cadence dml=20
  (BoardModel) syntax<BR><BR></DIV></FONT>
  <P style=3D"MARGIN-BOTTOM: 0px; MARGIN-TOP: 0px"><FONT =
face=3D=B1=BC=B8=B2>I need to convert=20
  Cadence dml file(BoardModel) to EBD file.</FONT></P>
  <P style=3D"MARGIN-BOTTOM: 0px; MARGIN-TOP: 0px"><FONT =
face=3D=B1=BC=B8=B2>So, I need to=20
  understand syntax of dml file exactly.</FONT></P>
  <P style=3D"MARGIN-BOTTOM: 0px; MARGIN-TOP: 0px"><FONT =
face=3D=B1=BC=B8=B2>But I have little=20
  information about dml.</FONT></P>
  <P style=3D"MARGIN-BOTTOM: 0px; MARGIN-TOP: 0px"><FONT =
face=3D=B1=BC=B8=B2>Is there any=20
  Cadence engineer who can help me ?</FONT></P>
  <P style=3D"MARGIN-BOTTOM: 0px; MARGIN-TOP: 0px"><FONT =
face=3D=B1=BC=B8=B2>I need detail=20
  information about dml syntax.</FONT></P>
  <P=20
style=3D"MARGIN-BOTTOM: 0px; MARGIN-TOP: =
0px">&nbsp;</P></BLOCKQUOTE></BODY></HTML>

------_=_NextPart_001_01C0C6D3.AEA9DA20--

 
From owner-ibis Wed Apr 18 10:17:56 2001
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Date: Wed, 18 Apr 2001 10:17:15 -0700
From: Bob Ross <bob_ross@mentorg.com>
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Subject: IBIS Version 3.2 [Fwd: IEC 62014-1 Ed.1]
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To All:

Cecilia Fleming of EIA reports that IBIS Version 3.2 has
been approved for release as an international standard
under IEC.  The vote link is below.

It should be published by IEC in about a month.

Bob Ross
Mentor Graphics
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Bob:

It looks like it was approved go to:

http://www.iec.ch/cgi-bin/procgi.pl/www/iecwww.p?wwwlang=3DE&wwwprog=3Dv=
ote2.p&wcom=3D93&wclass=3D&wdoc=3D129&wsup=3D

Cece

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From owner-ibis Thu Apr 19 15:02:52 2001
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From: "Kris Young" <kyoung@phaseiv.com>
To: <ibis-users@eda.org>
Subject: another ebd modeling question
Date: Thu, 19 Apr 2001 17:01:41 -0500
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I have one more question for the IBIS gurus out there.  I'm using Pspice to
model a signal path from an EBD file.  I've figured out everything except
what to do when the length is zero and there's an L and a C.  When I look at
the classic lumped lossy line (taking R=0 and G=inf), the series L comes
first and then the parallel C.  However, when I look at the classic lossless
case, the parallel C comes first, and then the series L.

Since the impedances of these configurations differ, which one should I use.
I can only guess, but it should be clearer than that, right?  Would the
lossy case be the one to use, even if there's no R?

Thanks again,

Kris Young

 
From owner-ibis Fri Apr 20 03:41:31 2001
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Kris,

Why not use the PSPICE transmission line model? It is a true distributed
transmission line model, so you don't have to be concerned about how
to do the lumping. Also, it accepts per-length RLGC values. For example:

T3 one_end 0 other_end 0 LEN=1 C=3.1p L=1.05p

PSPICE accepts the notion that LEN is not in any particular units,
same as EBD. Of course you can add R= and G= for lossy lines, too.

That said, if you still need to create a lumped model, try splitting
the series elements in two to make it symmetric. For example, use
two inductors, each with half the inductance. This way a signal going
one way comes out identical to the same signal going the other way.
You can leave the middle series elements unsplit.

Mike LaBonte

Kris Young wrote:
> 
> I have one more question for the IBIS gurus out there.  I'm using Pspice to
> model a signal path from an EBD file.  I've figured out everything except
> what to do when the length is zero and there's an L and a C.  When I look at
> the classic lumped lossy line (taking R=0 and G=inf), the series L comes
> first and then the parallel C.  However, when I look at the classic lossless
> case, the parallel C comes first, and then the series L.
> 
> Since the impedances of these configurations differ, which one should I use.
> I can only guess, but it should be clearer than that, right?  Would the
> lossy case be the one to use, even if there's no R?
> 
> Thanks again,
> 
> Kris Young
 
From owner-ibis Fri Apr 20 07:35:24 2001
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From: "Kris Young" <kyoung@phaseiv.com>
To: "Mike LaBonte" <mike@labonte.com>
Cc: <ibis-users@eda.org>
Subject: RE: another ebd modeling question
Date: Fri, 20 Apr 2001 09:34:04 -0500
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Mike,

I have been using the PSPICE distributed transmission line model, and you're
right, it's very convenient to plug in the values from the EBD file.  I was
very relieved when I figured that out.

My question concerns the special case in the EBD file when LEN=0.
Supposedly this requires the use of a lumped element.  For instance, when
LEN=0 and R=0.003, it is specifying a series 3 mOhm resistor.  In the file
I'm simulating, there are a few cases where LEN=0, and L and C are
specified.  I'm trying to figure out what configuration of L and C is
specified by such a description.

Kris Young
Phase IV Systems, Inc.
Huntsville, AL

-----Original Message-----
From: Mike LaBonte [mailto:mike@labonte.com]
Sent: Friday, April 20, 2001 5:39 AM
To: Kris Young
Cc: ibis-users@eda.org
Subject: Re: another ebd modeling question


Kris,

Why not use the PSPICE transmission line model? It is a true distributed
transmission line model, so you don't have to be concerned about how
to do the lumping. Also, it accepts per-length RLGC values. For example:

T3 one_end 0 other_end 0 LEN=1 C=3.1p L=1.05p

PSPICE accepts the notion that LEN is not in any particular units,
same as EBD. Of course you can add R= and G= for lossy lines, too.

That said, if you still need to create a lumped model, try splitting
the series elements in two to make it symmetric. For example, use
two inductors, each with half the inductance. This way a signal going
one way comes out identical to the same signal going the other way.
You can leave the middle series elements unsplit.

Mike LaBonte

Kris Young wrote:
>
> I have one more question for the IBIS gurus out there.  I'm using Pspice
to
> model a signal path from an EBD file.  I've figured out everything except
> what to do when the length is zero and there's an L and a C.  When I look
at
> the classic lumped lossy line (taking R=0 and G=inf), the series L comes
> first and then the parallel C.  However, when I look at the classic
lossless
> case, the parallel C comes first, and then the series L.
>
> Since the impedances of these configurations differ, which one should I
use.
> I can only guess, but it should be clearer than that, right?  Would the
> lossy case be the one to use, even if there's no R?
>
> Thanks again,
>
> Kris Young

 
From owner-ibis Fri Apr 20 11:17:44 2001
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From owner-ibis Mon Apr 23 06:41:31 2001
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Subject: Temperature variations
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From: Hayes <jhayes@btv.ibm.com>


To my knowledge an IBIS model is unable to account for temperature 
variations at a fixed process corner.  My customer claims otherwise.  
Without additional information within a simple CMOS model, I do not see 
how this possible. Could someone clarify my understanding on this issue?

Thanks,
Jerry  

  


 
From owner-ibis Mon Apr 23 09:43:26 2001
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Jerry,

You are correct.  An IBIS model is extracted at a process corner with
a fixed temperature.  It is possible to perform multiple extractions at
various temperatures for each process corner and create multiple
IBIS models to show this behavior ... although this is not normally done.

What is normally done is that a behavioral model is extracted for CMOS
under the following conditions:

fast-n, fast-p,  low temperature
nominal-n, nominal-p, room temperature
slow-n, slow-p, high temperature

If there is some reason to have extractions at more than one temperature
for each process corner, then separate IBIS models could be extracted.
These models would then be valid at those new temperatures.  Normally,
if device behavior is linear with respect to temperature, then it should
only be necessary to perform the extraction at the temperature extremes,
as is usually done.

regards,

scott

--
Scott McMorrow
Principal Engineer
SiQual, Signal Quality Engineering
18735 SW Boones Ferry Road
Tualatin, OR  97062-3090
(503) 885-1231
http://www.siqual.com



Hayes wrote:

> To my knowledge an IBIS model is unable to account for temperature
> variations at a fixed process corner.  My customer claims otherwise.
> Without additional information within a simple CMOS model, I do not see
> how this possible. Could someone clarify my understanding on this issue?
>
> Thanks,
> Jerry
>
>




 
From owner-ibis Mon Apr 23 09:52:53 2001
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From: Offer Kaye <sofferk@techst02.technion.ac.il>
To: Hayes <jhayes@btv.ibm.com>
Cc: ibis-users@eda.org
Subject: Re: Temperature variations
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To the best of my knowledge, the [Temperature Range] keyword together with
the Typ, Min, Max columns for the various IBIS parameters account together
for this issue.

Offer Kaye
sofferk@techst02.technion.ac.il


On Mon, 23 Apr 2001, Hayes wrote:

> 
> To my knowledge an IBIS model is unable to account for temperature 
> variations at a fixed process corner.  My customer claims otherwise.  
> Without additional information within a simple CMOS model, I do not see 
> how this possible. Could someone clarify my understanding on this issue?
> 
> Thanks,
> Jerry  
> 
>   
> 
> 
> 

 
From owner-ibis Mon Apr 23 11:36:29 2001
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From: "Ingraham, Andrew" <Andrew.Ingraham@compaq.com>
To: "'Hayes'" <jhayes@btv.ibm.com>
Cc: ibis-users@eda.org
Subject: RE: Temperature variations
Date: Mon, 23 Apr 2001 14:35:59 -0400
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> To my knowledge an IBIS model is unable to account for temperature 
> variations at a fixed process corner.  My customer claims otherwise.  
> Without additional information within a simple CMOS model, I do not see 
> how this possible. Could someone clarify my understanding on this issue? 
 
IBIS models do (or are supposed to) account for the full temperature range
over which they are specified.  But they do not allow for simulations to
vary as a function of temperature variations.

Performance of CMOS and Bipolar process ICs tend to vary in opposite
directions versus temperature.  IBIS models are blind to the process.

Regards,
Andy

 
From owner-ibis Mon Apr 23 12:24:53 2001
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From: "Mathew, Elizabeth (MED)" <Elizabeth.Mathew@med.ge.com>
To: ibis-users@eda.org
Subject: IBIS Model question
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Hi IBIS Gurus,
                     In the IBIS model of any part does the term
"dv/dt_r" correspond to the rise time (tr - as denoted in the datasheet)
of that particular part?
Thanks,
Elizabeth

Elizabeth Mathew
Signal Integrity Expert,
Global Electrical Technology Center,
GE Medical Systems,
Phone:(262)544-3776
Fax:(262)548-2315
<mailto:Elizabeth.Mathew@med.ge.com>

 
From owner-ibis Mon Apr 23 13:08:00 2001
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dv/dt_r : seems like its a propogation velocity/ actually acceleration--it
might be the rise time . However I am not sure.


"Mathew, Elizabeth (MED)" wrote:

> Hi IBIS Gurus,
>                      In the IBIS model of any part does the term
> "dv/dt_r" correspond to the rise time (tr - as denoted in the datasheet)
> of that particular part?
> Thanks,
> Elizabeth
>
> Elizabeth Mathew
> Signal Integrity Expert,
> Global Electrical Technology Center,
> GE Medical Systems,
> Phone:(262)544-3776
> Fax:(262)548-2315
> <mailto:Elizabeth.Mathew@med.ge.com>

--
*********************************************************************
Abdulrahman A. Rafiq (AKA Abbey)
Hardware/Layout Engineer

CISCO SYSTEMS INC.
Signal Integrity and Packaging Group
230 West Tasman Drive
Mail Stop: SJ/G/2/3
San Jose, Ca 95134
(Bldg: G-2, Office: 227)

Voice: (408) 527-5540
Fax  : (408) 526-8573
Pager: (408) 301-8880
email: arafiq@cisco.com
epage: arafiq@epage.cisco.com
Webpage: http://wwwin-people.cisco.com/~arafiq
Group Page: http://wwwin-sipd.cisco.com
*********************************************************************



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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
dv/dt_r : seems like its a propogation velocity/ actually acceleration--it
might be the rise time . However I am not sure.
<br>&nbsp;
<p>"Mathew, Elizabeth (MED)" wrote:
<blockquote TYPE=CITE>Hi IBIS Gurus,
<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
In the IBIS model of any part does the term
<br>"dv/dt_r" correspond to the rise time (tr - as denoted in the datasheet)
<br>of that particular part?
<br>Thanks,
<br>Elizabeth
<p>Elizabeth Mathew
<br>Signal Integrity Expert,
<br>Global Electrical Technology Center,
<br>GE Medical Systems,
<br>Phone:(262)544-3776
<br>Fax:(262)548-2315
<br>&lt;<a href="mailto:Elizabeth.Mathew@med.ge.com">mailto:Elizabeth.Mathew@med.ge.com</a>></blockquote>

<pre>--&nbsp;
*********************************************************************
Abdulrahman A. Rafiq (AKA Abbey)
Hardware/Layout Engineer

CISCO SYSTEMS INC.
Signal Integrity and Packaging Group
230 West Tasman Drive&nbsp;
Mail Stop: SJ/G/2/3
San Jose, Ca 95134
(Bldg: G-2, Office: 227)

Voice: (408) 527-5540
Fax&nbsp; : (408) 526-8573
Pager: (408) 301-8880
email: arafiq@cisco.com
epage: arafiq@epage.cisco.com
Webpage: <A HREF="http://wwwin-people.cisco.com/~arafiq">http://wwwin-people.cisco.com/~arafiq</A>
Group Page: <A HREF="http://wwwin-sipd.cisco.com">http://wwwin-sipd.cisco.com</A>
*********************************************************************</pre>
&nbsp;</html>

--------------7C7A69538E822E183675CF43--

 
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From: "Dagostino, Tom" <tom_dagostino@mentorg.com>
To: "'arafiq@cisco.com'" <arafiq@cisco.com>,
   "Mathew, Elizabeth (MED)"
	 <Elizabeth.Mathew@med.ge.com>
Cc: ibis-users@eda.org
Subject: RE: IBIS Model question
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From the IBIS 3.2 spec
 
BM__Toc460058252| Keyword: [Ramp]

| Required: Yes, except for inputs, terminators, Series and Series_switch

| model types.

| Description: Defines the rise and fall times of a buffer. The ramp rate

| does not include packaging but does include the effects of the

| C_comp parameter.

| Sub-Params: dV/dt_r, dV/dt_f, R_load

| Usage Rules: The rise and fall time is defined as the time it takes the

| output to go from 20% to 80% of its final value. The ramp

| rate is defined as:

|

| dV 20% to 80% voltage swing

| -- = ----------------------------------------

| dt Time it takes to swing the above voltage

|

| The ramp rate must be specified as an explicit fraction and

| must not be reduced. The [Ramp] values can use "NA" for the

| min and max values only. The R_load subparameter is optional

| if the default 50 ohm load is used. The R_load subparameter

| is required if a non-standard load is used.

|---------------------------------------------------------------------------
--

[Ramp]

| variable typ min max

dV/dt_r 2.20/1.06n 1.92/1.28n 2.49/650p

dV/dt_f 2.46/1.21n 2.21/1.54n 2.70/770p

R_load = 300ohms

 

Tom Dagostino 
IBIS and Tau Modeling Manager 
SDD 
Mentor Graphics Corp. 
503-685-1613 
tom_dagostino@mentor.com 

-----Original Message-----
From: Abdulrahman Rafiq [mailto:arafiq@cisco.com]
Sent: Monday, April 23, 2001 1:07 PM
To: Mathew, Elizabeth (MED)
Cc: ibis-users@eda.org
Subject: Re: IBIS Model question


dv/dt_r : seems like its a propogation velocity/ actually acceleration--it
might be the rise time . However I am not sure. 
  

"Mathew, Elizabeth (MED)" wrote: 


Hi IBIS Gurus, 
                     In the IBIS model of any part does the term 
"dv/dt_r" correspond to the rise time (tr - as denoted in the datasheet) 
of that particular part? 
Thanks, 
Elizabeth 

Elizabeth Mathew 
Signal Integrity Expert, 
Global Electrical Technology Center, 
GE Medical Systems, 
Phone:(262)544-3776 
Fax:(262)548-2315 
< mailto:Elizabeth.Mathew@med.ge.com <mailto:Elizabeth.Mathew@med.ge.com> >

-- 

*********************************************************************

Abdulrahman A. Rafiq (AKA Abbey)

Hardware/Layout Engineer



CISCO SYSTEMS INC.

Signal Integrity and Packaging Group

230 West Tasman Drive 

Mail Stop: SJ/G/2/3

San Jose, Ca 95134

(Bldg: G-2, Office: 227)



Voice: (408) 527-5540

Fax  : (408) 526-8573

Pager: (408) 301-8880

email: arafiq@cisco.com

epage: arafiq@epage.cisco.com

Webpage:  http://wwwin-people.cisco.com/~arafiq
<http://wwwin-people.cisco.com/~arafiq> 

Group Page:  http://wwwin-sipd.cisco.com <http://wwwin-sipd.cisco.com> 

*********************************************************************
  


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<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=737301420-23042001>From 
the IBIS 3.2 spec</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=737301420-23042001></SPAN></FONT>&nbsp;</DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN 
class=737301420-23042001><B><FONT face="Courier New" size=2>
<P><A name=_Toc460058252>| Keyword: [Ramp]</A></P></B>
<P>| Required: Yes, except for inputs, terminators, Series and Series_switch</P>
<P>| model types.</P>
<P>| Description: Defines the rise and fall times of a buffer. The ramp rate</P>
<P>| does not include packaging but does include the effects of the</P>
<P>| C_comp parameter.</P>
<P>| Sub-Params: dV/dt_r, dV/dt_f, R_load</P>
<P>| Usage Rules: The rise and fall time is defined as the time it takes the</P>
<P>| output to go from 20% to 80% of its final value. The ramp</P>
<P>| rate is defined as:</P>
<P>|</P>
<P>| dV 20% to 80% voltage swing</P>
<P>| -- = ----------------------------------------</P>
<P>| dt Time it takes to swing the above voltage</P>
<P>|</P>
<P>| The ramp rate must be specified as an explicit fraction and</P>
<P>| must not be reduced. The [Ramp] values can use "NA" for the</P>
<P>| min and max values only. The R_load subparameter is optional</P>
<P>| if the default 50 ohm load is used. The R_load subparameter</P>
<P>| is required if a non-standard load is used.</P>
<P>|-----------------------------------------------------------------------------</P>
<P>[Ramp]</P>
<P>| variable typ min max</P>
<P>dV/dt_r 2.20/1.06n 1.92/1.28n 2.49/650p</P>
<P>dV/dt_f 2.46/1.21n 2.21/1.54n 2.70/770p</P>
<P>R_load = 300ohms</P></FONT></SPAN></FONT></DIV>
<DIV>&nbsp;</DIV>
<P><FONT face=Arial size=2>Tom Dagostino</FONT> <BR><FONT face=Arial size=2>IBIS 
and Tau Modeling Manager</FONT> <BR><FONT face=Arial size=2>SDD</FONT> <BR><FONT 
face=Arial size=2>Mentor Graphics Corp.</FONT> <BR><FONT face=Arial 
size=2>503-685-1613</FONT> <BR><FONT face=Arial 
size=2>tom_dagostino@mentor.com</FONT> </P>
<BLOCKQUOTE>
  <DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma 
  size=2>-----Original Message-----<BR><B>From:</B> Abdulrahman Rafiq 
  [mailto:arafiq@cisco.com]<BR><B>Sent:</B> Monday, April 23, 2001 1:07 
  PM<BR><B>To:</B> Mathew, Elizabeth (MED)<BR><B>Cc:</B> 
  ibis-users@eda.org<BR><B>Subject:</B> Re: IBIS Model 
  question<BR><BR></DIV></FONT>dv/dt_r : seems like its a propogation velocity/ 
  actually acceleration--it might be the rise time . However I am not sure. 
  <BR>&nbsp; 
  <P>"Mathew, Elizabeth (MED)" wrote: 
  <BLOCKQUOTE TYPE="CITE">Hi IBIS Gurus, 
    <BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
    In the IBIS model of any part does the term <BR>"dv/dt_r" correspond to the 
    rise time (tr - as denoted in the datasheet) <BR>of that particular part? 
    <BR>Thanks, <BR>Elizabeth 
    <P>Elizabeth Mathew <BR>Signal Integrity Expert, <BR>Global Electrical 
    Technology Center, <BR>GE Medical Systems, <BR>Phone:(262)544-3776 
    <BR>Fax:(262)548-2315 <BR>&lt;<A 
    href="mailto:Elizabeth.Mathew@med.ge.com">mailto:Elizabeth.Mathew@med.ge.com</A>&gt;</P></BLOCKQUOTE><PRE>--&nbsp;
*********************************************************************
Abdulrahman A. Rafiq (AKA Abbey)
Hardware/Layout Engineer

CISCO SYSTEMS INC.
Signal Integrity and Packaging Group
230 West Tasman Drive&nbsp;
Mail Stop: SJ/G/2/3
San Jose, Ca 95134
(Bldg: G-2, Office: 227)

Voice: (408) 527-5540
Fax&nbsp; : (408) 526-8573
Pager: (408) 301-8880
email: arafiq@cisco.com
epage: arafiq@epage.cisco.com
Webpage: <A href="http://wwwin-people.cisco.com/~arafiq">http://wwwin-people.cisco.com/~arafiq</A>
Group Page: <A href="http://wwwin-sipd.cisco.com">http://wwwin-sipd.cisco.com</A>
*********************************************************************</PRE>&nbsp; 
</BLOCKQUOTE></BODY></HTML>

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From owner-ibis Mon Apr 23 14:16:12 2001
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CC: ibis-users@eda.org
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"Mathew, Elizabeth (MED)" wrote:
> 
> Hi IBIS Gurus,
>                      In the IBIS model of any part does the term
> "dv/dt_r" correspond to the rise time (tr - as denoted in the datasheet)
> of that particular part?
> Thanks,
> Elizabeth
> 
> Elizabeth Mathew
> Signal Integrity Expert,
> Global Electrical Technology Center,
> GE Medical Systems,
> Phone:(262)544-3776
> Fax:(262)548-2315
> <mailto:Elizabeth.Mathew@med.ge.com>

dV/dt_r is defined as the time to go from 20% to 80%
of the swing from low to high.  This may not correspond exactly
to the risetime as defined in a datasheet; you have to check how
it's measured for the datasheet to be sure.


-- 
Kim Helliwell
Senior CAE Engineer
Acuson Corporation
Phone: 650 694 5030  FAX: 650 943 7260
 
From owner-ibis Tue Apr 24 12:41:38 2001
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Date: Tue, 24 Apr 2001 14:37:42 -0500
From: r6aabt@email.sps.mot.com (Jay Azurin)
Organization: Motorola Semiconductor Products Sector
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Subject: Package Parasitics
References: <200101311917.LAA22736@phys-ha1mpka.eng.sun.com>
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Hello,

I am new to the IBIS game so pardon my simplistic question. I would like
to know the meaning of the values in an IBIS model: 

[Package]                                                       

|variable       typ     min     max                             

R_pkg           250m    200m    300m                    

L_pkg           8nH     5nH     12nH                    

C_pkg           0.7pF   0.56pF  1.2pF   
|               


I have found other models that have these values set to zero:

 
> > > [Package]
> > > R_pkg   0   0   0
> > > L_pkg   0   0   0
> > > C_pkg   0   0   0


Can you explain why these values are used, i.e. why the model would be
realistic with no package parasitics?

Thanks for your help.


Best regards,
Jay Azurin
Motorola NetComm Applications
 
From owner-ibis Tue Apr 24 14:46:57 2001
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CC: ibis-users@eda.org
Subject: Re: Package Parasitics
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Jay Azurin wrote:
> 
> Hello,
> 
> I am new to the IBIS game so pardon my simplistic question. I would like
> to know the meaning of the values in an IBIS model:
> 
> [Package]
> 
> |variable       typ     min     max
> 
> R_pkg           250m    200m    300m
> 
> L_pkg           8nH     5nH     12nH
> 
> C_pkg           0.7pF   0.56pF  1.2pF
> |
> 
> I have found other models that have these values set to zero:
> 
> 
> > > > [Package]
> > > > R_pkg   0   0   0
> > > > L_pkg   0   0   0
> > > > C_pkg   0   0   0
> 
> Can you explain why these values are used, i.e. why the model would be
> realistic with no package parasitics?
> 
> Thanks for your help.
> 
> Best regards,
> Jay Azurin
> Motorola NetComm Applications

The package parasitics might be included in the pullup, pulldown, and clamp
curves in some way.  While this is permissible (I think), it makes it much
harder to re-use the pullup/pulldown/clamp curves for any other package.  The
whole point of separating these effects is to allow re-use of the curves with
different package models.
-- 
Kim Helliwell
Senior CAE Engineer
Acuson Corporation
Phone: 650 694 5030  FAX: 650 943 7260
 
From owner-ibis Tue Apr 24 15:04:34 2001
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Date: Tue, 24 Apr 2001 15:03:55 -0700 (PDT)
From: Syed Huq <shuq@cisco.com>
Reply-To: Syed Huq <shuq@cisco.com>
Subject: Re: Package Parasitics
To: r6aabt@email.sps.mot.com
Cc: ibis-users@eda.org
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One reason could be is that a ASIC vendor is simply creating "buffer only"
models without any package parasitics. Once the ASIC is defined(with package)
then you create the full IBIS model with all the individual buffers along
with the package parameters..

For a commercially available component, it does not make sense to have
a model without the package parasitics.

Syed
Cisco Systems, Inc 



>
> > |
> > 
> > I have found other models that have these values set to zero:
> > 
> > 
> > > > > [Package]
> > > > > R_pkg   0   0   0
> > > > > L_pkg   0   0   0
> > > > > C_pkg   0   0   0
> > 
> > Can you explain why these values are used, i.e. why the model would be
> > realistic with no package parasitics?
> > 
> > Thanks for your help.
> > 
> > Best regards,
> > Jay Azurin
> > Motorola NetComm Applications
> 

 
From owner-ibis Tue Apr 24 16:16:00 2001
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To: "'Kim Helliwell'" <khelliwe@acuson.com>,
   Jay Azurin
	 <r6aabt@email.sps.mot.com>
Cc: ibis-users@eda.org
Subject: RE: Package Parasitics
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Hello,

It's also possible to have pin specific parasitics which override the Package specific parasitics.

| ----- Cut from the IBIS 2.1 specification -----
[Pin]   signal_name     model_name      R_pin   L_pin   C_pin
|
  1     RAS0#           Buffer1         200.0m  5.0nH   2.0pF
  2     RAS1#           Buffer2         209.0m  NA      2.5pF
| ------------------------------------------------

Regards
Dave

David Makihara
Manager, System Interface Modelling
PMC-Sierra Inc.
105-8555 Baxter Place
Burnaby, BC V5A 4V7
tel:604-415-6000 ext 2422
fax:604-415-6206
e-mail:makihara@pmc-sierra.bc.ca
website: http://www.pmc-sierra.com



> -----Original Message-----
> From: Kim Helliwell [mailto:khelliwe@acuson.com]
> Sent: Tuesday, April 24, 2001 2:46 PM
> To: Jay Azurin
> Cc: ibis-users@eda.org
> Subject: Re: Package Parasitics
> 
> 
> Jay Azurin wrote:
> > 
> > Hello,
> > 
> > I am new to the IBIS game so pardon my simplistic question. 
> I would like
> > to know the meaning of the values in an IBIS model:
> > 
> > [Package]
> > 
> > |variable       typ     min     max
> > 
> > R_pkg           250m    200m    300m
> > 
> > L_pkg           8nH     5nH     12nH
> > 
> > C_pkg           0.7pF   0.56pF  1.2pF
> > |
> > 
> > I have found other models that have these values set to zero:
> > 
> > 
> > > > > [Package]
> > > > > R_pkg   0   0   0
> > > > > L_pkg   0   0   0
> > > > > C_pkg   0   0   0
> > 
> > Can you explain why these values are used, i.e. why the 
> model would be
> > realistic with no package parasitics?
> > 
> > Thanks for your help.
> > 
> > Best regards,
> > Jay Azurin
> > Motorola NetComm Applications
> 
> The package parasitics might be included in the pullup, 
> pulldown, and clamp
> curves in some way.  While this is permissible (I think), it 
> makes it much
> harder to re-use the pullup/pulldown/clamp curves for any 
> other package.  The
> whole point of separating these effects is to allow re-use of 
> the curves with
> different package models.
> -- 
> Kim Helliwell
> Senior CAE Engineer
> Acuson Corporation
> Phone: 650 694 5030  FAX: 650 943 7260
> 
 
From owner-ibis Wed Apr 25 06:11:46 2001
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From: Mark Bossard <mbossard@atmel.com>
Organization: Atmel
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To: Syed Huq <shuq@cisco.com>
CC: r6aabt@email.sps.mot.com, ibis-users@eda.org
Subject: Re: Package Parasitics
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I agree with Syed... 

The ASIC house I work in does supply ibis models to our customers that
are simply an ibis model for one I/O buffer.  They are many times left
without package RLC so they can be filled in depending on the package
that is used.  

-Mark Bossard
Atmel Chesapeake Design Center

Syed Huq wrote:
> 
> One reason could be is that a ASIC vendor is simply creating "buffer only"
> models without any package parasitics. Once the ASIC is defined(with package)
> then you create the full IBIS model with all the individual buffers along
> with the package parameters..
> 
> For a commercially available component, it does not make sense to have
> a model without the package parasitics.
> 
> Syed
> Cisco Systems, Inc
> 
> >
> > > |
> > >
> > > I have found other models that have these values set to zero:
> > >
> > >
> > > > > > [Package]
> > > > > > R_pkg   0   0   0
> > > > > > L_pkg   0   0   0
> > > > > > C_pkg   0   0   0
> > >
> > > Can you explain why these values are used, i.e. why the model would be
> > > realistic with no package parasitics?
> > >
> > > Thanks for your help.
> > >
> > > Best regards,
> > > Jay Azurin
> > > Motorola NetComm Applications
> >

-- 

========================================================================
| Mark Bossard                     |                                   |
| Direct Phone: (410) 872-9267     | Atmel Corporation                 |
| Main Phone:   (410) 312-4400     | Chesapeake Design Center          |
| Fax:          (410) 312-4424     | 6740 Alexander Bell Dr, Suite 100 |
| Email:        mbossard@atmel.com | Columbia, MD 21046                |
========================================================================
 
From owner-ibis Wed Apr 25 08:02:44 2001
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From: "Muranyi, Arpad" <arpad.muranyi@intel.com>
To: ibis-users@eda.org
Subject: RE: Package Parasitics
Date: Wed, 25 Apr 2001 08:02:01 -0700
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Kim,

You cannot include the package parasitics in the pullup,
pulldown, and clamp IV curves.  The IV curves are DC
characteristics, and there is no way you can describe
AC effects with them, such as inductance, and capacitance.
The best you can do with these is the resistive losses in
the package.

The AC part may be described in the waveforms (Vt curves),
but that is not the best or most correct way to go about it.

Arpad Muranyi
Intel Corporation
=============================================================

-----Original Message-----
From: Kim Helliwell [mailto:khelliwe@acuson.com]
Sent: Tuesday, April 24, 2001 2:46 PM
To: Jay Azurin
Cc: ibis-users@eda.org
Subject: Re: Package Parasitics


Jay Azurin wrote:
> 
> Hello,
> 
> I am new to the IBIS game so pardon my simplistic question. I would like
> to know the meaning of the values in an IBIS model:
> 
> [Package]
> 
> |variable       typ     min     max
> 
> R_pkg           250m    200m    300m
> 
> L_pkg           8nH     5nH     12nH
> 
> C_pkg           0.7pF   0.56pF  1.2pF
> |
> 
> I have found other models that have these values set to zero:
> 
> 
> > > > [Package]
> > > > R_pkg   0   0   0
> > > > L_pkg   0   0   0
> > > > C_pkg   0   0   0
> 
> Can you explain why these values are used, i.e. why the model would be
> realistic with no package parasitics?
> 
> Thanks for your help.
> 
> Best regards,
> Jay Azurin
> Motorola NetComm Applications

The package parasitics might be included in the pullup, pulldown, and clamp
curves in some way.  While this is permissible (I think), it makes it much
harder to re-use the pullup/pulldown/clamp curves for any other package.
The
whole point of separating these effects is to allow re-use of the curves
with
different package models.
-- 
Kim Helliwell
Senior CAE Engineer
Acuson Corporation
Phone: 650 694 5030  FAX: 650 943 7260

 
From owner-ibis Wed Apr 25 09:09:41 2001
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From: "Nelson, Kerry" <kerry.nelson@intel.com>
To: r6aabt@email.sps.mot.com, ibis-users@eda.org
Cc: Syed Huq <shuq@cisco.com>, "'Mark Bossard'" <mbossard@atmel.com>
Subject: RE: Package Parasitics
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In addition to other reasons...

We have often found this section of the IBIS model to be inadequate in
describing our CPU and chipset packages. For example, there is no way to
include a transmission line element of any sort. We usually use a Package
Model or an Electrical Board Description (EBD) to more accurately describe
the package. (Both are part of the IBIS specification.) In those cases we
will set R_pkg, L_pkg, and C_pkg to zero.

I hope that helps.
Kerry
Intel Corp.

 -----Original Message-----
From: 	Mark Bossard [mailto:mbossard@atmel.com] 
Sent:	Wednesday, April 25, 2001 6:10 AM
To:	Syed Huq
Cc:	r6aabt@email.sps.mot.com; ibis-users@eda.org
Subject:	Re: Package Parasitics

I agree with Syed... 

The ASIC house I work in does supply ibis models to our customers that
are simply an ibis model for one I/O buffer.  They are many times left
without package RLC so they can be filled in depending on the package
that is used.  

-Mark Bossard
Atmel Chesapeake Design Center

Syed Huq wrote:
> 
> One reason could be is that a ASIC vendor is simply creating "buffer only"
> models without any package parasitics. Once the ASIC is defined(with
package)
> then you create the full IBIS model with all the individual buffers along
> with the package parameters..
> 
> For a commercially available component, it does not make sense to have
> a model without the package parasitics.
> 
> Syed
> Cisco Systems, Inc
> 
> >
> > > |
> > >
> > > I have found other models that have these values set to zero:
> > >
> > >
> > > > > > [Package]
> > > > > > R_pkg   0   0   0
> > > > > > L_pkg   0   0   0
> > > > > > C_pkg   0   0   0
> > >
> > > Can you explain why these values are used, i.e. why the model would be
> > > realistic with no package parasitics?
> > >
> > > Thanks for your help.
> > >
> > > Best regards,
> > > Jay Azurin
> > > Motorola NetComm Applications
> >

-- 

========================================================================
| Mark Bossard                     |                                   |
| Direct Phone: (410) 872-9267     | Atmel Corporation                 |
| Main Phone:   (410) 312-4400     | Chesapeake Design Center          |
| Fax:          (410) 312-4424     | 6740 Alexander Bell Dr, Suite 100 |
| Email:        mbossard@atmel.com | Columbia, MD 21046                |
========================================================================

 
From owner-ibis Thu Apr 26 00:54:55 2001
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Reply-To: "Jongho Kang" <jhkang@hynix.com>
From: "Jongho Kang" <jhkang@hynix.com>
To: <ibis-users@eda.org>, "Kris Young" <kyoung@phaseiv.com>
References: <IPEHLHEELKPPNKAMAFIPOEIDCCAA.kyoung@phaseiv.com>
Subject: Re: another ebd modeling question
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Kris,

Did you figure out what configuration of L and C is used when Len=0 and
L and C is specified ?
I'm in the same situation as you was.  I'm trying to describe C-L-C lumped
circuit in the EBD.
If you figured out , please let me know.

Thanks,
Jongho Kang

----- Original Message ----- 
From: Kris Young <kyoung@phaseiv.com>
To: Mike LaBonte <mike@labonte.com>
Cc: <ibis-users@eda.org>
Sent: Friday, April 20, 2001 11:34 PM
Subject: RE: another ebd modeling question


Mike,

I have been using the PSPICE distributed transmission line model, and you're
right, it's very convenient to plug in the values from the EBD file.  I was
very relieved when I figured that out.

My question concerns the special case in the EBD file when LEN=0.
Supposedly this requires the use of a lumped element.  For instance, when
LEN=0 and R=0.003, it is specifying a series 3 mOhm resistor.  In the file
I'm simulating, there are a few cases where LEN=0, and L and C are
specified.  I'm trying to figure out what configuration of L and C is
specified by such a description.

Kris Young
Phase IV Systems, Inc.
Huntsville, AL

-----Original Message-----
From: Mike LaBonte [mailto:mike@labonte.com]
Sent: Friday, April 20, 2001 5:39 AM
To: Kris Young
Cc: ibis-users@eda.org
Subject: Re: another ebd modeling question


Kris,

Why not use the PSPICE transmission line model? It is a true distributed
transmission line model, so you don't have to be concerned about how
to do the lumping. Also, it accepts per-length RLGC values. For example:

T3 one_end 0 other_end 0 LEN=1 C=3.1p L=1.05p

PSPICE accepts the notion that LEN is not in any particular units,
same as EBD. Of course you can add R= and G= for lossy lines, too.

That said, if you still need to create a lumped model, try splitting
the series elements in two to make it symmetric. For example, use
two inductors, each with half the inductance. This way a signal going
one way comes out identical to the same signal going the other way.
You can leave the middle series elements unsplit.

Mike LaBonte

Kris Young wrote:
>
> I have one more question for the IBIS gurus out there.  I'm using Pspice
to
> model a signal path from an EBD file.  I've figured out everything except
> what to do when the length is zero and there's an L and a C.  When I look
at
> the classic lumped lossy line (taking R=0 and G=inf), the series L comes
> first and then the parallel C.  However, when I look at the classic
lossless
> case, the parallel C comes first, and then the series L.
>
> Since the impedances of these configurations differ, which one should I
use.
> I can only guess, but it should be clearer than that, right?  Would the
> lossy case be the one to use, even if there's no R?
>
> Thanks again,
>
> Kris Young

 

