From owner-ibis  Mon Feb  2 10:58:51 1998
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From: bobr@emicx.mentorg.com (Bob Ross)
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Date: Mon, 2 Feb 98 10:55:58 PST
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To: atulapt@giascl01.vsnl.net.in
Subject: Re:  Series enhancement queries
Cc: ibis@eda.org, ibischk-bug@eda.org

Atul:

Sorry for the delay in responding.  As previously mentioned, I and
several other people were out of town.  When I got back, I needed
to deal with several other issues requiring less thinking before
I could focus on your questions.

My responses are embedded in your questions.  Comments from others
are welcome.  this is being copied to the ibis reflector for
information.

Best Regards
Bob


> Date: Mon, 26 Jan 1998 23:45:20 +0500
> To: bobr (Bob Ross)
> From: "Atul P. Agarwal" <atulapt@giascl01.vsnl.net.in>
> Subject: Series enhancement queries


> Hello Bob

> Thank you for the previous clarifications. Here are some more
> queries on the Series enhancements.

> a) For the Series and Series_switch models which of the following
> keywords should be allowed or disallowed ? For the ones that are
> disallowed, should there be an error or warning ?

I am filling your table with only those entries for which the ERROR (E)
and WARNING (W) messages should be issued.  The rest are allowed.

W   >         [Model Spec]        Currently permitted even when not applicable
E   >         [Driver Schedule]
>         [Temperature Range]
>         [Voltage Range]             Previously defined reference hierarchy
>         [Pullup Reference]          still applies here, even if some are
>         [Pulldown Reference]        not used.
>         [POWER Clamp Reference]
>         [GND Clamp Reference]
E  >         [TTgnd]
E  >         [TTpower]
E  >         [Pulldown]
E  >         [Pullup]
E  >         [GND Clamp]
E  >         [POWER Clamp]
E  >         [Ramp]
E  >         [Rising Waveform]
E  >         [Falling Waveform]

> b) For the keywords above which are allowable for Series_switch, do they
> need to be specified twice, both under [On] and [Off] keywords if a user
> wants them to be meaningful both under the on and off states ?

Both [On] and [Off] should be required.  The both must be filled with
a meaningful entry (see below).  The keywords used under [On] could be
different than used under [Off].  For example the series switch sample
under eda.org/pup/ibis/samples/ver3.0/cbt.ibs  uses [Series MOSFET]
for the [On] model and [R Series] for a high impedance [Off] model.

> Is the [Series MOSFET] keyword valid under the [Off] keyword or should it be 
> specified only under the [On] keyword ? 

The [Series MOSFET] is invalid and meaningless under the [Off] keyword.


> c) If [Ramp] is not a required keyword for Series and Series_switch models
> there needs to be an editorial change under [Ramp]
> |
> Keyword: [Ramp]
> Required: Yes, except for inputs, terminators, Series and Series_switch model
> types.
> |

Thank you for that correction.  This will be made as an editioral correction.

> d) For the Series and Series_switch models which of the following
> sub parameters should be allowed or disallowed ? For the ones that are
> disallowed, should there be an error or warning ?

>         Polarity
>         Enable
>         Vinl
>         Vinh
>         C_comp 
>         Vmeas
>         Cref
>         Rref
>         Vref

The ibischk2 parser does not issue any warnings for non-used subparameters
under [Model].  None of the above are used, but no message should be
issued.  If we were to add such messages, then we would have to do
it for all model types, under [Model].

By other rules. C_comp remains required, but not used.

> e) Is an empty [On] or [Off] keyword section allowed ?
> |
> [On]
> [Off]
> [R_series] .......
> |

Empty [On] or [Off] sections should be flagged as an error.  While we
could default to a high impedance, I would rather require the model
developer to put in what he/she wants.  Otherwise we would not know
if the omission was a mistake or was intended.

> f) What is the maximum number of [Series MOSFET] keywords allowed per 
> series model. For the waveforms, the parser has a limit of 100.

This is not specified.  I would check against 100, just as with waveform
tables.  In practice, I do not expect to ever see that many [Series MOSFET]
models.  

> Can there be two [Series MOSFETS] keywords with the 
> same value for Vds  or should this be flagged as an error ?

This should be an Error since the tables could be different.  The
simulator could not process both.

> Thanks 

> atul




 
From owner-ibis  Mon Feb  2 11:05:02 1998
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From: bobr@emicx.mentorg.com (Bob Ross)
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Date: Mon, 2 Feb 98 11:02:17 PST
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To: atulapt@giascl01.vsnl.net.in
Subject: Re:  Clarifications
Cc: ibis@eda.org, ibischk-bug@eda.org

Atul:

Here are some additional responses.  This is also copied to the
IBIS reflector for information.

Best Regards,
Bob
Interconnectix BU

> Date: Fri, 30 Jan 1998 20:20:55 +0000 (GMT)
> From: "APT SOFTWARE AVENUES PVT.LTD" <atulapt@giascl01.vsnl.net.in>
> To: Bob Ross <bobr>
> Subject: Clarifications


> Hello Bob

> I had sent you a list of queries about a week back but have
> not heard from you. I hope that you did receive it. If not
> I can send it again.

> Meanwhile here are a couple more for you to look at.

> 1) In the IBIS Tree diagram for Version 3.0 (which you had
> given me), the [Model Selector] keyword is indicated within
> the [Component] scope. Now, a model selector is nothing
> but a "stand-in" for a model and models are defined at file
> scope. By this logic, shouldn't a [Model Selector] be at the
> file scope also ?

In my opinion the scope of [Model Selector] should remain under
[Component], just as shown in the Tree diagram.  This allows a
different [Component] in the same file which will access similar
models to have a different default model and different configurations.
For example, a different component may not offer a reduced set of
selections since one of the pins controling the selection may be NC.

> 2) Under DOS, as soon as a model has been parsed, the data structures 
> associated with the model are released to free the memory. I guess
> it is OK to keep those data structures around which will be needed
> to perform some checks after the complete file has been parsed,
> say, in the case of [Driver Schedule].

I am comfortable with this approach.  I do not see any problem.

> thanks for your help

> -- atul






 
From owner-ibis  Mon Feb  2 13:57:55 1998
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From: bobr@emicx.mentorg.com (Bob Ross)
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Date: Mon, 2 Feb 98 13:55:06 PST
Message-Id: <9802022155.AA06970@bob>
To: harunys@haselect.com, ibis-users@eda.org, ibis@eda.org
Subject: Re:  Consistancy between various simulators using IBIS models

Haruny:

This would be a good study for the IBIS Users group.  However,
I want to keep company-specific issues off the IBIS reflectors.
If there is any public discussion, then use the SI reflectors.

Best Regards,
Bob Ross
Interconnectix


> Date: Sat, 31 Jan 1998 00:59:28 -0500
> To: ibis@eda.org
> From: Haruny Said <harunys@haselect.com>
> Subject: Consistancy between various simulators using IBIS models


> Hi,

>  has anybody done any research or tests into how well the results from
> different SI tools match up when using the same IBIS model to analyse the
> same PCB design?

>  I ask because we get a lot of conflicting feedback about our models from
> users of different tools.
> Haruny Said
> H.A.S. Electronics, Inc.
> 33 Boston Post Rd West
> Suite 270
> Marlborough
> MA 01752

> Email: Harunys@haselect.com
> WWW:   http://www.haselect.com
> Phone: (508) 624 6227
> Fax:   (508) 624 6054


 
From owner-ibis  Tue Feb  3 04:23:10 1998
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From: Andrew Ingraham <Andrew.Ingraham@digital.com>
To: ibis-users@eda.org, ibis@eda.org, "'John Berrie'" <johnb@redac.co.uk>
Subject: RE: Pin to model mapping
Date: Tue, 3 Feb 1998 07:22:02 -0500
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My guess: Either (a) the person who made the IBIS models didn't bother
finding out the true pin/model mapping, leaving it as an "exercise for
the user," or (b) the pinout wasn't fixed when the model was created.

It's a pain in the neck because it can make the model unusable.

Regards,
Andy

 
From owner-ibis  Tue Feb  3 04:01:57 1998
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Date: Tue, 03 Feb 1998 12:09:48 +0000
To: ibis-users@eda.org, ibis@eda.org
From: John Berrie <johnb@redac.co.uk>
Subject: Pin to model mapping

Hello IBISers,
Since we are currently in the process of constructing an IBIS extractor,
it would be really useful if someone could answer the following question:

In some of the IBIS part models on the web site, there is an incomplete
mapping of pins to driver and receiver models.

1. Is this intentional?
2. Is there a default mapping which takes place if a pin within a part
   does not have an eplicit mapping?

One of the parts only had two pin mappings, even though the part has
more than 14 pins, and multiple drivers/receivers (a buffer chip).

Thank you in advance
John

John Berrie
Chief Application Engineer
Dynamic Solutions
Zuken-Redac
Tewkesbury
U.K.

 
From owner-ibis  Tue Feb  3 09:35:45 1998
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To: ibis@eda.org
Subject: EIA IBIS face-to-face meeting minutes 1/26
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 DATE: 2/3/98

 SUBJECT: 1/26/98 EIA IBIS Open Forum Minutes
  
 VOTING MEMBERS AND 1998 PARTICIPANTS LIST:
 AMP                            (Martin Freedman) 
 Applied Simulation Technology  Norio Matsui*, Raj Raghuram*
 Cadence Design & UniCAD        C. Kumar*, Don Telian*, Patrick Riffault*, 
				Craig Lewis*, Greg Fitzgerald*, Paul Galloway*
 Cypress                        (Bruce Wenniger)
 Digital Equipment Corp.        Jeff Chu, Greg Edlund*, Bob Haller*
 Hewlett Packard 
   EEsof                        Karl Kachigan*, Henry Wu*
   Boise                        Paul Gregory*
 High Design Technology         (Razvan Ene)
 HyperLynx                      Kellee Crisafulli*, Matthew Flora*
 Incases                        Olaf Rethmeier, Scott Jacobson*
 Intel Corporation              Stephen Peters*, Arpad Muranyi*, Frank Kern*
   Columbia, SC (formerly NCR)  Dave Moxley
 Mentor Graphics                Mark Noneman* 
   Interconnectix               Bob Ross*
   Zeelan Technology            George Opsahl, Tom Dagostino*
 Mitsubushi                     Tam Cao*
 Motorola                       (Ron Werner)
 National Semiconductor         Syed Huq*, Cheng-Yang Kao*, John Goldie*,
				Ikchang Song*
 NEC                            (Hiroshi Matsumoto)
 Quantic EMC                    (Mike Ventham)
 Texas Instruments              Thomas Fisher*, Harvey Stiegler*,
				Vincent Chang*
 Thomson-CSF/SCTF               (Jean LeBrun)
 Viewlogic                      Jon Powell*, Chris Rokusek* 
 VeriBest                       Ian Dodd*
 VLSI Technology                D.C. Sessions*
 Zuken-Redac                    (John Berrie) 

 OTHER PARTICIPANTS IN 1998:
 Ansoft                         Eric Bogatin*
 Apple                          Fred Floresca*, Danny Itani*
 Apteq Design Systems           Dan FitzPatrick* 
 Compaq                         Shariq Rahman*
 EIA                            Patti Rusher*
 EMC                            Fawn Engelmann*
 Fairchild Semiconductor        Peter LaFlamme*
 NESA                           Edward Sayre*, Kathy Breda*
 North Carolina State U.        (Michael Steer)
 Philips Semiconductor          Todd Andersen*
 Seagate                        Vanessa Howard*
 Symmetry                       Andy Hughes*
 Tektronix                      Nassrin Ghahyasi*
 Ultratest International        Chris O'Connor*
 Xilinx                         Susan Wu*

 In the list above, attendees at the meeting are indicated by *.  Principal
 members or other active members who have not attended are in parentheses.
 Participants who no longer are in the organization are in square brackets.

 Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
 follows:
   
   Date               Bridge Number     Reservation #    Passcode
   February 13, 1998  (916) 356-9200    5-15348          8377869
   Thurday, February 26, 1998  EUROPEAN IBIS SUMMIT - NO BRIDGE
 
 All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
 7 days before each Open Forum and meeting minutes out within 7 days after.  
 When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
 Hobbs and give the reservation number and passcode.
 
 NOTE: "AR" = Action Required.

-------------------------------- MINUTES -------------------------------------

 INTRODUCTIONS AND MEETING QUORUM
 Syed Huq opened the meeting.  Syed asked the officers Syed, Bob Ross, 
 Jon Powell, and Stephen Peters to introduce themselves.  Then all 
 participants introduced themselves and company affiliation.  

 Bob surveyed the attendance and found good representation among users (of
 models and tools), EDA providers and Semiconductor Vendors.  The recorded
 attendance was 49.
 
 Bob also thanked National Semiconductor for their exceptional show of
 support of the EIA IBIS Open Forum for hosting the meeting and to Syed
 Huq for making the arrangements for the meeting and handling the logistics
 of scheduling the presentations.


 MEMBERSHIP UPDATE AND TREASURER'S REPORT
 Patti Rusher handed out invoices for 1998 EIA IBIS Open Forum membership
 to representatives of member companies in attendance.  The rest will be
 mailed directly.  
 
 Bob Ross reported that as a result of an error, Zuken-Redac should have
 been listed as a member company in 1997 and is now listed for 1998.  (The
 participation lists above are now reset to represent 1998 membership and
 participation.)  There should be some revisions as some recent company
 acquisitions and mergers are finalized.


				   PROGRAM

 The program was rearranged to accommodate several presenters and to offer
 a better flow.  The notes below represent the program in the order of
 presentation rather than in the original Agenda.  Copies of the electronic 
 presentations will be stored on eda.org, so the notes below will just
 be brief comments of some main points and related discussions that were
 captured.

 
 STATUS OF EIAJ I/O MODEL STANDARD 
 - Norio Matsui, Applied Simulation Technology
 Bob Ross introduced this presentation indicating that the Chair., Hideki 
 Fukuda, from Hitachi and Chair. of the subgroup could not attend.  He had 
 given a presentation to a small group in April, 1998, so Norio Matsui is 
 giving the report on the I/O Buffer Interface for ICs activity.  Norio 
 stated that Version 1.0 was  completed in January, 1998, and an English 
 translation is under preparation.  Like IBIS, the specification uses table 
 data for transistor descriptions rather than the process parameters.   
 Stimulus expressions for buffers were added.  The specification describes 
 I/O buffers and package models on a more detailed level than IBIS and is 
 used for signal integrity, power integrity and in the future, EMI.  Norio 
 showed examples of ground bounce simulation, reflections, and crosstalk.  
 Applied Simulation Technology processes table spice models and simulation 
 times are as fast as IBIS simulations.  In addition, Avent! is reportedly
 going to re-instate a ibis2spice converter. Future activities involve 
 extensions for EMI, a BGA (Power/Ground Plane) model, and development of 
 tools.

 Bob commented at the end that Fukuda-san had indicated that the English
 translations of Version 1.0 was planned by February 1998, and that a Web 
 site was also planned by March 1998 to give information and background.


 REPORT ON IBIS USER'S FORUM
 - Ed Sayre, Northeast Systems Associates (NESA)
 Ed summarized the three meetings held so far on September 18, 1997 (hosted
 by NESA), December 4, 1997 at Cadence, and January 18, 1998 at Stratus.  Two 
 sub-committees were formed.  Greg Edlund chairs a group on Accuracy and
 Validation, and Paul Galloway on Software Aspects of IBIS.  Greg and Bob 
 Haller have presented their thoughts on IBIS model accuracy, and Paul has
 reported that users are interested in an IBIS to Spice translation.  The
 next meeting is scheduled on Thursday, February 12, 1998 at EMC.  The 
 participants will report back on the IBIS Summit meeting and the sub-
 committees will report on progress.  Ed emphasized that there is strong 
 participation from the East Coast IBIS user community, but will accept help 
 from all over.  Ed also stressed that the communications industry (operating 
 in the GHz region and with fiber optics) is under-represented in IBIS.  The 
 IBIS East group will coordinate its activities with the IBIS Open Forum.


 HYPERLYNX IBIS DEVELOPERS KIT
 - Kellee Chrisafulli, HyperLynx
 Kellee introduced the HyperLynx IBIS Developers Tool Kit to assist in 
 producing better IBIS models and verifying them.  It will be available
 for free to semiconductor vendors who will provide the models to the public
 for free.  It will also be available to others for $4,000.  The Kit consists
 of the (free) Visual IBIS Editor with built in ibischk2+ rules checking,
 a simulator to run IBIS models, pre-built schematics with test loads,
 a schematic editor to create any type of load circuit, and over 800 IBIS
 models to be used as examples.  Plans for future releases include an
 "IBIS Model Wizard" to help you generate models by asking questions about
 output resistance, rise and fall times, etc., and a similar "Package Model
 Wizard" to provide first cut package information.  Kellee expects the 
 product to be available by the end of February, 1998.

 DEVELOPING AN IBIS ACCURACY SPECIFICATION
 - Greg Edlund, Digital Equipment
 Greg indicated that the focus has shifted to accuracy, defined as
 agreement between model prediction and lab measurements.  He chairs a sub-
 committee which intends to produce an accuracy specification by January,
 1999 and is looking for a semiconductor manufacturer to serve as a beta
 site.  The specification would cover relevant model parameters, minimum
 set of test loads, measurement methodology, a comparison metric and a
 characterization report.  Greg defined three levels of model accuracy and
 the comparison metric for AAPE: average absolute percent error.  The
 accuracy statistics would be added to the IBIS model header.
 As part of his presentation, Greg passed around a board they are using
 as a test fixture, along with the schematic.

 This presentation generated a general discussion on accuracy and a number
 of questions. D.C Sessions commented that to do correlation on EVERY model
 in an I/O cell library would be difficult.  Instead, the semi house must
 create a process that works for a few, then apply the process to get
 confidence.  There was some discussion on whether this process should be
 documented as part of the spec. 

 V-T CURVE MODELING
 - C. Kumar, Cadence
 Kumar argued that IBIS Models as currently specified with V/T tables can
 be processed by different algorithms, all satisfying the "golden data".
 He argues that specifying an IBIS model with one I/T curve and one V/T 
 table for 50 ohms terminated to Vcc/2 gives the internal staged switching 
 information to produce unambiguous and accurate results.  Kumar showed
 an example of a staged switch and also showed the assumed equations.  Upon
 questioning, Kumar stated that this specification method would work best for 
 Spice models and would be more difficult for physical devices.  Jon Powell
 argued that V/T curve modeling was still valid, but that the proper loads
 had to be selected -- "the selection of tests loads is not arbitrary".
 
 
 COMPARING THE PERFORMANCE AND ACCURACY OF SPICE AND IBIS MODELS IN HIGH
 FREQUENCY SIMULATION
 - Arpad Muranyi, Intel
 Arpad presented some preliminary results addressing the question of whether
 there is a frequency limit for using IBIS models.  He compared HSPICE models
 and behavioral Spice models for flight time simulation comparisons.  First 
 he established that his comparison was limited by time step resolution
 limitations.  Some suggested that he could have controlled this.  Then he
 showed very good correlation between the simulations under a resistor, 
 capacitor and set of transmission line loads.  He concludes that while
 v2.1 IBIS models are more accurate than v1.1 models, both are accurate to
 within a few pS, and IBIS models are applicable for higher frequency 
 simulations.


 A COMPARISON AND CORRELATION OF RESULTS FOR PHILIPS BICMOS ALVT16244 USING
 HSPICE AND PSTAR (INTERNAL) VERSUS SIMULATED AND MEASURED IBIS MODELS
 - Todd Andersen, Philips
 Todd presented a complete report of a comparison study based on measurement,
 simulation using HyperLynx LineSim, Philips Pstar, and HSPICE.  He showed
 the non-monotonic behavior of the input bus hold circuit.  In general, 
 the comparison of IV data and time simulations were excellent.  


 CORRELATING A SIMULATED MODELS (SPICE2IBIS) TO LAB MEASUREMENTS
 - Patrick Riffault, Cadence
 Patrick presented a methodology for doing a comparison.  An internal test
 board was used which could be populated with different technologies.  The
 process involves correlating the actual IBIS model with physical model
 measurements to adjust the RAMP times and I/V data.  When correlated, the
 measured results are then compared with simulation results.  Patrick's 
 results did show some differences, but there was only a 6% (max) error
 between the predicted and measured overshoot/undershoot .  As a general 
 design process, Patrick recommends using the min and max tables, since the
 IBIS model adjustment is a time consuming process requiring proper equipment.
 
 
 DATA REQUIREMENTS TO BUILD A COMPLETE IBIS MODEL - CADENCE'S MODEL 
 DEVELOPMENT PROCESSES
 - Paul Galloway, Cadence
 Paul presented a process for generating IBIS models from Spice models.  The
 process involves using s2ibis and then comparing the simulations using 
 SigNoise and Spice.  He showed that source data comes from Spice models,
 data sheets, measurements and legacy models.  All sources can be used, and
 he showed a table where keyword parameters are best obtained.  As part of
 the final QA process, he does syntax checking with ibischk, visual 
 inspection and simulation to examine the rising and falling waveforms.
 Paul showed some plots of results which showed excellent correlation.
 
 
 INSPECTING IBIS MODELS
 - Bob Ross, Interconnectix/Mentor Graphics
 Bob indicated that as a goal, IBIS models from commercial sources and
 semiconductor vendors should be plug-in compatible across simulators.
 This is a more stringent requirement than is satisfied with existing Spice
 models which have no standard syntax for I/O buffer models, may be
 different for different Spices, and require user Spice knowledge and
 user re-configuration for the application.  The presentation was concerned 
 with IBIS syntax and construction issues rather than on accuracy issues.
 Similar to Paul Galloway's presentation, Bob presented four areas that
 he checks:  ibischk2+ checking (after converting version 1.1 models to
 [IBIS Ver] 2.1, plotting (to view all the tables), and simulations (for
 amplitude and rise and fall time reality, and inspection of the contents.
 Bob showed some expected plots for CMOS, TTL, ECL and BiCMOS technologies.
 Some problems revealed by the inspection process may also be revealed by
 some of the other steps.  Among the items to be observed or tested are
 required Vinh and Vinl thresholds and values, endpoints of Waveform tables,
 Timing test load information and intersection, and monotonic data.  Typical
 voltage and current points at 0 A and 0 V crossings can be inspected for
 typical technologies.  Clean time responses should exist for the waveform
 tables.  Bob outlined areas of inspection and listed several points under
 each.  The areas included correctness, minimal completeness, correct 
 numerical values, accuracy of information, and relationship with CAE
 algorithms.  Bob also showed some older s2ibis defects which you would look
 for based on information on which s2ibis was used.  Basically, look for both  
 the expected and unexpected.  Many models can be fixed or completed, but 
 Plug-in compatibility should be an objective for commercial quality IBIS 
 models.
 

			      OTHER BUSINESS

 
 COMMERCIAL MODELS AND SERVICES
 At the suggestion of Jon Powell, Bob Ross asked for individuals who have
 commercial offerings to describe briefly what services, products or models
 they are offering.

 John Powell described that he is managing the Viewlogic Consulting Services.
 The service will provide IBIS models to semiconductor vendors and customers
 based on HSPICE or measurement.

 Andy Hughes of Symmetry used to be an IBIS Model provider prior to being
 acquired by Analogy.  Symmetry still supports existing customers.
 
 Tom Dagostino of Zeelan Technology (A Mentor Graphics business) has a 
 library of over 10,000 IBIS Components for sale that are measurement
 based.  Zeelan also will provide libraries in Quad and Cadence formats
 directly.  Zeelan also provides model development services for users
 and semiconductor vendors.

 Paul Galloway introduced the Cadence IBIS Modeling Service for developing
 IBIS Models from Spice models for semiconductor vendors and customers.

 The HyperLynx tool was discussed in the main presentation.  About 800
 IBIS Models are available to customers.

 Chris O'Connor discussed the UltraTest International programmable curve
 tracer which can be configured to automatically extract the IBIS Model
 I/V tables for any set of pins.  
 
 Scott Jacobson mentioned that Incases provides IBIS models through its
 consulting services to customers.

 Bob noted that other commercial IBIS model providers not mentioned above 
 also exist.


 MODEL REVIEW COMMITTEE
 Bob Ross mentioned that an EDA tool vendor IBIS Model Review committee has
 been formed and coordinated by Matthew Flora.  These individuals will be 
 available to review models that are submitted to them from semiconductor
 vendors, commercial vendors, or users, and will provide feedback to the
 originator of the model regarding correctness and how the models performed
 in their simulators.  In that way the model developers will learn about the
 common set of features that need to be supported in addition to learn about
 possible problems in the models common to all.  The members consist of the
 following people:

   Matthew Flora, HyperLynx
   Bob Ross, Interconnectix/Mentor Graphics
   Olaf Rethmeier, Incases
   Chris Rokusek, Viewlogic

 Bob asked for and got additional members:

   Paul Galloway, Cadence
   Ian Dodd, VeriBest
   Jon Powell, Viewlogic


 IBISCHK2.1.15 STATUS
 Bob Ross indicated the ibischk2+ Version 2.1.15 is waiting a fix for BUG21 
 and creation of executables before being posted.  Matthew Flora has sent
 the revised code with BUG20 fixed to Chris Rokusek, and Chris needs to fix
 BUG21 and send the source code to Atul Agarwal and Bob and Matthew.  Chris
 will also send the executables to Bob to be put on eda.org.
 

 IBISCHK3 STATUS
 Bob Ross indicated that 10 companies have committed to the development
 project.  Bob will check whether a few more companies will join.  He expects 
 to decide on issuing invoices at the February 13, 1998 meeting based on 
 commitments at that date.  So far Bob has commitments or payment from the
 following companies:

   Applied Simulation Technology
   Cadence
   Digital Equipment
   HyperLynx
   Incases
   Intel
   Interconnectix/Mentor Graphics
   Mitsubishi Semiconductor 
   National Semiconductor
   Viewlogic

 Bob reported that Atul Agarwal has completed 5 of the eight items.
 He expects to have a Beta Version of the Source Code available by the
 beginning of March, 1998.  Bob will distribute it to the companies who
 have funded the development.  Atul is awaiting ibischk2 Version 2.1.15
 as the new baseline.

 
 S2IBIS2/3
 Bob Ross stated that the spice2ibis project could be turned over to 
 industry to create a commercial product.  Currently, a student, R. Sanjeev,
 also known as Presi is working on improvements.


 VERSION 3.1 OBJECTIVE
 Bob Ross indicated that it would be nice to close out all of the issues
 and vote for ratification of Version 3.1 at the June IBIS Summit meeting
 at the Design Automation Convention.  The ibischk3 development project is
 part of the process to check and stabilize Version 3.1.


 EUROPEAN IBIS SUMMIT
 Bob Ross showed the tentative agenda consisting of 10 presentations to date.
 He indicated good sign up so far, but will send out another notice for
 sign up and additional presentations.  The European IBIS Summit is being
 co-sponsored by Cadence, High Design Technology, and Mentor Graphics and
 will be held on Thursday, February 26, 1998 in Paris, France.


 ADJOURNMENT
 The meeting was adjourned after once again thanking Syed Huq and National
 Semiconductor for taking care of all of the arrangement.

 
 NEXT MEETING:
 The next teleconference meeting is on Friday, February 13, 1998, 8:00 A.M. to 
 9:55 A.M.
 ==============================================================================
                             NOTES
 
 IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
	     bob_ross@mentorg.com
	     Modeling Engineer, Interconnectix BU of Mentor Graphics
	     8005 S.W. Boeckman Road, Wilsonville, OR 97070

 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785
	     huq@rockie.nsc.com
	     Staff Applications Engineer, National Semiconductor, M/S A-2595
	     2900 Semiconductor Drive, Santa Clara, CA 95052
 
 SECRETARY:  Stephen Peters (503) 264-4108, Fax: (503) 264-4515
	     sjpeters@ichips.intel.com
	     Senior Hardware Engineer, Intel Corporation
	     M/S JF1-56
	     2111 NE 25th Ave. 
	     Hillsboro, Oregon 97124-5961

 LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
	     jonp@qdt.com
	     Senior Scientist, Viewlogic (formerly Quad Design)
	     1385 Del Norte Rd., Camarillo, CA 93010
  
 This meeting was conducted in accordance with the EIA Legal Guides and EIA
 Manual of Organization and Procedure.
 
 The following e-mail addresses are used:

   ibis-request@eda.org
       To join, change, or drop from either the IBIS Open Forum Reflector
       (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
       or both.  State your request.

   ibis-info@eda.org
       To obtain general information about IBIS, to ask specific questions
       for individual response, and to inquire about joining the EIA-IBIS
       Open Forum as a full Member.

   ibis@eda.org
       To send a message to the general IBIS Open Forum Reflector.  This
       is used mostly for IBIS Standardization business and future IBIS
       technical enhancements.  Job posting information is not permitted.

   ibis-users@eda.org
       To send a message to the IBIS Users' Group Reflector.  This is 
       used mostly for IBIS clarification, current modeling issues, and
       general user concerns.  Job posting information is not permitted.

   ibischk-bug@eda.org
       To report ibischk2 parser bugs.  The Bug Report Form Resides on
       eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

       To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
       which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, 
       /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
       respectively.

 Information on IBIS technical contents, IBIS participants, and actual
 IBIS models are available on the IBIS Home page found by selecting the
 Electronic Information Group under:

   http://www.eia.org

 Check the pub/ibis directory on eda.org for more information on previous 
 discussions and results.  You can get on via FTP anonymous.
 
 "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for 
 use at trade shows.
 ==============================================================================




--=====================_886403533==_
Content-Type: text/plain; charset="us-ascii"


--=====================_886403533==_--


 
From owner-ibis  Tue Feb  3 15:08:40 1998
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	id PAA03612; Tue, 3 Feb 1998 15:05:43 -0800 (PST)
From: bobr@emicx.mentorg.com (Bob Ross)
Received: by bob (4.1/CF5.23L)
	id AA07929; Tue, 3 Feb 98 15:05:53 PST
Date: Tue, 3 Feb 98 15:05:53 PST
Message-Id: <9802032305.AA07929@bob>
To: atulapt@giascl01.vsnl.net.in, ibischk-bug@eda.org
Subject: Re:  Series enhancement queries
Cc: ibis@eda.org

Atul:

My response is below and also copied to the IBIS reflector for
information.

Best Regards,
Bob




> From: "APT SOFTWARE AVENUES PVT.LTD" <atulapt@giascl01.vsnl.net.in>
> Reply-To: "APT SOFTWARE AVENUES PVT.LTD" <atulapt@giascl01.vsnl.net.in>
> To: Bob Ross <bobr>
> Subject: Re:  Series enhancement queries


> Hello Bob,

> With respect to your reply below, I want to make sure about the following
> which was my original intent of asking you the question.

> Any keyword, which is allowable for Series_MOSFET, can be specified twice,
> both under [On] and [Off], if the model developer wants that keyword to be
> meaningful in both the on and off states. For example, the [Voltage Range]
> keyword can be specified twice if the model developer wants different
> voltage ranges for on and off states. Similary for [Temperature Range]
> and all other keywords which are allowable.
>  

The [Voltage Range] or any power reference voltage and [Temperature Range]
keywords should appear only once and above the [On] and [Off] keywords.


> > > b) For the keywords above which are allowable for Series_switch, do they
> > > need to be specified twice, both under [On] and [Off] keywords if a user
> > > wants them to be meaningful both under the on and off states ?
> > 
> > Both [On] and [Off] should be required.  The both must be filled with
> > a meaningful entry (see below).  The keywords used under [On] could be
> > different than used under [Off].  For example the series switch sample
> > under eda.org/pup/ibis/samples/ver3.0/cbt.ibs  uses [Series MOSFET]
> > for the [On] model and [R Series] for a high impedance [Off] model.
> > 
> > 




 
From owner-ibis  Tue Feb  3 15:23:37 1998
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	id PAA03756; Tue, 3 Feb 1998 15:20:46 -0800 (PST)
From: bobr@emicx.mentorg.com (Bob Ross)
Received: by bob (4.1/CF5.23L)
	id AA07932; Tue, 3 Feb 98 15:20:57 PST
Date: Tue, 3 Feb 98 15:20:57 PST
Message-Id: <9802032320.AA07932@bob>
To: atulapt@giascl01.vsnl.net.in, ibischk-bug@eda.org
Subject: Re:  Model Selector
Cc: ibis@eda.org

Atul:

You have a valid point.  I change my position.  [Model Selector]
should exist at the file scope to be consistent with the fact that
[Model]s exist at the file scope.  If we had restricted the
[Model Selector] to be constrained to a [Component] scope, then
we could have allowed two [Model Selector]s with the same name to
exist under different [Component]s.  This could be very confusing.
So like [Model]s, only unique names for [Model Selector] can
exist in a .ibs file.  Thank you for pushing back on this point.
This is being copied to the IBIS reflector for information.

Best Regards,
Bob


> Date: Tue, 3 Feb 1998 12:06:33 +0000 (GMT)
> From: "APT SOFTWARE AVENUES PVT.LTD" <atulapt@giascl01.vsnl.net.in>
> To: Bob Ross <bobr>
> Subject: Model Selector

> Hello Bob

>     Just to argue further, every model selector has a unique
> name associated with it.  So there is nothing to prevent multiple
> model selectors from being defined at the file scope. If we make
> model selectors component scope, then we preclude the possibility
> of sharing the same model selector among multiple components( as
> we do with models).

>     I must confess that my vehement arguments for making the model
> selector file scope are biased by the fact that I have already 
> implemented them such, but it would not be very difficult
> to make them component scope should you remain unconvinced :-)

> Regards

> atul

> > 
> > > 1) In the IBIS Tree diagram for Version 3.0 (which you had
> > > given me), the [Model Selector] keyword is indicated within
> > > the [Component] scope. Now, a model selector is nothing
> > > but a "stand-in" for a model and models are defined at file
> > > scope. By this logic, shouldn't a [Model Selector] be at the
> > > file scope also ?
> > 
> > In my opinion the scope of [Model Selector] should remain under
> > [Component], just as shown in the Tree diagram.  This allows a
> > different [Component] in the same file which will access similar
> > models to have a different default model and different configurations.
> > For example, a different component may not offer a reduced set of
> > selections since one of the pins controling the selection may be NC.
> > 




 
From owner-ibis  Thu Feb  5 16:06:43 1998
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Date: Thu, 5 Feb 98 16:06:15 PST
From: huq@rockie.nsc.com (Syed Huq)
Message-Id: <9802060006.AA29196@rockie.nsc.com>
To: ibis@vhdl.org
Subject: IBIS Jan98 Summit softcopy on vhdl.org

Hi,

The softcopies of the IBIS summit98 that are available have been
placed on the anonymous ftp site at vhdl.org for downloading 
under the following sub-dir

/pub/ibis/summits/jan98

Below is the content of the '00readme.txt' file that explains
the files available for download.

00readme.txt:

IBIS Summit98 -  Jan26th 1998
Santa Clara, CA
------------------------------

The 'zip' files are WinZip'ed using ver6.2. Most of the papers are
Powerpoint presentations on Win95


Cadence.zip : "Correlating a Simulated Model (Spice2IBIS) to Lab
               Measurements" - Patrick Riffault (Cadence)
               (Powerpoint presentation with notes)

digital.zip : "Developing an IBIS Model Quality Specification"
               Greg Edlund (Digital)
               (Powerpoint presentation)

hyperlynx.zip:"A New IBIS Development Tool Kit"
               Kellee Crisafulli (Hyperlynx)
               (Powerpoint presentation)

icxjan98.zip: "Inspecting IBIS Models"
               Bob Ross (Interconnectix/Mentor Graphics)
               (Powerpoint presentation) 

nesa.ppt:     "The IBIS User's Group Objective and Program"
               Ed Sayre (NESA)
	       (Powerpoint presentation)
              
cpkibis98.tar "Probelms in V-T Curve Modeling and Simulation"
               C. Kumar (Cadence)
               (Unix tar file and will explode into html and gif
               format files of each slides)

m012698.txt   Meeting minutes of the Jan26th Summit in text format.


Regards,
Syed
Vice-Chair ANSI/EIA-656 (IBIS)
National Semiconductor Corp.
 
From owner-ibis  Fri Feb  6 11:48:03 1998
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From: bobr@emicx.mentorg.com (Bob Ross)
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	id AA11216; Fri, 6 Feb 98 11:45:32 PST
Date: Fri, 6 Feb 98 11:45:32 PST
Message-Id: <9802061945.AA11216@bob>
To: ibis@eda.org
Subject: IBIS MEETING FEBRUARY 13, 1998

                       IBIS Open Forum Meeting Agenda 
                                for 2/13/98

                  Bridge Number    Reservation #   Passcode
                  (916) 356-9200   5-15348         8377869
   

 All meetings are 8:00 AM to 9:55 AM Pacific Time.  When you call into the 
 meeting, ask for the IBIS Open Forum hosted by Will Hobbs and give the
 Reservation Number and Passcode.
 
 8:00 Check-In, Intros, Announcements                         Ross

      - Intros of New IBIS Participants, Meeting Quorum       Ross
      - Membership Update and Treasurers Report               Rusher
      - Review of Previous Meeting's Minutes (and ARs)        Peters
      - Miscellany/Announcements                              All
      - Press & Web Page Updates                              Huq, All
      - New Models Available, Library Update                  Powell, All
      - Opens for New Issues                                  All

 8:25 Administrative and Project Discussions

      New Year General Administrative Comments                Ross

      International Progress                                  Rusher/Ross
      - IEC 62014-1 (IBIS Version 2.1)
      - EIAJ III (I/O Interface Model for ICs)
      - IBIS and EMC Simulation

      IBIS East Meeting                                       Ross

      DesignCon98 IBIS Summit Meeting Review                  Huq

      DesignCon98 Review                                      Ross

      DATE98 (Design Automation and Test in Europe -          Ross
              formerly EuroDAC)
      - IBIS Summit
      - PCB Symposium

      s2ibis for NT Status                                    Dodd/Wiens

      Editing Committee                                       Ross/Peters

      BIRD44 - Interpretation of Min/Max/Weak/Strong Data     Ross
               Vote?

      IBISCHK2+ (Ver 2.115) PROGRESS                          Flora/Rokusek

      BUG22 - Empty [Rising Waveform] or Empty                Ross
              [Falling Waveform] Causes Crash

      Version 3.1 Parser Development                          Ross/Peters
      - Funding
      - Test Matrix
      - Samples

      Cookbook Status                                         Peters
      - Examples

      New Administrative Issues                               All

 9:15 Technical Discussion

      BIRD42.3 - Modeling Current Waveforms                   Kumar/Ross

      BIRD45.1 - Dynamic Clamps                               Orhanovic/Muranyi

      BIRD46 - Relaxation of Some IBIS Model File Name        Flora
               Restrictions

      New Technical Issues                                    All

 9:50 Wrap Up and Next Meetings Plans                         Ross

 9:55 Sign Off
 







 
From owner-ibis  Mon Feb 16 18:18:19 1998
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Message-ID: <91A98A376577D1118ADF0000B441F5D6011C47@exchange3.via.com.tw>
From: Weber Chuang <WeberChuang@via.com.tw>
To: ibis@eda.org
Subject: Dual curve characteristic for input pad
Date: Tue, 17 Feb 1998 10:21:36 +0800
X-Priority: 3
MIME-Version: 1.0
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</HEAD>
<BODY>
<P><FONT COLOR=3D"#0000FF" SIZE=3D1>Dear IBISers,</FONT>
<BR>
<BR><FONT COLOR=3D"#0000FF" SIZE=3D1>&nbsp;&nbsp; I am currently =
involved in the design of a I/O pad and building IBIS for it, but I am =
facing some troubles, my I/O pad has dual I/V curves while in input =
mode, that is, the I/V curves for rising input and falling input&nbsp; =
are different. IBIS seems to not supporting this kind of design, and =
s2ibis2 will not generate correct model for this. Is there any =
workaround? Any comment is welcome.</FONT></P>
<BR>
<P><FONT SIZE=3D1>Best Regards</FONT>
<BR>
<BR><FONT SIZE=3D1>Weber Chuang(ChingFu Chuang)</FONT>
<BR><FONT SIZE=3D1>SI Engineer, System Team.</FONT>
<BR><FONT SIZE=3D1>VIA Technologies, Inc.</FONT>
<BR><FONT SIZE=3D1>Taipei, Taiwan, ROC </FONT>
<BR>
<BR>
<BR>
</P>

</BODY>
</HTML>
 
From owner-ibis  Mon Feb 16 18:55:09 1998
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From: Weber Chuang <WeberChuang@via.com.tw>
To: "'ibis@eda.org'" <ibis@eda.org>
Subject: dual curve issue for input pad
Date: Tue, 17 Feb 1998 10:58:29 +0800
X-Priority: 3
MIME-Version: 1.0
X-Mailer: Internet Mail Service (5.0.1457.3)
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Dear IBISers, 

    I resend this mail because the previous one seem to have some
problems.

    I am currently involved in the design of a I/O pad and building IBIS
for it, but I am facing some troubles, my I/O
pad has dual I/V curves while in input mode, that is, the I/V curves for
rising input and falling input  are
different. IBIS seems to not supporting this kind of design, and s2ibis2
will not generate correct model for this. Is
there any workaround? Any comment is welcome.

Best Regards

Weber Chuang(ChingFu Chuang)
SI Engineer, System Team.
VIA Technologies, Inc.
Taipei, Taiwan, ROC 

 
From owner-ibis  Wed Feb 18 08:44:53 1998
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From: Andrew Ingraham <Andrew.Ingraham@digital.com>
To: "'ibis@eda.org'" <ibis@eda.org>,
        "'Weber Chuang'"
	 <WeberChuang@via.com.tw>
Subject: RE: dual curve issue for input pad
Date: Wed, 18 Feb 1998 11:41:51 -0500
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Content-Type: text/plain

Weber Chuang wrote:

>     I am currently involved in the design of a I/O pad and building
IBIS
> for it, but I am facing some troubles, my I/O
> pad has dual I/V curves while in input mode, that is, the I/V curves
for
> rising input and falling input  are
> different. IBIS seems to not supporting this kind of design, and
s2ibis2
> will not generate correct model for this. Is
> there any workaround? Any comment is welcome.

Are you talking about a hysteresis-like feedback characteristic, such as
a bus-hold circuit?

If so, IBIS doesn't do it.  Both because it doesn't handle input I/V
curves that change, and because bus-hold input curves are non-monotonic
which can create problems for the simulator.

(Someone correct me if I'm wrong or if version 3 changes this.)

Regards,
Andy Ingraham

 
From owner-ibis  Thu Feb 19 14:13:06 1998
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Subject: AGENDA EUROPEAN IBIS SUMMIT 2/26/98
Cc: bobr@emicx.mentorg.com

                    AGENDA EUROPEAN IBIS SUMMIT MEETING
                         Concorde-Lafayette Hotel
                              Paris, France
			    February 26, 1998

 8:30   REFRESHMENTS

 9:00   Welcome, IBIS Activities
        Bob Ross, Interconnectix/Mentor Graphics, USA 
       
 9:25   IBIS Users Group
        Paul Galloway, Cadence, USA

 9:45   Use of IBIS in Alcatel
        John Fitzpatrick, Alcatel, France

 10:25  IBIS Model Development at National Semiconductor Corporation
        Syed Huq, National Semiconductor, USA
 
 10:45  BREAK

 11:00  IBIS Models, Spice vs. Measurement
        Tom Dagostino, Zeelan Technology/Mentor Graphics, USA
 
 11:30  Required IBIS Enhancements
        Gerald Bannert, Siemens, Germany
	       
 12:00  Challenges in Using IBIS in High Frequency Applications
        Prakash Radhakrishnan, Intel, USA                  

 12:30  LUNCH

 13:30  IBIS Models and EMC Simulation Standardization Status
        Christian Marot, Siemens, France
                         
 14:00  Future Component Characterization for EMI Analysis
        Werner Rissiek, Incases, Germany

 14:30  IBIS Models for EMC and High-Frequency Devices
        Razvan Ene, High Design Technology, Italy

 15:15  BREAK

 15:30  SI-Analysis with HSPICE Based on IBIS Behavioral Models
        Bernhard Unger, Siemens, Germany

 16:00  Problems in V-T Curve Modeling and Simulation
        C. Kumar, Cadence, USA

 16:30  BIRD42.3 Algorithm Considerations
        Bob Ross, Interconnectix/Mentor Graphics, USA

 16:45  GROUP DISCUSSION
        Technical Comments
        IBIS Usage Comments
        Questions About the EIA IBIS Open Forum
        Forming a European IBIS Users Group

 17:00  ADJOURN

 
From owner-ibis  Fri Feb 20 09:22:30 1998
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Subject: IBIS Open Forum Minutes 2/13
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Date: Fri, 20 Feb 1998 09:18:41 -0800
From: Stephen Peters <sjpeters@ichips.intel.com>



 DATE: 2/20/98

 SUBJECT: 2/13/98 EIA IBIS Open Forum Minutes
   
 VOTING MEMBERS AND 1998 PARTICIPANTS LIST:
 AMP                            (Martin Freedman) 
 Applied Simulation Technology  Norio Matsui, Raj Raghuram*
 Cadence Design & UniCAD        C. Kumar, Don Telian, Patrick Riffault, 
				Craig Lewis, Greg Fitzgerald, Paul Galloway
 Cypress                        (Bruce Wenniger)
 Digital Equipment Corp.        Jeff Chu*, Greg Edlund*, Bob Haller
 Hewlett Packard 
   EEsof                        Karl Kachigan, Henry Wu
   Boise                        Paul Gregory
 High Design Technology         (Razvan Ene)
 HyperLynx                      Kellee Crisafulli, Matthew Flora*
 Incases                        Olaf Rethmeier, Scott Jacobson
 Intel Corporation              Stephen Peters*, Arpad Muranyi*, Frank Kern
   Columbia, SC (formerly NCR)  Dave Moxley*
 Mentor Graphics                Mark Noneman
   Interconnectix               Bob Ross*
   Zeelan Technology            George Opsahl, Tom Dagostino
 Mitsubishi                     Tam Cao
 Motorola                       (Ron Werner)
 National Semiconductor         Syed Huq*, Cheng-Yang Kao, John Goldie,
				Ikchang Song
 NEC                            (Hiroshi Matsumoto)
 Quantic EMC                    (Mike Ventham)
 Texas Instruments              Thomas Fisher, Harvey Stiegler,
				Vincent Chang
 Thomson-CSF/SCTF               (Jean LeBrun)
 Viewlogic                      Jon Powell, Chris Rokusek* 
 VeriBest                       Ian Dodd
 VLSI Technology                D.C. Sessions
 Zuken-Redac                    (John Berrie) 

 OTHER PARTICIPANTS IN 1998:
 Ansoft                         Eric Bogatin
 Apple                          Fred Floresca, Danny Itani
 Apteq Design Systems           Dan FitzPatrick 
 Compaq                         Shariq Rahma
 EIA                            Patti Rusher
 EMC                            Fawn Engelmann
 Fairchild Semiconductor        Peter LaFlamme
 NESA                           Edward Sayre, Kathy Breda
 North Carolina State U.        (Michael Steer)
 Philips Semiconductor          Todd Andersen*
 Seagate                        Vanessa Howard
 Symmetry                       Andy Hughes
 Tektronix                      Nassrin Ghahyasi
 Ultratest International        Chris O'Connor
 Xilinx                         Susan Wu

 In the list above, attendees at the meeting are indicated by *.  Principal
 members or other active members who have not attended are in parentheses.
 Participants who no longer are in the organization are in square brackets.

 Upcoming Meetings:  The bridge numbers for future IBIS teleconferences are as
 follows:
   
   Date               Bridge Number     Reservation #    Passcode
   February 26, 1998   EUROPEAN EIA IBIS SUMMIT - NO BRIDGE
   March 13, 1998     (916) 356-9200    5-23353          2913463


 
 All meetings are 8:00 AM to 9:55 AM Pacific Time.  We try to have agendas out 
 7 days before each Open Forum and meeting minutes out within 7 days after.  
 When you call into the meeting, ask for the IBIS Open Forum hosted by Will 
 Hobbs and give the reservation number and passcode.
 
 NOTE: "AR" = Action Required.

 -------------------------------- MINUTES -------------------------------------

 INTRODUCTIONS AND MEETING QUORUM
 No new participants.


 MEMBERSHIP UPDATE AND TREASURER'S REPORT
 No report.  Bob Ross mentioned that Patti Rusher had issued invoices to
 attendees at the EIA IBIS Open Forum Meeting on January 26, 1998


 REVIEW OF MINUTES AND AR'S
 Bob Ross has done minor editorial spelling correction on some previous
 minutes.  The Mitsubishi name is corrected in the January 26, 1998 Minutes.


 MISCELLANY/ANNOUNCEMENTS
 Bob Ross indicated that he still plans the Majordomo conversion when he has
 time.  In the last few days there was intermittent ftp access to eda.org due
 to a hacker attack and security hole.  This has been resolved.

 Matthew Flora announced that a new version of the IBIS Visual Editor will
 be made available as soon as the HyperLynx system administrator uploads it.
 It has minor corrections and an updated version of ibischk2+.


 PRESS AND WEB PAGE UPDATES
 Syed Huq reported that the Digital logo and links are on the Poster page of 
the
 EIA IBIS Home Page.  The Model Provider Link was removed since the list is not
 being maintained.

 Bob Ross reported that he will present "IBIS Modeling Tips and Advances" at 
the
 PCB Design Conference West in Santa Clara, March 23-26, 1998.


 NEW MODELS AVAILABLE, LIBRARY UPDATE
 None reported.


 OPENS FOR NEW ISSUES
 Bob Ross on BUG23 - An Empty [Pullup], [Pulldown] with Waveform Table Crashes
 Stephen Peters on the Model Review Committee 


 INTERNATIONAL PROGRESS

 - IEC 62014-1 (IBIS Version 2.1) - Bob Ross reported that he has no new 
   information on the status. 

 - EIAJ III (I/O Interface Model for ICs) - Bob reported that the EIAJ
   subcommittee plans to have a web site in early March with access to 
   Version 1.0 of the document, which is being translated into English.

 - IBIS and EMC Simulation - Bob reported that a meeting of national experts
   has been set up in Paris on Friday, February 27, 1998.  Bob is the US
   representative.  Other national representatives are invited from England,
   France, Germany, Denmark, and Italy.  This meeting is conducted under
   IEC TC93/WG5.  The French group will make a report at the European IBIS
   Summit on IBIS Models and EMC Simulation Standardization Status.

  
 IBIS EAST MEETING
 Greg Edlund reported on the IBIS User's Group meeting held Thursday, February
 12, 1998 at EMC.  The DesignCon EIA IBIS Summit Meeting was reviewed.  Greg
 also mentioned that Paul Galloway has been giving brief tutorials on IBIS
 keywords.  The IBIS East committee is working on establishing a Web Site
 for material they are collecting.   One participant suggested that a one-day
 crash course on IBIS would be useful.  Ed Sayre would be interested in setting
 up such a course and would have others contribute to it.  Stephen Peters and
 others expressed interest in such a course.  The next meeting is scheduled
 on Thursday, March 19, 1998 for 3 PM to 5 PM.


 DESIGNCON98 IBIS SUMMIT
 The EIA IBIS Summit Meeting was held on Monday, January 26, 1998 at the 
 Santa Clara Convention Center and just before the DesignCon show.  Syed Huq
 reported that many of the presentations at the EIA IBIS Summit have been
 uploaded on eda.org/pub/ibis/summits/jan98.  The Summit was very successful
 with 49 people attending and with many good presentations.

 Bob Ross thanked Syed for handling the arrangements and National Semiconductor
 for sponsoring the meeting.


 DESIGNCON98
 The DesignCon presentations on Tuesday, January 27, 1998 in the Signal
 Integrity track involved IBIS model issues.  These were well attended.  Syed
 reported that the panel on How Good are IBIS Models? turned out well.  The
 moderator, Jim Lipmann of EDN Magazine, did not have to ask any questions,
 and the question/answer session continued even after Jim left.

 Bob noted that Greg Edlund and Bob Haller of Digital (along with Mentor
 Graphics for sponsoring the booth) got the best Demo Booth Award at the show.

 Bob also noted that Margery Conner of the DesignCon98 committee was very
 helpful in working with us and getting IBIS listed as a DesignCon98 sponsor.


 DATE98 (DESIGN AUTOMATION AND TEST IN EUROPE) IBIS SUMMIT
 The DATE98 Conference will be held Monday thru Thursday, February 23-26, 1998
 in Paris France.  Several IBIS and PCB Design related activities are 
 scheduled.
 
 The DATE Conference itself is the continuation of EuroDAC (with EuroVHDL)
 and ED&TC (EDAC, ETC, and EuroASIC).  More information is available at:

   http://www.date-conference.com


 - PCB Symposium - Wednesday, February 25, 1998
 Bob Ross reported that seven EDA companies (Cadence, Incases, Mentor
 Graphics, VeriBest, Viewlogic, Xynetix, and Zuken-Redac) are co-sponsors of
 a vender-neutral (i.e., no product promotion), informative, all-day event.  
 Bob outlined the currently planned program which is scheduled from 10:00 AM 
 to 4:00 PM:

   10:00: Opening Address, Lutz Treutler of the FED
   10:15: Viewlogic, Guy DeBurgh
   10:45: Mentor Graphics, Bob Ross
   11:15: Xynetix, Andrew Jones 
   11:45: Incases, Torsten Maeser and Werner Rissiek
   12:15: Buffet Luncheon
   1:30:  VeriBest, David Weins
   2:00:  Cadence, Paul Galloway
   2:30:  Zuken-Redac, Anthony Cutler
   3:00:  Round Table Discussion

 The Round Table Discussion will have representatives from several EDA 
 companies and also former EIA IBIS Open Forum Chair.  Will Hobbs.  


 - European IBIS Summit - Thursday, February 26, 1998
 Bob reported that about 41 people have signed up so far, and he is looking
 for about 45 to 50.  The meeting is hosted by Cadence. High Design Technology,
 (HDT) and Mentor Graphics.  There are about 14 possible presentations.  Bob
 presented a tentative schedule, and the one shown below with updates after
 the meeting is still tentative.  Some last minute confirmations are still
 needed.

			      PRELIMINARY AGENDA
			 EUROPEAN IBIS SUMMIT MEETING
			      February 26, 1998
				Paris, France

 8:30   REFRESHMENTS

 9:00   Welcome, IBIS Activities
        Bob Ross, Interconnectix/Mentor Graphics, USA 
       
 9:25   IBIS Users Group
        Paul Galloway, Cadence, USA

 9:45   Use of IBIS in Alcatel
        John Fitzpatrick, Alcatel, France

 10:25  IBIS Model Development at National Semiconductor Corporation
        Syed Huq, National Semiconductor, USA
 
 10:45  BREAK

 11:00  IBIS, Measurements vs Spice
        Tom Dagostino, Zeelan Technology/Mentor Graphics, USA
 
 11:30  Required IBIS Enhancements
        Gerald Bannert, Siemens, Germany
	       
 12:00  Challenges in Using IBIS in High Frequency Applications
        Prakash Radhakrishnan, Intel, USA                  

 12:30  LUNCH

 13:30  IBIS Models and EMC Simulation Standardization Status
        Christian Marot, Siemens, France

 14:00  IBIS and Radiation Analysis (Incases)
        Werner Rissiek, Incases, Germany

 14:30  IBIS Models for EMC and High-Frequency Devices
        Razvan Ene, High Design Technology, Italy

 15:15  BREAK

 15:30  SI-Analysis with HSPICE Based on IBIS Behavioral Models
        Bernhard Unger, Siemens, Germany

 16:00  Problems in V-T Curve Modeling and Simulation
        C. Kumar, Cadence, USA

 16:30  BIRD42.3 Algorithm Considerations
        Bob Ross, Interconnectix/Mentor Graphics, USA

 16:45  GROUP DISCUSSION
        Technical Comments
        IBIS Usage Comments
        Questions About the EIA IBIS Open Forum
        Forming a European IBIS Users Group

 17:00  ADJOURN


 S2IBIS2
 Bob Ross mentioned that the VeriBest AR for an NT version of s2ibis2 is
 dropped because VeriBest cannot commit someone to do this as originally
 planned.  Bob asked Matthew Flora if he would check whether HyperLynx would be
 interested in the doing the conversion.  Bob also mentioned that another
 person that may be willing to make public his implementation. 


 EDITING COMMITTEE
 Bob Ross reported that he still plans to put an unofficial IBIS ver3_1b.ibs
 update in the  /pub/ibis/wip directory of eda.org to correct some editorial
 errors and also to deal with the [End Electrical Description] and [End Board
 Description] nomenclature inconsistency and other issues reported by Atul
 Agarwal.

 The BNF AR remains.

 AR - Bob Ross generate and post a BNF for IBIS Version 3.0 (and IBIS Version
 3.0 ratification AR).


 BIRD44 - INTERPRETATION OF MIN/MAX/WEAK/STRONG DATA
 Bob Ross opened the discussion on BIRD44 which was submitted just prior to
 the June 1997 IBIS Summit meeting by Andy Ingraham.  BIRD44 proposes 
 changing the min and max column headings for certain keywords to slow/weak
 and fast/strong for IV tables and [Temperature Range], and also to slow and
 fast for [Ramp] and Waveform tables.  This would apply only to the comment
 lines that are used for column headings and to any related discussion in the 
 Specification.

 After a general discussion at the last teleconference meeting, Bob listed
 options for IBIS Version 3.1 implementation.  These included (1) reject (do
 nothing), (2) add a note (which most did not favor), (3) adopt, (4) adopt
 with revision such as standardizing on just slow/weak and strong/fast for all
 of the revised headings to show correlation, and (5) adopt with a combined
 syntax such as min-slow/weak, max-fast/strong for maximum consistency.

 The group discussed and reviewed the options and favored pursuing (4).  Bob
 also wanted BIRD44 to include the additional Version 3.0 keywords and sub-
 parameters that might be changed since BIRD44 was written before Version 3.0
 ratification and discussed only Version 2.1 keywords and subparameters.  The
 committee would need agreement on how the changes apply to all of the Version
 3.0 keywords and subparameters before asking for a vote.

 Bob suggested that he ask the author, Andy Ingraham, to make the changes.

 AR - Bob Ross request Andy Ingraham to issue BIRD44.1 with the changes noted
 above.  [Done]


 IBISCHK2+ (VER 2.115) PROGRESS
 Matthew Flora and Chris Rokusek reported that ibischk2+ Version 2.1.15 
 which incorporated BUG20 and BUG21 fixes was completed and its executables
 were put on eda.org/pub/ibis/ibischk2+.  Matthew asked Bob Ross if the DOS32
 executable was posted, and Bob confirmed that it was, but forgot to send out
 a notice.  So the AR regarding posting ibischk2+ Version 2.1.15 was completed.


 BUG22 - Empty [Rising Waveform] of [Falling Waveform] Causes Crash
 BUG23 - An Empty [Pullup], [Pulldown] with Waveform Table Crashes
 BUG22 and BUG23 were discussed together.  Atul Agarwal reported these
 crashes.  Matthew Flora stated that BUG22 was similar to BUG10 and that
 the fix was easy.  Similarly, Chris Rokusek knew how to fix BUG23.  

 Bob Ross classified both these BUGs as Severe and Medium because they both
 relate to ibischk2+ crashes.  Bob also noted that these BUGs have appeared
 in the ibischk2 Version 2.1.11 release, so they have been in the system for
 a long time.  Such as set of fixes would go into ibischk2+ Version 2.1.16.
 Chris suggested that the executables for Version 2.1.16 be done in several
 months since the process of generating executable is time consuming.  Also
 other new bugs may need to be corrected in this release.

 However, the solutions to the problems need to be communicated to Atul to
 be put into the ibischk3 code.

 So the action is for Matthew to communicate the solution to BUG22 to Atul,
 and Chris to communicate the solution to BUG23.  Both will maintain an
 updated pending ibischk2+ Version 2.1.16, but will not issue executables
 at this time.

 AR - Matthew Flora and Chris Rokusek communicate the fixes to Atul Agarwal
 for BUG22 and BUG23.  [Done]


 VERSION 3.1 PARSER DEVELOPMENT
 Bob Ross got commitments from Hewlett-Packard EEsof and VeriBest to join
 the ibischk3 funding activity.  With 12 companies that makes the per company
 price $2084. 

 The committee by unanimous vote approved issuing $2084 invoices against the
 purchase orders.

 Syed Huq suggested that the two companies which already issued checks at
 $2500 be handled on an individual basis - such as credit the excess against
 future expenses.  Bob would also approve issuing a refund, if requested.

 Bob listed the twelve companies which are joining the funding effort:

   Applied Simulation Technology
   Cadence
   Digital Equipment
   Hewlett-Packard EEsof
   HyperLynx
   Incases
   Intel
   Interconnectix/Mentor Graphics
   Mitsubishi Semiconductor 
   National Semiconductor
   Viewlogic
   VeriBest

 Bob had no further status on the ibischk3 development and still expects
 the first release in early March.  Bob still expects to incorporate the
 editorial corrections based on ibischk-bug@eda.org reflector activity
 concerning ambiguities.  One fix is to change [End Board Description] to
 [End Electrical Description].  This correction would be put in the unofficial
 ver3_1b.ibs document.


 COOKBOOK
 No report, all the ARs are carried forward.

 AR - The following people have volunteered to supply examples
  Steve Kaufer/Hyperlynx -- Example 1 (Version 1.1 basic model)
  Arpad Muranyi - Example 2
  Stephen Peters - Example 3 

 AR - Syed Huq.  Review and expand (if necessary) Section 3.3. on "Obtaining
 I/V and Switching Information via Lab Measurement".


 IBIS MODEL REVIEW COMMITTEE DISCUSSION
 This discussion occurred after the BIRD42.3 discussion but is listed here
 as an Administrative topic.  Bob Ross reviewed that the committee was formed
 at the January 9, 1998 meeting.  Its function was to provide IBIS model
 developers feedback from EDA tool. The goal was to communicate to the IBIS
 developers how the model functioned and what are some of the critical 
 practices and preferred options.  One original option was for the IBIS
 committee to create a one day IBIS model development course.  However, the
 committee members could not commit the time to do such a project.  So the
 original committee with four members was formed at the meeting, and three
 more were added at the January 26, 1998 meeting.

 The complete committee along with their e-mail addresses are listed below:

   Matthew Flora, HyperLynx                   mbflora@hyperlynx.com
   Bob Ross, Interconnectix/Mentor Graphics   bob_ross@mentorg.com
   Olaf Rethmeier, Incases                    orethmeier@pad.incases.com
   Chris Rokusek, Viewlogic                   crokusek@qdt.com
   Paul Galloway, Cadence                     pgjr@cadence.com
   Ian Dodd, VeriBest                         idodd@veribest.com
   Jon Powell, Viewlogic                      jonp@qdt.com

 Bob asked how the committee should proceed.  Chris Rokusek suggested some
 method of central distribution such as a Web site where an IBIS model
 developer could issue a model and it would automatically be distributed to
 the committee.  Matthew Flora volunteered to be the focal point for such
 distribution.  At this time he would distribute IBIS models to the other
 members.  If the company required individual company agreements, such as
 NDA documents or Intel CITR documents, then this requirement would be
 distributed by Matthew.  This mechanism complied with Chris' intent.  So
 Matthew is the focal point for providing IBIS model review.

 The reviewers would provide feedback directly to the model provider.  The
 model provider might then learn of important features needed by EDA tools
 which use IBIS models.  Syed Huq questioned how long the feedback would
 take, and Bob stated that on a time available basis he expected the feedback
 to take several days or more.


 BIRD42.3 - MODELING CURRENT WAVEFORMS
 Bob Ross indicated that BIRD42.3 will be discussed in presentations by
 C. Kumar and by Bob at the European IBIS Summit.  Bob indicated that there
 are two fundamental reasons given for BIRD42.3: Data for another IBIS
 processing algorithm and data for correction currents.


 BIRD45 - DYNAMIC CLAMPS
 Arpad Muranyi reported that he still needs to investigate incorporating the
 dynamic clamp tables into the [Driver Selection] mechanism.  He still needs
 to work with Neven Orhanovic on this issue.
 

 BIRD46 - RELAXATION OF SOME IBIS FILE NAME RESTRICTIONS
 Matthew Flora continued the BIRD46 discussion that was started at the
 January 9, 1998 meeting.  BIRD46 allows the total <filename>.ibs to be
 expanded to 64 characters.  It is currently limited by the original DOS
 convention of 8.3.  So the <filename> could contain 60 characters.

 A concern was raised that the DOS limitation might still exist in Windows NT 
 Version 3.5.1 but subsequent e-mail argued that this limitation did not
 exist.
 
 Bob Ross had stated for consistency that a change made for the .ibs files 
 should also apply to the .pkg and .ebd files in IBIS Version 3.0.  Todd
 Andersen asked where .pkg and its limit was documented.  Bob found some
 references in the IBIS Version 3.0 document.  The other formats refer to
 complying to the <filename>.ibs or <filename>.pkg or <filename>.ebd file
 naming conventions.  Rule 3 of the General Syntax Rules and Guidelines
 Section states that the filename must not exceed 8 characters in order to
 conform with DOS rules.
 
 Arpad Murany asked if the 64 character extension would cause the [Filename]
 keyword to exceed the 80 character line limit.  Bob was concerned that the 
 [Reference Designator Map] keyword has three columns consisting of the 
 reference designator, the file name and component name.  Since the component
 name can have 20 characters, Bob suggested that <filename> be limited to
 20 characters.  This would give naming flexibility without encouraging
 excessively long names.  Greg Edlund asked if the underline character "_", 
 character can be used in the name, and Matthew responded that it was already
 allowed.
 
 The general action item is for Matthew Flora to take this discussion into
 account and issue BIRD46.1.  It is possible that BIRD46.1 will be up for
 a vote at the next meeting.

 AR - Matthew Flora issue BIRD44.1 to include references to the .pkg file
 and .ebd file and to change the limitation from 64 total characters to
 a <filename> limit of 20 characters.


 NEXT MEETING:
 The next meeting is the European EIA IBIS Summit in Paris, France on Monday,
 February 26, 1998.  No teleconference connection is planned.

 The next teleconference meeting is on Friday, March 13, 1998, 8:00 A.M. to 
 9:55 A.M.  BIRD46.1 may be scheduled for a vote.
 ==============================================================================
				       NOTES
 
 IBIS CHAIR: Bob Ross (503) 685-0732, Fax (503) 685-4897
	     bob_ross@mentorg.com
	     Modeling Engineer, Interconnectix BU of Mentor Graphics
	     8005 S.W. Boeckman Road, Wilsonville, OR 97070

 VICE CHAIR: Syed Huq (408) 721-4874, Fax: (408) 721-4785
	     huq@rockie.nsc.com
	     Staff Applications Engineer, National Semiconductor, M/S A-2595
	     2900 Semiconductor Drive, Santa Clara, CA 95052
 
 SECRETARY:  Stephen Peters (503) 264-4108, Fax: (503) 264-4515
	     sjpeters@ichips.intel.com
	     Senior Hardware Engineer, Intel Corporation
	     M/S JF1-56
	     2111 NE 25th Ave. 
	     Hillsboro, Oregon 97124-5961

 LIBRARIAN:  Jon Powell (805) 988-8250, Fax: (805) 988-8259
	     jonp@qdt.com
	     Senior Scientist, Viewlogic (formerly Quad Design)
	     1385 Del Norte Rd., Camarillo, CA 93010
  
 This meeting was conducted in accordance with the EIA Legal Guides and EIA
 Manual of Organization and Procedure.
 
 The following e-mail addresses are used:

   ibis-request@eda.org
       To join, change, or drop from either the IBIS Open Forum Reflector
       (ibis@eda.org), the IBIS Users' Group Reflector (ibis-users@eda.org)
       or both.  State your request.

   ibis-info@eda.org
       To obtain general information about IBIS, to ask specific questions
       for individual response, and to inquire about joining the EIA-IBIS
       Open Forum as a full Member.

   ibis@eda.org
       To send a message to the general IBIS Open Forum Reflector.  This
       is used mostly for IBIS Standardization business and future IBIS
       technical enhancements.  Job posting information is not permitted.

   ibis-users@eda.org
       To send a message to the IBIS Users' Group Reflector.  This is 
       used mostly for IBIS clarification, current modeling issues, and
       general user concerns.  Job posting information is not permitted.

   ibischk-bug@eda.org
       To report ibischk2 parser bugs.  The Bug Report Form Resides on
       eda.org in /pub/ibis/bugs/ibischk/bugform.txt along with reported bugs.

       To report s2ibis, s2ibis2 and s2iplt bugs, use the Bug Report Forms
       which reside under eda.org in /pub/ibis/bugs/s2ibis/bugs2i.txt, 
       /pub/ibis/bugs/s2ibis2/bugs2i2.txt, & /pub/ibis/bugs/s2iplt/bugsplt.txt
       respectively.

 Information on IBIS technical contents, IBIS participants, and actual
 IBIS models are available on the IBIS Home page found by selecting the
 Electronic Information Group under:

   http://www.eia.org

 Check the pub/ibis directory on eda.org for more information on previous 
 discussions and results.  You can get on via FTP anonymous.
 
 "IBIS Spoken Here" placards are available from Jon Powell (jonp@qdt.com) for 
 use at trade shows.
 ==============================================================================


 
From owner-ibis  Mon Feb 23 08:36:29 1998
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Date: Mon, 23 Feb 98 08:26:00 PST
From: Arpad Muranyi <Arpad_Muranyi@ccm.fm.intel.com>
Message-ID: <Mon, 23 Feb 98 08:28:21 PST_5@ccm.fm.intel.com>
To: ibis@eda.org, WeberChuang@via.com.tw
Subject: Re[2]: dual curve issue for input pad


Text item: 

Weber,

It is true that we do not have something like that in IBIS, but I am currently 
working on BIRD 45 in which we are addressing this kind of needs.  Could you 
please give me a beter description of these I-V curves so I could consider these
when I write the BIRD?

Thanks,

Arpad Muranyi
==============================================================================

Weber Chuang wrote:

>     I am currently involved in the design of a I/O pad and building
IBIS
> for it, but I am facing some troubles, my I/O
> pad has dual I/V curves while in input mode, that is, the I/V curves
for
> rising input and falling input  are
> different. IBIS seems to not supporting this kind of design, and
s2ibis2
> will not generate correct model for this. Is
> there any workaround? Any comment is welcome.

Are you talking about a hysteresis-like feedback characteristic, such as
a bus-hold circuit?

If so, IBIS doesn't do it.  Both because it doesn't handle input I/V
curves that change, and because bus-hold input curves are non-monotonic
which can create problems for the simulator.

(Someone correct me if I'm wrong or if version 3 changes this.)

Regards,
Andy Ingraham

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Date: Wed, 18 Feb 1998 11:41:51 -0500
Subject: RE: dual curve issue for input pad
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From: Andrew Ingraham <Andrew.Ingraham@digital.com>
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