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Dear colleagues,
As you saw in the minutes of the OOVHDL Study Group meeting last week, a
process for reviewing the SUAVE and Objective VHDL proposals was agreed
to. A description of the process is included below.
The first step in the process is to call for nominations for the three
review panel members. The criteria for reviewers are that
- they be expert in the definition of the VHDL standard and in
application of VHDL,
- they not be a member of a development team or a sponsoring
organization of either proposal.
Members nominated to date are:
Paul Menchini confirmed
John Willis confirmed
Dough Dunlop subject to confirmation
Dave Barton subject to confirmation
Jacques Rouillard confirmed
Alain Fonkoua confirmed
Wolfgang Ecker confirmed
Janick Bergeron subject to confirmation
Please forward additional nominations to me by email by 5pm US-PDT Fri 2
Jul. It would help if you could check first that your nominee is
willing to participate according to the rules of the process.
Next week, I will circulate a list of nominees and call for a vote.
Thanks.
Cheers,
PA
--
Dr. Peter J. Ashenden Email: petera@cs.adelaide.edu.au
Dept. Computer Science peter.ashenden@acm.org
University of Adelaide peter.ashenden@computer.org
Adelaide, SA 5005 Phone: +61 8 8303 4477
Australia Fax: +61 8 8303 4366
WWW: http://www.cs.adelaide.edu.au/~petera (includes PGP public key)
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DASC Object-Oriented VHDL Study Group
Process for Review of SUAVE and Objective VHDL Proposals
25 June 1999
Peter Ashenden and Wolfgang Nebel
Co-Chairs
Preamble
--------
The Object-Oriented VHDL (OOVHDL) Study Group has been studying the
issue of object-oriented extensions to VHDL to improve its modeling
support. The scope and purpose of the work is summarized in the
proposed PAR for a Trial Use Standard:
Purpose
Object-oriented and generic modeling offer mechanisms for
abstraction and encapsulation of descriptions of designs and
testbenches, and thus provide significant potential for reuse. VHDL
currently lacks many features for these styles of modeling, which are
important for managing the increasing complexity of design
descriptions. The overall goal is to increase the productivity of
electronic system design engineers.
Scope
To define new language features and to extend existing language
features of VHDL to allow object-oriented and generic modeling of
electronic systems. Among the approaches to be considerd are:
expression of abstract data types, including encapsulated data and
applicable operations; inheritance of data and operations;
polymorphism of objects; and genericity of types.
This proposed PAR has yet to be voted on within the Study Group.
The Study Group has been presented with two proposals for
object-oriented extensions to VHDL. SUAVE has been proposed by Peter
Ashenden of the University of Adelaide and Phil Wilsey of the
University of Cincinnati. Objective VHDL has been proposed by
Wolfgang Nebel of the OFFIS Research Institute, University of
Oldenburg.
The Study Group sought to merge aspects of the two proposals into a
single language proposal for use as the basis of the Trial Use
Standard. To this end, the proposers worked together to identify
common aspects of SUAVE and Objective VHDL. Their conclusion what
that, thought here are many aspects that are in common, or that could
be merged, there is a basic aspect that is irreconcilable, namely the
language mechanism used to define classes, encapsulated data and
methods.
In order to make progress towards a Draft Trial Use Standard, the
Study Group will follow a process, defined in this document, to choose
between the two language proposals.
The Resolution Process
----------------------
The Study Group will seek the advice of a panel of three distinguished
experts.
Members of the panel shall be expert in the definition of the VHDL
standard and in application of VHDL. A person who is a member of a
development team or a sponsoring organization of either proposal shall
not be eligible to be a member of the panel.
Candidates for the panel shall be nominated by members of the Study
Group. A nominated candidate shall agree to participate according to
this process to be eligible to be a member of the panel.
Should there be more than three eligible nominees, the members of the
Study Group shall vote for three members using an approval voting
scheme.
The panel will be presented with the following documents, delivered by
email and published on the OOVHDL Study Group Web page:
1. A Language Description Document for the SUAVE proposal (prepared by
the SUAVE proposers),
2. A Language Description Document for the Objective VHDL proposal
(prepared by the Objective VHDL proposers),
3. A Language Comparison Document comparing the proposals (prepared
jointly by both proposers),
4. Supplemental Material for the SUAVE proposal (tutorials, design
case studies, tools, etc, prepared by the SUAVE proposers),
5. Supplemental Material for the Objective VHDL proposal (tutorials,
design case studies, tools, etc, prepared by the Objective VHDL
proposers),
At a later date, the panel will be presented with the following
additional documents, delivered by email and published on the OOVHDL
Study Group Web page:
0. User Requirements Document (prepared by the requirements
subcommittee convened by Greg Peterson),
6. A Critique of the SUAVE proposal (prepared by the Objective VHDL
proposers), and
7. A Critique of the Objective VHDL proposal (prepared by the SUAVE
proposers).
The members of the panel shall jointly consider the material in the
documents, and prepare answers to the following questions for each
proposal:
Q0. To what extent does the proposal address the user requirements
identified in Document 0?
Q1. Is the proposal a strict superset of VHDL?
Q2. Is the proposal semantically consistent with VHDL?
Q3. Is the proposal consistent with VHDL syntax?
Q4. Is the proposal completely defined?
(Note: Q1 to Q4 are the questions that were put to the "Opal vs. Jade"
review panel in the P1076.1 Working Group, with the omission of the
question that the reviewers identified as the dual of Q1.)
There shall be a meeting of the Study Group at which the proposers may
give oral presentations of their documents and rebuttals of the
critiques, and shall respond to oral and written questions from the
attendees and the review panel. The review panel shall then present
its answers to the questions, with rationale, and shall recommend
which proposal would best serve as the basis for object-oriented
extensions to VHDL.
Subsequent to the latter meeting, the Study Group shall vote by email
on which proposal to use as the basis for object-oriented extensions
to VHDL. The vote shall be limited to members who, at the time, are
paid-up members of DASC.
Schedule
--------
Nominations for panel members: 5pm US-PDT Fri 2 Jul, 1999
Vote on panel members (if needed): 5pm US-PDT Fri 9 Jul, 1999
Publication of Documents 1 to 5: 5pm US-PDT Fri 9 Jul, 1999
Publication of Document 0 & Critiques: 5pm US-PDT Fri 6 Aug, 1999
Meeting (with FDL, Lyon, France): 9am-1pm, Thu 2 Sep, 1999
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