Subject: Re: New vote on SUAVE or Objective VHDL
From: John Michael Williams (jwill@pacbell.net)
Date: Mon Jun 26 2000 - 11:34:42 PDT
Resend: I replied only to Mark. --jmw
Hi Mark.
Mark Zwolinski wrote:
>
> John Michael Williams wrote:
> >
>
> (... Long exchange of views deleted...)
>
> Dear all,
>
> This is degenerating into an argument that will leave most readers cold.
>
> There's some truth to what both parties are saying. It might be helpful
> to recall a parallel.
>
> The work on analogue extensions to VHDL started in circa 1991. This work
> was getting stuck in a rut. There were prototype implementations of
> ideas (one of which was actually marketed). In about 1995, the working
> group made a call for proposals (i.e. draft standards) to get the
> process started again. Two proposals came forward. They were read and
> voted on by the discussion group. A standard then emerged and was agreed
> last year. The commercial implementations of VHDL-AMS are all complete
> reimplementations.
>
> It seems to me that almost exactly the same process is happening with
> OOVHDL. I have some misgivings about what is in both proposals. Having
> now tried to write VHDL-AMS models, I have some criticisms of that
> standard. Those doubts did not emerge until working implementations of
> the software were released. Realistically, whatever results from the
> OOVHDL work, its strengths and weaknesses will not be clear until people
> start using it for real. We need the prototypes to try out ideas, but I
> hope the prototypes will be ditched once the ideas are worked out.
>
> The alternative to this process is to do what the Verilog guys do and
> write a standard as a small group then send it out fully-formed into the
> world. You get a standard that way; the EDA vendors can then release
> tools very soon after the standard is approved, but it won't necessarily
> reflect the ideas of the wider community. I much prefer the way that
> VHDL standards are worked out and I think the OOVHDL work is following
> that pattern.
> ...
Yet another "the" alternative would be not to consider running
code at all. But, you are making a good suggestion.
I don't think Verilog was intended to be a standard: It
was intended to be a commercial product superior to any other
at that time. It was intended to be sole property
of a simulator vendor. Only later, after complaints of
noninteroperability and maybe noncompetition, was (is) Verilog
mildly polished by IEEE, with cooperation of Cadence, into
a standard.
Because VHDL already is widely used, and this group is attempting to
enhance it, not invent it de novo, if we have to look at an analogy,
we should be looking at AMS to VHDL (thanks to Mark), or SDF to
Verilog, rather than Verilog vs VHDL. Also, in the AMS & SDF cases,
the enhancement was addition of functionality (analogue;
backannotation). OO adds no functionality at all: It makes the
language easier to use, reduces error rate, and improves reuse.
These are (or, should be) because of the new language features
available to achieve a given simulator or synthesizer output.
I am happy to hear from Mark on this. It's a good point;
I have not been involved in AMS and was not aware of the
history.
Let me amend my proposal: We vote as proposed. If a valid
choice emerges for one of the two prototypes, then the
requirements document for the choice will be reduced to a
draft standards document (or part of one) for OO VHDL,
and no further running code shall be presented to the group
unless to prove contradiction(s) within the standard.
--
John
jwill@pacbell.net
John Michael Williams
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