Subject: Re: e-mail discussion on review report
From: Ronald Waxman (r.waxman@computer.org)
Date: Sun Mar 26 2000 - 17:34:18 PST
I would like to support the direction that Peter is advocating for VHDL
extensions.
At 06:23 PM 03/26/2000 +0930, Peter J. Ashenden wrote:
>Jean Mermet wrote:
> >
> > To be very clear I want to say that I support 100% the position of Wolfgang
> > which is not provocative but very reasonable:
>
>Indeed, Wolfgang's argument was reasonable. I don't think he meant to
>be provocative in the sense of being inflamatory, but rather sought to
>stimulate discussion. I'm pleased he succeeded!
Agree.
> > -1- VHDL is not the language needed at system level
>
>Again, I ask, what do we mean by "system level"? If we mean the level
>at which people who call themselves Systems Engineers operate, I agree.
>If we mean the level of expressing function in terms of algorithms and
>structure in terms of interconnected IP cores, processors, memories,
>buses, ICs, etc, then I think VHDL can be the language. People are
>already using it at this level of modeling. What we seek to do in
>adding object-orientation and other features is to improve the
>expressiveness of VHDL at this level, as well as at lower levels.
I fully support Peter's definition of System Level. VHDL has been designed
to do those very things and needs some fine tuning to achieve those
necessary goals. Leading-edge designers are using VHDL today for such
operations. They have ideas to improve VHDL to do these things better and
simpler.
> > -2- Extending VHDL towards an hypothetical system level other language
> > makes no sense before that language is defined
>
>I agree. Extending VHDL to bridge towards some system-level language
>was not my intention in developing SUAVE. I don't believe it was
>Wolfgang's either.
I have said that we should provide facility in VHDL to interface to other
languages. I overstated that capability by making it seem that we could
bridge to a language that has not as yet been defined. Of course we
cannot. However, facilities can be added to VHDL so that bridging to other
paradigms can be addressed as the other languages come along. This we
should do.
> > -3- Adding abstract data types would make sense but was refused during the
> > initial steps of the VHDL standardisation
>
>That was nearly 15 years ago. Since then, object-orientation has become
>widely accepted as a paradigm for analysis and design of systems.
>Abstract data types are fundamental to object orientation. I think it
>is time now to revisit the decision to omit abstract data types, and to
>include them as part of a suite of language features for
>object-orientation. Evidently the users surveyed as part of the REQUEST
>project think so too, since they strongly supported development of
>object-oriented extensions to VHDL.
Peter is right on here. In 1983 we did not even know how to do behavior
and structure in one language until we did it in VHDL. We must look anew
at abstract data types now that they are accepted by the design community.
> > -4- This has deprived VHDL of a definitive advantage to VERILOG
> (although in
> > Europe VHDL is prefered anyway)
>
>I do not believe that this is the reason why Verilog is preferred over
>VHDL by many users (at least in US and Japan). The most common reason I
>have heard is that Verilog users consider VHDL too verbose. Most
>Verilog users prefer not to have any type system, let alone one that
>supports ADTs!
VHDL's strong typing is a feature that must be preserved. The verbosity is
only noticed by those who must use the whole language (e.g.
consultants). Most designers work within a smaller segment of the
languages capability, and find it easy to pass their design models onto the
next level. Strong typing may result in more care (time) in the first pass
design, but the number of passes can be significantly reduced because of
this feature.
> > -5- Finding a reasonable extension to facilitate synthesis and re-use
> is a good
> > and immediately beneficial goal
>
>I agree 150%. In those areas of semantic mechanism common to SUAVE and
>Objective VHDL (namely, object-oriented data classes), both languages
>support synthesis and reuse almost equivalently. The only minor
>difference is that SUAVE, as reviewed, does not allow variables of
>class-wide type. However, I have indicated that this can and should be
>reviewed, to provide similar semantics for class-wide variables to those
>in Objective VHDL.
Amen!!
>In the area of type-generics (supported by SUAVE but not by Objective
>VHDL), synthesis is not affected, and reuse is substantially enhanced.
>Binding of actual types to formal types in instantiation of design
>entities and packages is done at elaboration time. Hence, for each
>instance, the types are fully bound in the elaborated model, which is
>used as the input to synthesis. It is feasible to write a preprocessor
>that does instantiation of type-genericized modules and writes out VHDL
>without type-generics. This would provide a link to existing synthesis
>tools, in the same way that the Objective VHDL to VHDL translator does
>for Objective VHDL.
>
>
>In summary, while I have minor disagreements with some of your points,
>we agree on the more significant points.
>
>Cheers,
>
>PA
>--
>Dr. Peter J. Ashenden Email: petera@cs.adelaide.edu.au
>Dept. Computer Science peter.ashenden@acm.org
>University of Adelaide peter.ashenden@computer.org
>Adelaide, SA 5005 Phone: +61 8 8303 4477
>Australia Fax: +61 8 8303 4366
>
>WWW: http://www.cs.adelaide.edu.au/~petera (includes PGP public key)
I intend my comments to be constructive. I hope they are taken as such.
Ron
-------------------------------------------------------------------->>>>
Ronald Waxman r.waxman@computer.org
EDA Standards Consulting voice: (+1)(703) 620-2117
Principal Scientist at UVa, retired fax: (+1) (703) 620-6716
2369 Paddock Lane mobile: (+1) (703) 509-0372
Reston, VA 20191-2607
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