e-mail discussion on review report


Subject: e-mail discussion on review report
From: Jean Mermet (Jean.Mermet@imag.fr)
Date: Sat Mar 25 2000 - 14:28:11 PST


To be very clear I want to say that I support 100% the position of Wolfgang
which is not provocative but very reasonable:
-1- VHDL is not the language needed at system level
-2- Extending VHDL towards an hypothetical system level other language
makes no sense before that language is defined
-3- Adding abstract data types would make sense but was refused during the
initial steps of the VHDL standardisation
-4- This has deprived VHDL of a definitive advantage to VERILOG (although in
Europe VHDL is prefered anyway)
-5- Finding a reasonable extension to facilitate synthesis and re-use is a good
and immediately beneficial goal

This summarises the position that ECSI is ready to promote
Jean

Dear all,

after those hot discussions in the past, I am very surprised about the
silence on the net after the circulation of Paul's review report. In order
to stimulate the discussion a bit, let post my maybe provocative
interpretation of the report:

Both proposals have significant pros and cons.

Both require a lot of clarification in details.

Both meet many aspects of the Greg's requirement doc.

Both need extensions:
         - e.g. SUAVE: entity/architecure objects,
        - e.g. Objective VHDL: genericity.

SUAVE targets the system level and abstract data modelling.

Objective VHDL targets electronic hardware design and synthesizability.

As stated in our comments on the report, we do not fully agree with all
assessments of Paul, e.g. the difficulty to implement, to prove this you
can download our translator from the web.

In the discussion the group should avoid to get lost in many detailed
technical issues but concentrate on the global picture, i.e. the position
and scope the group sees for VHDL in the electronic system design world.

- Should it become a system level language?
  (N.b. if you like ADA style for this, why not use ADA95 for system level?)
- Should it support a seamless path to hardware, i.e. should it be
synthesizable?

As I said: certainly provocative and not unbiased,

looking forward to a vivid discussion,

best regards,

Wolfgang
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________________________________________________________________________

Jean Mermet * e-mail: Jean.Mermet@imag.fr
Laboratoire-TIMA, INPG * or: jeanm@ecsi.alpes-net.fr
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