Subject: Re: e-mail discussion on review report - VHDLOO
From: Peter Ashenden (petera@cs.adelaide.edu.au)
Date: Sun Mar 12 2000 - 15:08:50 PST
Kamal.Hashmi@icl.com wrote:
>
> As I have said before, I regard OO extensions as enhancing the
> infrastructure of the language - not just the higher levels
> should become easier but every level should also benefit.
I agree.
> However, the problem with OO is mainly with the level of
> training and intelligence required to use it effectively.
> In the software case, I have rarely seen any OO program which
> makes sensible use of inheritance beyond one level. Many
> even fail to make good use of encapsulation and data abstraction.
> Now, in software, one can survive with crap code which doesn't
> work the first time, or on the first few iterations, because
> you can always hack the code.
Yes, but taking this approach increases development cost.
> Indeed I suspect that computer
> science courses nowadays teach students to produce a
> nearly-working program as fast as possible, and then pile on
> unstructured fixes afterwards.
We don't teach that approach, though many of our students adopt it
despite us!
> For hardware and for systems,
and for software!
> we have to help the engineer in designing a quality system
> which will not only work the first time but also be easy to
> maintain, reuse and refine. So ... do we need to dumb down
> our HDLs from .303s to .22s, or give the kids bazookas ? It's
> the old discussion:
> (capability & flexibility) + (smart engineer) = better products
> (capability & flexibility) + (dumb engineer) = no products
> (capability & flexibility) + (ordinary engineer) = ????
> I seem to be getting off the subject here.
Indeed!
> There are people who argue that no HDL can ever be a system
> design language - or should ever try to be one. And sometimes
> I almost believe them - but what do they propose ? UML ? C ?
> C++ ? In my opinion, the biggest single advantage of HDLs is
> that their users expect to create a product that works the
> first time or very nearly so. Most software design cycles
> (especially C-based ones) depend heavily on debugging the final
> product - and this is not acceptable for a system design cycle.
You might be interested in current thinking and (hopefully) practice in
software engineering - reliable and repeatable software development with
zero defect tolerance. The aim is to identify systemic sources of
defects and to remove the sources. But again, this is tangential.
> A big problem with VHDL is that any system langauage based on it
> is unacceptable to Verilog users - maybe the merger of OVI and VI
> will come up with an idea.
Don't hold your breath.
Cheers,
PA
-- Dr. Peter J. Ashenden Email: petera@cs.adelaide.edu.au Dept. Computer Science peter.ashenden@acm.org University of Adelaide peter.ashenden@computer.org Adelaide, SA 5005 Phone: +61 8 8303 4477 Australia Fax: +61 8 8303 4366WWW: http://www.cs.adelaide.edu.au/~petera (includes PGP public key)
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